JPH10270666A - Semiconductor element with pad layer and forming method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a self-aligning pad layer. SOLUTION: The semiconductor element is constituted while having gates 55 formed onto a semiconductor substrate 51 in an irregular shape, spacers 57b formed onto the side walls of the gates 55, source/drain shaped onto the semiconductor substrate 51, first inter-gate regions filled with the spacers 57b among the gates 55 and a second inter-gate region filled with the self-aligning pad layer 59. An element isolation film 53 is formed onto the semiconductor substrate 51 to define an active region and an inactive region, and the irregular gates 55 are formed onto the semiconductor substrate 51, to which the element isolation film 53 is shaped. The spacers 57b are formed onto the side walls of the gates 55 by using an insulating substance, the inter-gate regions are partitioned into the first inter-gate regions filled with the spacers 57b and the second inter-gate region not filled with the spacer 57b, the sources/drains are formed onto the semiconductor substrate 51, and the self-aligning pad layer 59 is formed only by vapor deposition and etchback processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a pad layer and a method for forming the same.

[0002]

2. Description of the Related Art With the high integration of semiconductor devices, the size of patterns is required to be submicron or less, and particularly to a limit level exceeding the limit of photo process. In addition to this, the cell capacitor also moves from the planar structure to the COB through the stack.
(COB; Capacitor On Bit-line) mechanism is changing.

In the COB mechanism, since a capacitor is formed after a bit line is formed, in order to form a buried contact for connecting a storage electrode and a source, the bit line cannot directly pass over the active region. You will avoid it. In this state, the pad layer connects these between the bit line and the active region.

However, since the design rule of the process of forming the pad layer is small, the photo and etching techniques are limited. FIG. 1 is a layout showing an active region mask pattern 21 and a gate mask pattern 23 that limit an active region by a conventional technique. The active region mask pattern 21 is a cross pattern having arms extending in the horizontal and horizontal directions, respectively. Each of the horizontal and vertical arms has a predetermined width, and the cross patterns are alternately arranged.

The gate mask pattern 23 is a pattern of the active region mask pattern 21 that crosses both arms in the horizontal direction along the vertical direction, and the distance from each gate mask pattern 23 is constant. 2 to 5 are cross-sectional views illustrating a method of forming a pad layer of a semiconductor device using the mask pattern of FIG.

In the drawings, reference numeral 1 is a semiconductor substrate,
3 is an element isolation film, 5 is a gate, 7a is an insulating film,
b indicates a spacer, 9 and 9a indicate interlayer insulating layers, 11 indicates a first photosensitive film pattern, 13 indicates a conductive layer, 13a indicates a pad layer, and 15 indicates a second photosensitive film pattern. . Referring to FIG. 2, an element isolation process is performed on the semiconductor substrate 1 using the active area mask pattern 21 of FIG. 1, thereby forming an element isolation film 3 in an inactive area except an active area. Next, a gate 5 having a conductive layer / gate oxide film structure is formed on the semiconductor substrate 1 using the gate mask pattern 23 of FIG. An insulating material is deposited on the entire surface of the semiconductor substrate 1 on which the gate 5 is formed, and then etched back to form an insulating film 7a on the gate 5 and a spacer 7b on the side wall of the gate. Then, a source / drain (not shown) is formed by ion implantation into the semiconductor substrate 1, and a process of forming a transistor including the source / drain and the gate 5 is sequentially performed.

The device isolation process is performed by using a conventional method, that is, LOCOS or trench device isolation method. Therefore, a cross-shaped active region is formed in the semiconductor substrate 1. Next, an insulating material is deposited on the entire surface of the semiconductor substrate 1 on which the transistor is formed to form an interlayer insulating layer 9. After depositing a photoresist layer (patterned on the first photoresist layer pattern 11 in a subsequent process) on the interlayer insulating layer 9, a portion of the photoresist layer corresponding to the source / drain is etched to form a first layer. The process of forming the photosensitive film pattern 11 is performed.

Referring to FIG. 3, the interlayer insulating layer 9 is etched using the first photoresist pattern 11 as a mask to form an interlayer insulating layer 9a. Next, the first photosensitive film pattern 11 is removed. Referring to FIG. 4, a step of depositing a conductive material on the semiconductor substrate 1 on which the interlayer insulating layer 9a is formed to form a conductive layer 13, and a step of forming a photosensitive film on the conductive layer 13 (a second step in a subsequent step). Then, a patterning is performed so that a portion corresponding to the source / drain remains, and a process of forming the second photosensitive film pattern 15 is performed.

Referring to FIG. 5, the conductive layer 13 is etched using the second photoresist layer pattern 15 as a mask to form a pad layer 13a between the gate layer 5 and the gate 5. Next, the second photoresist pattern 15 is removed.

[0010]

In the above, after forming a contact hole between gates, a photolithography process is performed twice in order to form a pad layer filling the contact hole. In addition, the width of the second photosensitive film pattern for forming the pad layer and the distance between the second photosensitive film patterns are too small, so that the pad layer is bridged, the photosensitive film pattern is broken, and a pad layer having a desired pattern cannot be formed. A problem has arisen.

A first object of the present invention is to provide self-alignment (Self-A
lign) to provide a semiconductor device having a pad layer. A second object of the present invention is to provide a method of forming the semiconductor device.

[0012]

According to one aspect of the present invention, there is provided a semiconductor device comprising: a gate formed on a semiconductor substrate in an uneven shape; a spacer formed on a side wall of the gate; The formed source / drain, the first inter-gate region in which the space between the gates is filled with the spacer, and the second region in which the self-aligning pad layer is filled between the gates.
And an inter-gate region of.

The pad layer is element-isolated by the first inter-gate region. According to another aspect of the present invention, an isolation layer is formed on a semiconductor substrate to define an active region and an inactive region. An uneven gate is formed on the semiconductor substrate on which the device isolation film is formed, across the semiconductor substrate. By forming a spacer on the side wall of the gate using an insulating material, the inter-gate region is divided into a first inter-gate region filled with the spacer and a second inter-gate region not filled with the spacer. A source / drain is formed on the semiconductor substrate. A self-aligning pad layer is formed in the second inter-gate region by performing only a deposition and etch-back process without performing a photolithography process on the semiconductor substrate on which the gate and the source / drain are formed.

In the semiconductor device having the pad layer and the method of forming the same according to the present invention, the self-aligning pad layer can be formed without performing the photo process by using the uneven gate mask, and further, the cell array. When a pad layer with a small design rule is formed on a semiconductor substrate having a portion and a peripheral circuit portion, a cell array with a large design rule and a large photo margin, an open or close (openor close) photo, and an overall etch-back process Has the advantage that the self-aligning pad layer can be formed by a simpler process.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. (Embodiment 1) FIG. 6 shows a semiconductor device having a pad layer according to the present invention. Gates 55 having different widths are formed on the semiconductor substrate 51, and spacers 57b made of an insulating material are formed on side walls of the gates 55.

The region between the gates 55 is the spacer 5
The region is divided into a first inter-gate region h filled with 7b and a second inter-gate region k filled with the self-aligning pad layer 59. At this time, the width of the first inter-gate region h and the width of the second inter-gate region k are different from each other, and the pad layer 59 is isolated from adjacent cells by the first inter-gate region h.

FIG. 7 is a layout showing an active region mask pattern 31 and a gate mask pattern 33 according to the present invention. The active region mask pattern 31 is a cross-shaped pattern having arms extending in horizontal and vertical directions, respectively, and the horizontal and vertical arms have predetermined widths, respectively. Here, the cross patterns are alternately arranged as shown in FIG.

The gate mask pattern 33 traverses vertically from both horizontal arms of the cross-shaped mask pattern 31 and has an uneven shape. The gate mask pattern 33 is formed in this way to isolate adjacent cells from each other. If a pad layer is formed between the gates by a self-aligning method using the gate mask pattern 33, that is, a method of depositing a conductive material on a semiconductor substrate on which the gates are formed and then etching back, the adjacent pad layers are formed. There is a disadvantage that the pad layers of the cells come into contact with each other and the elements are not separated. Therefore, the gate mask pattern 33 should be aligned such that the width of the inter-gate region filled with the pad layer is different from the width of the inter-gate region not filled with the pad layer. For example, the width of the inter-gate region filled with the pad layer is made larger than that of the inter-gate region without the pad layer, and the width of the inter-gate region without the pad layer is smaller than the thickness of the spacer formed on the side wall of the gate. Should be less than twice.

In short, the gate mask pattern 33
Is such that when a spacer is formed on the side wall of a gate, an inter-gate region to be filled with the spacer and an inter-gate region not to be formed are generated. 8 to 12 are layout diagrams of semiconductor devices sequentially obtained by the method of the present invention.

FIGS. 13 to 16 are sectional views corresponding to VIII to XVI in FIGS. 8 to 11, and FIG.
20 to 20 are sectional views corresponding to XVII to XX of FIGS. 8 to 11, and sequentially showing a method of forming a pad layer of a semiconductor device according to the present invention. In the figure, reference numeral 51 is a semiconductor substrate, 53 is an element isolation film, 55 is a gate, 57a is an insulating film, 57b is a spacer, and 59 is a pad layer.

Referring to FIGS. 8, 13 and 17, the semiconductor substrate 5 is formed using the active region mask pattern 31 of FIG.
Then, an element isolation process is performed on the device 1. In the device isolation step, a LOCOS or trench device isolation method is usually used. Therefore, an element isolation film 53 is formed on the semiconductor substrate 51, and the semiconductor substrate 51 is divided into an active region 91 and an inactive region 93 as shown in FIG. Is slightly gentle without the active region mask pattern 31 appearing as it is.

Referring to FIGS. 9, 14 and 18, a gate oxide film (not shown) and a gate conductive layer (not shown) are sequentially deposited on the semiconductor substrate 51, and then, using the gate mask pattern 33 of FIG. Etching forms a gate 55 with a gate conductive layer / gate oxide mechanism. As shown in FIG. 9, the gate 55 has a concave-convex shape formed by horizontally traversing the semiconductor substrate 51 from both horizontal arms of the active region 91.

As a result, a first inter-gate region h and a second inter-gate region k having different widths appear between the gates 55. This is the part where the pad layer is formed in the process. The first inter-gate region h is filled with a spacer in a subsequent step to isolate adjacent cells from each other, and the width of the first inter-gate region h is equal to that of the second inter-gate region k. It should be formed smaller than the width, especially smaller than twice the spacer thickness.

Referring to FIG. 10, FIG. 15 and FIG.
An insulating material is deposited on the entire surface of the semiconductor substrate 51 and then etched to form an insulating film 57a on the gate 55 and a spacer 57b on the sidewall of the gate 55. As a result, the first inter-gate region h is filled with the spacer 57b, and the second inter-gate region k is filled with the semiconductor substrate 51.
The source / drain is exposed.

Referring to FIGS. 11, 16 and 20,
After performing an ion implantation step on the exposed semiconductor substrate 51 to form a source / drain (not shown), a pad layer 59 is formed in the second inter-gate region k. The pad layer 59 does not perform a photolithography process,
The use of an automatic alignment method, that is, a method of depositing a conductive material on the entire surface of the semiconductor substrate 51 and then etching back the entire surface, has the advantage of simplifying the process.

FIG. 12 shows a state in which the pad layer 59 is formed on the semiconductor substrate 51 by the method described above, and then the direct contact 95 and the buried contact 97 are formed. The direct contact 95 is a contact for connecting the drain to a bit line (not shown), and the buried contact 97 is for connecting the source to a lower electrode (not shown) of the capacitor.

(Embodiment 2) FIGS. 21 to 26 show another embodiment of the present invention, which sequentially shows a method of forming a pad layer on a semiconductor substrate divided into a cell array portion and a peripheral circuit portion. It is a figure. In the figure, reference numeral 101 denotes a semiconductor substrate, 103 denotes an element isolation film, 105 denotes a gate,
107, 107a, and 107c are insulating films, and 107b
And 107d denote spacers, 109 denotes a first photoresist pattern, 111 denotes a pad layer, and 113 denotes a second photoresist pattern.

Referring to FIG. 21, by performing an element isolation process on a semiconductor substrate 101 divided into a cell array portion A and a peripheral circuit portion B, the cell array portion A and the cell array portion A and the peripheral circuit portion B are separated from each other. Element isolation films 103a and 103b that define an inactive region at a boundary are formed. Then
A gate oxide film (not shown) and a gate conductive layer (not shown) are sequentially deposited on the semiconductor substrate 101 and then patterned using a gate mask to form a gate 105 having a gate conductive layer / gate oxide film structure.

At this time, the gate mask is formed of an uneven pattern in which the width between the gates 105 formed on the semiconductor substrate 101 is not uniform. That is, the width between the gates in the portion where the pad layer is formed on the semiconductor substrate is larger than the width between the gates in the portion where the pad layer is not formed. Particularly, a portion where the pad layer is not formed is a spacer (the gate 10
The width between the gates in the portion where the pad layer is not formed is smaller than twice the spacer thickness.

Referring to FIG. 22, the semiconductor substrate 10
1 to form an insulating film 107 by depositing an insulating material on the first photosensitive film pattern 1 and the first photosensitive film pattern 10 covering the peripheral circuit part B.
The step of forming 9 is advanced. The insulating film 107 is for forming a spacer on the sidewall of the gate 105.

Referring to FIG. 23, the insulating layer 107 is etched to form an insulating layer 107a on the gate 105.
A spacer 107b is formed on the side wall of the gate 105. As a result, in the cell array section A, an active region between the gates 105 is exposed.

Next, ion implantation is performed to form a source / drain (not shown) on the exposed semiconductor substrate 101. Referring to FIG. 24, a self-aligning pad layer is formed between the gates 105. In short, a conductive material is deposited on the entire surface of the semiconductor substrate 101 and then etched back to form a pad layer 111 filling the space between the gates 105.

Referring to FIG. 25, a step of removing the first photoresist layer pattern 109 and a step of forming a second photoresist layer pattern 113 covering the cell array portion A are performed. Next, a step of etching a pad layer remaining in the peripheral circuit portion B,
And an insulating film 107c is formed on the gate 105.
Then, the step of forming a spacer 107d on the side wall of the gate 105 is performed.

Referring to FIG. 26, the second photoresist pattern 109 is removed.

[0035]

The pad layer forming method described above has an advantage that the pad layer can be formed more simply by advancing the cell array open or close photo step and the full-scale etch back step which have a large design rule and a large photo margin. is there. The present invention is not limited to this,
Obviously, many variations are possible within the spirit of the present invention and by those having ordinary skill in the art.

[Brief description of the drawings]

FIG. 1 is a layout showing an active region mask pattern and a gate mask pattern that limit an active region according to a conventional technique.

FIG. 2 is a cross-sectional view illustrating a conventional method for forming a pad layer of a semiconductor device using the mask pattern of FIG.

FIG. 3 is a cross-sectional view illustrating a conventional method for forming a pad layer of a semiconductor device using the mask pattern of FIG. 1;

4 is a cross-sectional view shown for explaining a conventional method of forming a pad layer of a semiconductor device using the mask pattern of FIG.

5 is a cross-sectional view shown for explaining a conventional method of forming a pad layer of a semiconductor device using the mask pattern of FIG.

FIG. 6 illustrates a semiconductor device having a pad layer according to an embodiment of the present invention.

FIG. 7 is a layout showing an active region mask pattern and a gate mask pattern according to an embodiment of the present invention.

FIG. 8 is a layout diagram of semiconductor devices sequentially obtained by the method of the present invention.

FIG. 9 is a layout diagram of semiconductor devices sequentially obtained by the method of the present invention.

FIG. 10 is a layout diagram of semiconductor devices sequentially obtained by the method of the present invention.

FIG. 11 is a layout diagram of semiconductor devices sequentially obtained by the method of the present invention.

FIG. 12 is a layout diagram of semiconductor devices sequentially obtained by the method of the present invention.

FIG. 13 is a sectional view taken along line XVIII-XVIII in FIG. 8;

14 is a sectional view taken along line XIV-XIV in FIG.

FIG. 15 is a sectional view taken along line XV-XV in FIG. 10;

FIG. 16 is a sectional view taken along line XVI-XVI in FIG. 11;

FIG. 17 is a sectional view taken along line XVII-XVII in FIG. 8;

18 is a sectional view taken along line XVIII-XVIII in FIG.

19 is a sectional view taken along line XIV-XIV in FIG.

20 is a sectional view taken along line XX-XX in FIG.

FIG. 21 is a diagram showing another embodiment of the present invention, which is a method of forming a pad layer on a semiconductor substrate divided into a cell array portion and a peripheral circuit portion.

FIG. 22 is a view showing a method of forming a pad layer on a semiconductor substrate divided into a cell array portion and a peripheral circuit portion according to another embodiment of the present invention.

FIG. 23 is a view showing a method of forming a pad layer on a semiconductor substrate divided into a cell array portion and a peripheral circuit portion according to another embodiment of the present invention.

FIG. 24 is a diagram illustrating a method of forming a pad layer on a semiconductor substrate divided into a cell array portion and a peripheral circuit portion, which is another embodiment of the present invention.

FIG. 25 is a view illustrating a method of forming a pad layer on a semiconductor substrate divided into a cell array portion and a peripheral circuit portion according to another embodiment of the present invention.

FIG. 26 is a view showing a method of forming a pad layer on a semiconductor substrate divided into a cell array portion and a peripheral circuit portion according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 51 semiconductor substrate 53 element isolation film 55 gate 57a insulating film 57b spacer 59 pad layer

Claims (27)

[Claims] 1. A semiconductor device comprising: a first pattern formed on a semiconductor substrate; and a second pattern self-aligned with the first pattern. 2. The semiconductor device according to claim 1, wherein the second pattern is formed by using an etch back process after vapor deposition. 3. The semiconductor device according to claim 1, wherein the first pattern is a gate and the second pattern is a pad layer. 4. A gate formed in an uneven shape on a semiconductor substrate, a spacer formed on a side wall of the gate, a source / drain formed on the semiconductor substrate, and a space between the gate filled with the spacer. And a second inter-gate region filled with a self-aligning pad layer between the gates. 5. The semiconductor device according to claim 4, wherein the width of the first inter-gate region is different from the width of the second inter-gate region. 6. The width of the first inter-gate region is the second width.
5. The semiconductor device according to claim 4, wherein the width is smaller than the width of the inter-gate region of. 7. The semiconductor device according to claim 4, wherein the pad layer separates devices by the first inter-gate region. 8. A first step of forming an element isolation film on a semiconductor substrate to define an active region and an inactive region; and forming an uneven shape across the semiconductor substrate on the semiconductor substrate on which the element isolation film is formed. Forming a gate on the side wall of the gate using an insulating material, thereby filling the inter-gate region with the first inter-gate region and filling the inter-gate region with the spacer. A third step of forming a source / drain in the semiconductor substrate; and a fifth step of forming a self-aligning pad layer in the second inter-gate region. A method of forming a semiconductor device having a pad layer, comprising: 9. The method of claim 8, wherein in the first step, an active region is formed using a mask in which cross-shaped patterns are alternately arranged. 10. The method as claimed in claim 8, wherein in the second step, a gate is formed using a gate mask having an uneven pattern. 11. The distance from each pattern of the gate mask is different between a portion where a pad layer is formed on the semiconductor substrate and a portion where a pad layer is not formed on the semiconductor substrate. A method for forming a pad layer of a semiconductor device as described above. 12. The semiconductor device according to claim 11, wherein a distance between the gate mask and each pattern is larger in a portion where the pad layer is formed on the semiconductor substrate than in a portion where the pad layer is not formed. Pad layer forming method. 13. The semiconductor device according to claim 8, wherein the width of the first inter-gate region is different from the width of the second inter-gate region.
A method for forming a pad layer of a semiconductor device according to item 1. 14. The method for forming a pad layer of a semiconductor device according to claim 13, wherein the width of the first inter-gate region is smaller than the width of the second inter-gate region. 15. The method of claim 8, wherein the width of the first inter-gate region is smaller than twice the thickness of the spacer. 16. The method for forming a semiconductor device having a pad layer according to claim 8, wherein the first inter-gate region isolates the pad layer from each other. 17. The method as claimed in claim 8, wherein the pad layer is formed by depositing a conductive material on the semiconductor substrate and then etching it back. 18. A step of forming an isolation layer on a semiconductor substrate divided into a cell array part and a peripheral circuit part to define active regions and inactive regions, and forming a gate on the semiconductor substrate. Depositing an insulating material on the semiconductor substrate having the gate to form an insulating layer; and depositing a first photoresist layer on the semiconductor substrate to expose only the cell array unit. Forming a first photosensitive film pattern covering the peripheral circuit portion by etching a first photosensitive film; and etching the insulating film in the cell array portion to form a spacer on a side wall of the gate. Forming a self-aligning pad layer on the semiconductor substrate of the cell array portion; removing the first photosensitive film pattern; and depositing a second photosensitive film on the semiconductor substrate. The above Forming a second photosensitive film pattern covering the peripheral circuit portion by etching the second photosensitive film so that only the array portion is exposed; and etching the insulating film in the peripheral circuit portion. And forming a spacer on the sidewall of the gate, and removing the second photoresist pattern, a method of forming a pad layer of a semiconductor device. 19. The method as claimed in claim 18, wherein the gate of the cell array is formed using a gate mask having a concavo-convex pattern. 20. The semiconductor device according to claim 19, wherein a distance between the gate mask and each pattern is different between a portion where the pad layer is formed on the semiconductor substrate and a portion where the pad layer is not formed. Pad layer forming method. 21. The semiconductor device according to claim 20, wherein a distance between the patterns of the gate mask is larger in a portion where the pad layer is formed on the semiconductor substrate than in a portion where the pad layer is not formed. Pad layer forming method. 22. The method according to claim 18, wherein the width of the first inter-gate region is different from the width of the second inter-gate region. 23. The method of claim 22, wherein a width of the first inter-gate region is smaller than a width of the second inter-gate region. 24. The method according to claim 18, wherein the width of the first inter-gate region is smaller than twice the thickness of the spacer. 25. The method of claim 18, wherein the first inter-gate region isolates the pad layer. 26. The method according to claim 18, wherein the pad layer is formed by depositing a conductive material on the semiconductor substrate and then etching back the conductive material. 27. The method of claim 18, wherein a step of etching the pad layer is added after forming the second photoresist pattern.