KR0151067B1 - Semiconductor device manufacturing method - Google Patents

Abstract

The present invention relates to a method for manufacturing a highly integrated semiconductor device, comprising the steps of sequentially forming an interlayer insulating film, an etch stop film and a first conductive layer on a semiconductor substrate, and forming a photoresist pattern having a predetermined size on the first conductive layer. Forming a spacer on the sidewalls of the photoresist pattern, forming a contact portion by sequentially etching the first conductive layer, the etch stop layer, and the interlayer insulating layer by applying the spacer as an etch mask; And removing the photoresist pattern to form a second conductive layer on the entire surface of the resultant, and forming a storage electrode by anisotropically etching the second conductive layer. Therefore, it is possible to overcome the limitations of the photolithographic process due to the improved degree of integration.

Description

Manufacturing method of highly integrated semiconductor memory device

1A to 1G are cross-sectional views illustrating a method of manufacturing a highly integrated semiconductor memory device according to the present invention.

* Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 10 interlayer insulating film

12: etch stop SE: storage electrode

18: dielectric film PE: plate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a highly integrated semiconductor memory device having a contact portion formed by a self-alignment method.

As the development of semiconductor manufacturing technology and the application field of memory devices are expanded, the development of large-capacity memory devices is progressing. In particular, one memory cell has one capacitor and one transistor. Significant developments in DRAM (Dynamic Random Access Memory), which is advantageous for high integration, have been made.

During the development of this DRAM, several trench type capacitor cells or stack type capacitor cells have been developed for 256b DRAM. The method of forming these capacitor cells is 1.5V despite the complicated process. As a result of evaluating a cell size of 0.5 μm ^2, the problem of insufficient cell capacitance is still emerging.

Furthermore, the layout of capacitor cells with sufficient alignment margins not only causes large steps on topography, but also makes it difficult to reduce the cells below 10F ² (where F Is the minimum feature size). Thus, difficulties in photolithography processes have emerged as another obstacle.

Accordingly, an object of the present invention is to provide a method for manufacturing a highly integrated semiconductor device capable of forming the contact portion below the limit of the photolithographic process by forming the contact portion by a self-alignment method in order to solve the problems of the prior art as described above. have.

A semiconductor memory device manufacturing method according to the present invention for achieving the above object,

Sequentially forming an interlayer insulating film, an etch stop film, and a first conductive layer on the semiconductor substrate;

Forming a photoresist pattern having a predetermined size on the first conductive layer;

Forming a spacer on sidewalls of the photoresist pattern;

Forming a contact portion by sequentially etching the first conductive layer, the etch stop layer, and the interlayer insulating layer by applying the spacer as an etch mask;

Removing the photoresist pattern and forming a second conductive layer on the entire surface of the resultant product;

And forming a storage electrode by anisotropically etching the second conductive layer.

In the production method according to the present invention, the spacer is preferably formed of an oxide.

In the manufacturing method according to the present invention, the first and second conductive layers are preferably formed of polycrystalline silicon.

Therefore, according to the method of manufacturing the memory device according to the present invention, the contact field forming process for connecting the storage electrode to the source of the transistor does not need to be performed separately, so that the limitation of the photolithography process can be overcome by improving the integration degree.

Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.

1A to 1G are process flowcharts showing a part of a method for manufacturing a highly integrated semiconductor device according to the present invention.

FIG. 1A illustrates a process of forming the interlayer insulating film 10, the etch stop film 12, and the first conductive layer 14, on a semiconductor substrate 100 on which transistors (not shown) are formed. For example, the step of forming the interlayer insulating film 10 by depositing an oxide film to a predetermined thickness, and the etch stop layer 12 to prevent excessive etching in the subsequent wet etching process on the interlayer insulating film 10. ) Is formed by, for example, depositing a nitride film to a predetermined thickness and by depositing a first conductive layer 14 on the etch stop film 12, for example, polycrystalline silicon doped with impurities to a predetermined thickness. Proceed to the process.

FIG. 1B illustrates a process of forming the photoresist pattern PR, which is a photoresist of a portion where a storage electrode is to be formed on the first conductive layer 14 through a process such as photoresist coating, mask exposure, and development. Proceeding to the process of forming a photoresist pattern (PR) of the desired size so that is removed.

FIG. 1C illustrates a process of forming the spacer SP, which is formed by applying an oxide film having a predetermined thickness to the entire surface of the resultant after the process of FIG. 1B and etching back to form the spacer SP as shown. Proceed to the process.

FIG. 1D illustrates a process of forming the contact portion CH. The first conductive layer 14, the etch stop layer 12, and the interlayer insulating layer 10 are continuously formed using the spacer SP as an etch mask. The etching proceeds to the process of forming the contact portion CH of the portion where the storage electrode is to be formed.

In this case, the size of the contact portion may be adjusted by adjusting the thickness of the photoresist pattern and the thickness of the oxide film for forming the spacer.

Here, the contact portion CH is self-aligned by a spacer, so that the contact portion CH can be formed up to the limit of the conventional photolithography process.

FIG. 1E illustrates a process of forming the second conductive layer 16. The first conductive process of FIG. 1D removes the photoresist pattern, and then the second conductive layer 16, for example, a polycrystal doped with impurities, is formed on the entire surface of the resultant. It proceeds to the process of forming by depositing silicon to predetermined thickness.

In this case, the second conductive layer is preferably deposited to completely bury the contact portion.

FIG. 1E illustrates a process of forming the storage electrodes SE 14 and 16 by etching back the entire surface of the resultant after the process of FIG. 1E. In this case, the etch back process may be performed using the spacer SP and the etch stop layer. 12) to reveal. The first conductive layer 14 may include a pillar-shaped second conductive layer 16 formed on the contact portion and a cylinder-shaped second conductive layer 16 formed on the first conductive layer 14. It is connected to form a storage electrode (SE).

FIG. 1g illustrates a process of forming the dielectric film 18 and the plate electrode PE, which are removed by the wet etching after the step 1f, and then the dielectric film 18 and the plate electrode are formed on the entire surface of the resultant. PE) For example, it proceeds to the process of forming polycrystalline silicon doped with impurities for example.

After the formation of the capacitor consisting of the storage electrode, the dielectric film and the plate electrode, a transistor (not shown) is formed to complete the DRAM.

It goes without saying that the present invention described above is not limited to the production of the DRAM, but can be extended and applied within the scope of the technical idea of the present invention.

As described above, the manufacturing method of the highly integrated semiconductor device according to the present invention is performed by a self-alignment method using a spacer instead of a direct etching process when forming a contact portion for forming a storage electrode, thereby performing photolithography according to an improvement in integration. The limitations of the process can be overcome.

In addition, since the spacer is formed on the sidewall of the photoresist pattern, it is easy to adjust the step difference of the storage electrode, so that a high capacitance value can be expected as the effective area increases.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (3)

Sequentially forming an interlayer insulating film, an etch stop film and a first conductive layer on the semiconductor substrate; Forming a photoresist pattern having a predetermined size on the first conductive layer; Forming a spacer on sidewalls of the photoresist pattern; Forming a contact portion by sequentially etching the first conductive layer, the etch stop layer, and the interlayer insulating layer using the spacer as an etch mask; Removing the photoresist pattern and forming a second conductive layer on the entire surface of the resultant product; And forming a storage electrode by anisotropically etching the second conductive layer. The method of claim 1, wherein the spacer is formed of an oxide. The method of claim 1, wherein the first and second conductive layers are formed of polycrystalline silicon.