CN113224061B

CN113224061B - Semiconductor memory device and method of forming the same

Info

Publication number: CN113224061B
Application number: CN202110495955.9A
Authority: CN
Inventors: 张钦福; 程恩萍; 冯立伟; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-05-07
Filing date: 2021-05-07
Publication date: 2023-06-06
Anticipated expiration: 2041-05-07
Also published as: CN113224061A

Abstract

The application discloses a semiconductor memory device and a method of forming the same, the semiconductor memory device including a substrate, an active structure, and shallow trench isolation. An active structure is disposed in the substrate and includes a first active region and a second active region. The first active region comprises a plurality of active region units, and the second active region is arranged outside the first active region and is directly connected with a part of the active region units, wherein the second active region comprises a plurality of first openings and is arranged on the side edge of the second active region. Shallow trench isolation is provided in the substrate surrounding the active structure.

Description

Semiconductor memory device and method of forming the same

Technical Field

The present disclosure relates to semiconductor memory devices and methods of forming the same, and more particularly, to a semiconductor memory device including an active structure and a shallow trench isolation and a method of forming the same.

Background

With the miniaturization of semiconductor devices and the complexity of integrated circuits, the size of devices is continuously reduced and the structure is continuously changed, so maintaining the performance of small-sized semiconductor devices is a major goal in the industry. In the semiconductor manufacturing process, a plurality of active regions are defined on a substrate as a basis, and then required components are formed on the active regions. Generally, the active regions are formed with a plurality of patterns on the substrate by using photolithography and etching processes, but under the requirement of shrinking the size, the width of the active regions is gradually reduced, and the space between the active regions is also gradually reduced, so that the manufacturing process of the active regions faces many limitations and challenges, which cannot meet the product requirements.

Disclosure of Invention

An objective of the present invention is to provide a semiconductor memory device, wherein the active structure has a second active region surrounding the first active region, wherein a plurality of openings are further disposed on the second active region, and the openings are disposed at positions corresponding to specific bit lines and contacts disposed thereon, respectively, so that the bit lines and word lines can be prevented from being directly conducted, and the semiconductor memory device can achieve a more optimized device performance.

In order to achieve the above object, one embodiment of the present application provides a semiconductor memory device including a substrate, an active structure, and shallow trench isolation. The active structure is disposed in the substrate and includes a first active region including a plurality of active region units that are parallel to each other and extend along a first direction, and a second active region. The second active region is disposed outside the first active region, the second active region includes a first side extending along a second direction and a second side extending along a third direction, and the first side and the second side are directly connected to a portion of the active region unit, wherein the second active region includes a plurality of first openings disposed on the second side. The shallow trench isolation is disposed in the substrate surrounding the active structure.

In order to achieve the above object, another embodiment of the present application provides a method for forming a semiconductor memory device, comprising the following steps. First, a substrate is provided, and an active structure including a first active region including a plurality of active region units parallel to each other and extending along a first direction and a second active region disposed outside the first active region is formed in the substrate. The second active region includes a first side extending along a second direction and a second side extending along a third direction, and the first side and the second side are directly connected to a portion of the active region unit, wherein the second active region includes a plurality of first openings disposed on the second side. Shallow trench isolation is then formed in the substrate surrounding the active structure.

Drawings

Fig. 1 to 4 are schematic diagrams showing a semiconductor memory device according to a first preferred embodiment of the present application; wherein the method comprises the steps of

FIG. 1 is a schematic top view of an active structure of a semiconductor memory device of the present application;

FIG. 2 is a schematic top view of a semiconductor memory device of the present application;

FIG. 3 is a schematic cross-sectional view of FIG. 2 along line A-A' (broken line); and

fig. 4 is a schematic cross-sectional view of fig. 2 along line B-B' (straight line).

Fig. 5 is a schematic diagram of a semiconductor memory device according to a second preferred embodiment of the present application.

Fig. 6 is a schematic diagram of a semiconductor memory device according to a third preferred embodiment of the present application.

Fig. 7 is a schematic diagram of a semiconductor memory device according to a fourth preferred embodiment of the present application.

Wherein reference numerals are as follows:

100. 200, 300, 400 semiconductor memory device

101. First region

103. Second region

110. Substrate and method for manufacturing the same

120. Shallow trench isolation

130. Active structure

131. A first active region

131a active area cell

132. 134, 232, 234 openings

133. Second active region

133a first side edge

133b second side

140. Buried gate structure

141. Dielectric layer

143. Gate dielectric layer

145. Gate electrode

147. Cover layer

150. Insulating layer

160. 161, 163 bit lines

162. Semiconductor layer

164. Barrier layer

166. Conductive layer

168. Mask layer

170. 171, 173, 190 contacts

172. Dielectric layer

333c, 433c third side

435. Protruding part

D1 First direction

D2 Second direction

D3 Third direction of

D4 Fourth direction

Pore size of O1, O2 and O3

T1 width

W width

Detailed Description

In order to further understand the present application, a person skilled in the art will now be able to more fully understand the present application, a number of preferred embodiments of the present application are specifically illustrated below, together with the accompanying drawings, to more fully describe the structure and desired effects of the present application. Those of skill in the art will be able to make substitutions, rearrangements, and combinations of features from several different embodiments to accomplish other embodiments without departing from the spirit of the application with reference to the following examples.

Referring to fig. 1 to 4, which are schematic diagrams of a semiconductor memory device 100 according to a first preferred embodiment of the present application, fig. 1 and 2 are schematic top views of the semiconductor memory device 100, and fig. 3 and 4 are schematic cross-sectional views of the semiconductor memory device 100, wherein fig. 3 and 4 are schematic cross-sectional views along a folding line direction (A-A ') and a straight line direction (B-B'), respectively. The semiconductor memory device 100 includes a substrate 110, such as a silicon base, a silicon-containing base (e.g., siC, siGe) or a silicon-on-insulator (SOI) base, at least one shallow trench isolation (shallow trench isolation, STI) 120 is disposed in the substrate 110 to define an active structure (active structure) 130 on the substrate 110, i.e., the shallow trench isolation 120 is disposed around the active structure 130. In detail, the active structure 130 further includes a first active region 131 disposed in the first region 101 and a second active region 133 disposed in the second region 103, wherein the first region 101 is, for example, a region of relatively high component integration in the semiconductor memory device 100, such as a memory region, and the second region 103 is, for example, a peripheral region of relatively low component integration in the semiconductor memory device 100, such as, but not limited to, the second region 103 is, for example, disposed outside the first region 101, as shown in fig. 1 and 2.

As shown in fig. 1 and 2, the first active region 131 includes a plurality of active region units 131a extending parallel to each other and spaced apart from each other along a first direction D1, and alternately arranged along the first direction D1, wherein the first direction D1 is not perpendicular to an x direction (e.g., the second direction D2) or a y direction (e.g., the third direction D3). In one embodiment, the active area units 131a are sequentially arranged in a plurality of columns along the second direction D2 in the first area 101, and may be generally arranged in a specific arrangement, such as the array arrangement (array arrangement) shown in fig. 1 and 2, but not limited thereto. The first active region 131 may be formed by, but not limited to, a patterning process described below. For example, a mask layer (not shown) is formed on the substrate 110, the mask layer includes a pattern for defining a plurality of active area units 131a of the first active area 131 and exposing a portion of the substrate 110, an etching process is performed by using the mask layer, the portion of the substrate 110 is removed to form at least one shallow trench (not shown), and then an insulating material (not shown) such as silicon oxide, silicon nitride or silicon oxynitride is filled in the shallow trench, so as to form the shallow trench isolation 120 on the surface of the top cut Ji Chende, and define the first active area 131, as shown in fig. 3. In one embodiment, the first active region 131 may be formed by a self-aligned double patterning (self-aligned double patterning, SADP) process or a self-aligned reverse patterning (self-aligned reverse patterning, SARP) process, but is not limited thereto.

On the other hand, the second active region 133 is circumferentially disposed outside the first active region 131. In the present embodiment, the details of the second active region 133 include at least one first side 133a extending along the second direction D2, and at least two second sides 133b extending along the third direction D3, where the second sides 133b are opposite to each other and are adjacent to each other and sequentially arranged with respect to the first sides 133a, so that the second active region 133 may entirely take a rectangular frame shape (not shown) and directly contact a portion of the active region units 131a. That is, when the second active region 133 is disposed, a portion of the active region units 131a may be further connected to the first and

second sides

133a and 133b of the second active region 133, and another portion of the active region units 131a may not be connected to the first and

second sides

133a and 133b of the second active region 133 but disposed separately therefrom, as shown in fig. 1 and 2. In addition, the first and

second sides

133a and 133b may have the same width T1, and the width T1 thereof may preferably be greater than the width W of each active region unit 131a, but is not limited thereto. With this arrangement, the second active region 133 can be more uniformly subjected to the stress from the active region unit 131a and the shallow trench isolation 120, so as to obtain a more stable structure. However, in other embodiments (not shown), the second active region 133 may be selected not to contact the active region unit 131a at all according to the actual product requirement, or the width T1 of the first side 133a and the second side 133b may be selected to be equal to or smaller than the width W of the active region unit 131a. It should be understood by those skilled in the art that the specific number of the first side or the second side may be adjusted according to the actual requirement, or may further include other sides, so that the second active region may entirely take on other shapes, not limited to the rectangular frame shape.

It should be noted that the second active region 133 further includes a plurality of first openings 132 and a plurality of second openings 134 disposed on the second sides 133b, respectively, that is, the first openings 132 are disposed on one second side 133b in sequence, and the second openings 134 are disposed on the other second side 133b in sequence, as shown in fig. 1 and 2. In an embodiment, the first opening 132 and the second opening 134 are disposed offset from each other in the second direction D2, and may have the same aperture O1 in the third direction D3, as shown in fig. 1 and 2, but not limited thereto. In addition, it should be noted that, in the present embodiment, the second active region 133 may be formed by the patterning process of the substrate 110, and may be optionally performed together with the patterning process of the first active region 131. That is, in this embodiment, the patterns of the first active region 131 and the second active region 133 may be defined simultaneously or separately by using the same or different mask layers, and then the substrate 110 is etched and filled with the insulating material. Here, the first active region 131 and the second active region 133 may include the same material (i.e., the material of the substrate 110), and the first side 133a, the second side 133b, and the active region unit 131a connected thereto of the second active region 133 may be integrally formed, as shown in fig. 1 and 4. In this case, the portion of the active region unit 131a of the first active region 131 connected to the first side 133a and the second side 133b of the second active region 133 may be regarded as an extension portion of the first side 133a and the second side 133b of the second active region 133 extending into the first region 101, so that the second active region 133 may have a relatively stable and reinforced structure to protect the first active region 131 disposed inside thereof from structural collapse or damage. However, it should be understood by those skilled in the art that the second active region is not limited to the above method, and may be formed by other methods, such as a process separate from the first active region. For example, in another embodiment, the second active region may be formed by patterning the substrate before the first active region, and then the first active region is formed by an epitaxial growth process (epitaxial growth process, not shown), where the top surfaces of the second active region and the first active region may not be coplanar (not shown); alternatively, in another embodiment, the second active region may be formed after the first active region by patterning the substrate, and then the second active region (e.g. including polysilicon, dielectric material, etc. different from the substrate) may be formed by a deposition process, where the second active region and the first active region may include different materials.

Next, a plurality of gate structures, preferably buried gate structures 140, are formed in the substrate 110, as shown in fig. 1 and 4. In this embodiment, a plurality of trenches (not shown) are formed in the substrate 110 and extend along the third direction D3 in parallel and spaced apart from each other. Then, a dielectric layer 141 covering the entire surface of each trench, a gate dielectric layer 143 covering the lower half surface of each trench, a gate 145 filling the lower half of each trench, and a cap layer 147 filling the upper half of each trench are sequentially formed. In this manner, the surface of the cap layer 147 may be cut Ji Chende at the top surface of the substrate 110 so that the buried gate structure 140 within the substrate 110 may serve as a Word Line (WL) of the semiconductor memory device 100 to receive or transmit a voltage signal of each memory cell. Then, an insulating layer 150 is formed on the substrate 110 to entirely cover the substrate 110 and contact the buried gate structure 140 and the shallow trench isolation 120 in the substrate 110, wherein the insulating layer 150 includes, but is not limited to, a silicon oxide-nitride-oxide (ONO) structure.

Then, at least one Bit Line (BL) 160 is formed on the substrate 110, at least one contact 170 is formed on the at least one bit line 160, and a contact 190 is formed on the word line (i.e., the buried gate structure 140) to be electrically connected to the at least one bit line 160 or the word line (i.e., the buried gate structure 140), respectively. As shown in fig. 2 and 3, a plurality of bit lines 160 and a plurality of

contacts

170 and 190 are formed in this embodiment, and each of the bit lines 160 extends in parallel and spaced apart from each other along the second direction D2, crosses word lines (i.e., the buried gate structures 140) disposed in the substrate 110, and crosses the active region unit 131a. Each bit line 160 includes a semiconductor layer 162, such as polysilicon, a barrier layer 164, such as titanium and/or titanium nitride, a conductive layer 166, such as tungsten, aluminum or copper, and a mask layer 168, such as silicon oxide, silicon nitride or silicon oxynitride, which are sequentially stacked on the insulating layer 150. A Bit Line Contact (BLC) is formed under a portion of the bit line 160, and the bit line contact can directly contact a portion of the active area unit 131a to electrically connect to a transistor element (not shown) in the substrate 110 to receive or transmit a voltage signal of each of the memory cells.

Contacts

170, 190 are disposed in dielectric layer 172 above substrate 110 to connect to underlying bit lines 160 or word lines (i.e., buried gate structure 140), respectively.

It should be noted that, each bit line 160 is disposed above the active structure 130 and partially overlaps the first active region 131 and the second active region 133 below, wherein a portion of the bit line 161 may overlap the second side 133b of one side (e.g., the left side of the bit line 161 shown in fig. 2) of the second active region 133 and pass over the second opening 134, but not overlap the second side 133b of the other side (e.g., the right side of the bit line 161 shown in fig. 2) of the second active region 133 at the same time, as shown in fig. 1. And, the portion of the bit line 161 is further connected to the contact 171 above, wherein the contact 171 is disposed at a first end (not shown, for example, refer to the left end of the bit line 160 shown in fig. 2) of the bit line 161 and is electrically connected thereto. On the other hand, another portion of the bit line 163 may pass through the top of the first opening 132 and overlap the second side 133b of the other side of the second active region 133, as shown in fig. 1. And, the top of the bit line 163 of the other portion is connected to a contact 173, wherein the contact 173 is disposed at a second end (not shown, for example, refer to the right end of the bit line 160 shown in fig. 1) of the bit line 163 and is electrically connected thereto. Thus, as seen in a top view of fig. 2, the

bit lines

161 and 163 are alternately arranged in the third direction D3, and the contacts 171 and the first openings 132 are alternately arranged in the third direction D3, and the contacts 173 and the second openings 134 are alternately arranged in the third direction D3. That is, each contact 171 may be disposed between any two of the first openings 132, and each of the first openings 132 is also disposed between any two of the contacts 171, and is located on each of the bit lines 163 and the contacts 173 disposed thereon; each contact 173 may be disposed between any two of the second openings 134, and each of the second openings 134 is also disposed between any two of the contacts 173 and is positioned on each of the bit lines 161 and the contacts 171 disposed thereon. In addition, the contact 190 may also have a configuration similar to that of the contact 170, for example, a portion of the word line (i.e., the buried gate structure 140) may be electrically connected to the contact 190 through one end (not shown, for example, referring to the lower end of the buried gate structure 140 shown in fig. 1 and 2), while another portion of the word line (i.e., the buried gate structure 140) may be electrically connected to another portion of the contact (not shown), but not limited thereto, through another end (not shown, for example, referring to the upper end of the buried gate structure 140 shown in fig. 1 and 2). With this arrangement, the

contacts

170, 190 can not only maintain a sufficient process window, but also prevent the voltage signal of the bit line 160 from directly conducting with the voltage signal of the word line (i.e., the buried gate structure 140) through the second side 133b of the second active region 133, thereby shorting the semiconductor memory device 100.

Thus, the semiconductor memory device 100 of the first preferred embodiment of the present application is completed. The semiconductor memory device 100 has a second active region 133 circumferentially disposed outside the first active region 131, wherein a portion of the active region units 131a can be further connected to the first side 133a and the second side 133b of the second active region 133, such that the second active region 133 can be more uniformly subjected to the stress from the active region units 131a of the first active region 131 and the shallow trench isolation 120, so as to obtain a more stable structure. In addition, the second active region 133 is further provided with a plurality of first openings 132 and second openings 134, wherein the first openings 132 are disposed in the second direction D2 and are respectively opposite to the bit lines 163 and the contacts 173, and the second openings 134 are disposed in the second direction D2 and are respectively opposite to the bit lines 161 and the contacts 173, so that the bit lines 160 and the word lines (i.e. the buried gate structures 140) can be prevented from being directly conducted, and the semiconductor memory device 100 can achieve a more optimized device performance.

However, it should be readily understood by those skilled in the art that the semiconductor memory device and the manufacturing process thereof may have other aspects or may be achieved by other means, and are not limited to the foregoing, provided that the actual product requirements can be met. For example, in one embodiment, the second active region 133 may be patterned by adjusting etching conditions, but not limited to, to round the corners. Accordingly, further description will be made below with respect to other embodiments or variations of the present application. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present application are labeled with like reference numerals to facilitate cross-reference between the various embodiments.

Referring to fig. 5, a schematic diagram of a semiconductor memory device 200 according to a second preferred embodiment of the present application is shown. In this embodiment, the structure of the semiconductor memory device 200 is substantially the same as that of the semiconductor memory device 100 of the first preferred embodiment, and includes the substrate 110, the shallow trench isolation 120, the active structure 130, the buried gate structure 140 (i.e. word line), the bit line 160, and the

contacts

170, 190, etc., which are not repeated herein. The main difference between the semiconductor memory device 200 of the present embodiment and the aforementioned semiconductor memory device 100 is that the plurality of first openings 232 and the plurality of second openings 234 formed on the second side 133b may include different apertures O2 and O3.

In detail, the first openings 232 are sequentially disposed on one second side 133b of the second active region 133, and the second openings 234 are sequentially disposed on the other second side 133b of the second active region 133, as shown in fig. 5. In the present embodiment, the first opening 232 and the second opening 234 are disposed at a different position in the second direction D2, wherein the first opening 232 may have the same aperture O2 in the third direction D3, and the second opening 234 may have different apertures O2 and O3 in the third direction D3, but not limited thereto. It should be readily understood by those skilled in the art that the aperture sizes of the first opening 232 and the second opening 234 may be varied according to the actual product requirements, for example, in another embodiment, the apertures of the first opening and the second opening may be different, or the second openings may have uniform first apertures (not shown), and the first openings may have the same or different apertures.

In this arrangement, the first opening 232 is disposed at the second direction D2 opposite to the bit line 163 and the contact 173, and the second opening 234 is disposed at the second direction D2 opposite to the bit line 161 and the contact 173, so as to avoid direct conduction between the bit line 160 and the word line (i.e. the buried gate structure 140). Thus, the semiconductor memory device 200 of the second preferred embodiment of the present application can achieve more optimized device performance as well.

Referring to fig. 6, a schematic diagram of a semiconductor memory device 300 according to a third preferred embodiment of the present invention is shown. In this embodiment, the structure of the semiconductor memory device 300 is substantially the same as that of the semiconductor memory device 100 of the first preferred embodiment, and includes the substrate 110, the shallow trench isolation 120, the active structure 130, the buried gate structure 140 (i.e. word line), the bit line 160, and the

contacts

170, 190, etc., which are not repeated herein. The main difference between the semiconductor memory device 300 of the present embodiment and the semiconductor memory device 100 is that the second active region 133 further includes at least one third side 333c extending along the first direction D1.

In detail, the third side 333c is formed between the first side 133a extending along the second direction D2 and the second side 133b extending along the third direction D3, i.e. the first side 133a abuts the third side 333c, and the third side 333c further abuts the second side 133b, such that the second active region 133 may entirely have a multi-frame shape (not shown) to surround the first active region 131. In the present embodiment, the third side 333c may have a width T1 equal to the first side 133a and the second side 133b, but is not limited thereto. In another embodiment, the third side 333c may have a relatively larger width (not shown), such as a width T1 greater than the widths of the first side 133a and the second side 133 b. It should be understood that, as a person skilled in the art can easily understand, the extending direction of the third side and the specific number of the third side can be adjusted according to the actual requirement, so that the second active region can entirely take on other shapes, which is not limited as described above.

With this arrangement, the second active region 133 can obtain a relatively stable and reinforced structure by the arrangement of the third side 333c, so as to improve the stress around the semiconductor memory device and avoid structural collapse or damage. Meanwhile, the first opening 132 on the second active region 133 is still located at the bit line 163 and the contact 173 in the second direction D2, and the second opening 134 is still located at the bit line 161 and the contact 171 in the second direction D2, so as to avoid direct conduction between the bit line 160 and the word line (i.e. the buried gate structure 140). Thus, the semiconductor memory device 300 of the third preferred embodiment of the present application can achieve more optimized device performance as well.

Referring to fig. 7, a schematic diagram of a semiconductor memory device 400 according to a fourth preferred embodiment of the present invention is shown. In this embodiment, the structure of the semiconductor memory device 400 is substantially the same as that of the semiconductor memory device 300 of the aforementioned third preferred embodiment, and includes the substrate 110, the shallow trench isolation 120, the active structure 130, the buried gate structure 140 (i.e. word line), the bit line 160, and the

contacts

170, 190, etc., which are not repeated herein. The main difference between the semiconductor memory device 400 of the present embodiment and the aforementioned semiconductor memory device 300 is that a plurality of protruding portions 435 are additionally disposed on at least one third side 433 c.

In detail, the third side 433c extends along the first direction D1, and is formed between the first side 133a and the second side 133b, such that the second active region 133 may entirely take a multi-frame shape (not shown) to surround the first active region 131. The protruding portion 435 is, for example, integrally formed with the third side 433c and disposed on a side of the third side 433c away from the first active region 131, that is, the protruding portion 435 extends outward to the second region 103, for example, along a fourth direction D4 different from the first direction D1, the second direction D2 and the third direction D3, so as to further strengthen the structural strength outside the second active region 133.

Therefore, the semiconductor memory device 400 according to the fourth preferred embodiment of the present invention can further strengthen the structural strength of the second active region 133 by the arrangement of the third side 433c and the protruding portion 435, so as to improve the stress around the semiconductor memory device 400 and avoid structural collapse or damage. In addition, it should be understood by those skilled in the art that in the foregoing embodiments, the number, shape or size of the protruding portions may be adjusted according to the actual requirements of the components, and the number is not limited to that shown in fig. 7. Meanwhile, the first opening 132 on the second active region 133 is still located at the bit line 163 and the contact 173 in the second direction D2, and the second opening 134 is still located at the bit line 161 and the contact 173 in the second direction D2, so as to avoid direct conduction between the bit line 160 and the word line (i.e. the buried gate structure 140). Thus, the semiconductor memory device 400 according to the fourth preferred embodiment of the present invention can achieve more optimized device performance.

The semiconductor memory device is provided with the second active region which can surround the outer side of the first active region around the device, and a plurality of openings are further arranged on the second active region, so that the arrangement positions of the openings can be respectively opposite to a specific bit line and contacts arranged on the specific bit line, thereby avoiding the direct conduction between the bit line and a word line, and ensuring that the semiconductor memory device can achieve more optimized element performance. Meanwhile, the second active region is additionally provided with a strengthening structure, such as a thickened side edge or a protruding part, so that the periphery of the device can be provided with a relatively stable and strengthened structure, so that components on the inner side of the device are protected, and further relatively optimized element performance is achieved.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor memory device characterized by comprising:

a substrate;

an active structure disposed in the substrate, the active structure comprising:

a first active region including a plurality of active region units parallel to each other and extending along a first direction; and

a second active region disposed outside the first active region, the second active region including a first side extending along a second direction and a second side extending along a third direction, and the first side and the second side directly connecting a portion of the active region units, wherein the second active region includes a plurality of first openings disposed on the second side; and

shallow trench isolation disposed in the substrate surrounding the active structure;

at least one bit line disposed on the substrate and interleaved with the active region cells, the at least one bit line extending in the second direction, the second direction being perpendicular to the third direction and not perpendicular to the first direction;

at least one first contact is arranged on the at least one bit line to be electrically connected with the at least one bit line, and the first opening is arranged between any two first contacts.

2. The semiconductor memory device according to claim 1, wherein the at least one bit line includes a plurality of first bit lines and a plurality of second bit lines, the first bit lines and the second bit lines being sequentially alternately arranged in the third direction.

3. The semiconductor memory device according to claim 2, further comprising a plurality of second contacts, wherein the first contacts are respectively disposed on first ends of the first bit lines, and the second contacts are respectively disposed on second ends of the second bit lines.

4. The semiconductor memory device according to claim 3, wherein the pair of first openings are located at the second contact.

5. The semiconductor memory device according to claim 3, further comprising:

a plurality of second openings provided on another second side edge, wherein the another second side edge extends along the third direction and is opposite to the second side edge, and each of the second openings is provided between any two of the second contacts.

6. The semiconductor memory device according to claim 5, wherein the pair of second openings is located at the first contact.

7. The semiconductor memory device according to claim 1, wherein the second active region further comprises at least one third side extending along the first direction and located between the first side and the second side.

8. The semiconductor memory device according to claim 7, wherein a width of the third side of the second active region is equal to a width of the second side or a width of the first side.

9. The semiconductor memory device according to claim 7, wherein a width of the at least one third side of the second active region is greater than a width of the second side, a width of the first side, or a width of the active region unit.

10. The semiconductor memory device according to claim 7, further comprising:

a plurality of protruding portions disposed on the third side of the second active region.

11. The semiconductor memory device according to claim 1, wherein the first side of the second active region is parallel to the at least one bit line.

12. A method of forming a semiconductor memory device, comprising:

providing a substrate;

forming an active structure in the substrate, the active structure comprising:

forming shallow trench isolation in the substrate surrounding the active structure;

forming at least one bit line on the substrate, the at least one bit line extending in the second direction and being staggered with the active area cells, the second direction being perpendicular to the third direction and not perpendicular to the first direction; and

forming at least one first contact on the at least one bit line, electrically connecting the bit line; the first opening is arranged between any two first contacts.

13. The method of claim 12, wherein the at least one bit line comprises a plurality of first bit lines and a plurality of second bit lines, and at least one second contact is further formed on the at least one bit line, wherein the first bit lines and the second bit lines are alternately arranged sequentially in the third direction, the first contacts are respectively disposed on first ends of the first bit lines, and the second contacts are respectively disposed on second ends of the second bit lines.

14. The method of forming a semiconductor memory device according to claim 13, wherein the pair of first openings are located at the second contact.

15. The method for forming a semiconductor memory device according to claim 12, further comprising:

a third side is formed between the first side and the second side, the third side extending along the first direction.

16. The method for forming a semiconductor memory device according to claim 15, further comprising:

a plurality of protruding portions are formed on the third side edge, the protruding portions extending in a fourth direction different from the first direction, the second direction, and the third direction.