CN214411197U - Semiconductor memory device with a plurality of memory cells - Google Patents

Abstract

A semiconductor memory device includes a substrate, an active structure, and shallow trench isolation. An active structure is disposed in the substrate and includes a first active region and a second active region. The first active region comprises a plurality of active region units, the second active region is arranged outside the first active region and is directly connected with a part of the active region units, and the second active region comprises a plurality of first openings and is arranged on the side edge of the second active region. Shallow trench isolation is disposed in the substrate surrounding the active structure.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including an active structure and a shallow trench isolation.

Background

As semiconductor devices are miniaturized and integrated circuits are complicated, device sizes are continuously reduced and structures are continuously changed, so that maintaining the performance of small-sized semiconductor devices is a major goal in the industry. In a semiconductor fabrication process, a plurality of active regions are defined on a substrate as a basis, and required devices are formed on the active regions. Generally, the active regions are formed by photolithography and etching processes to form a plurality of patterns on the substrate, but the width of the active regions is gradually reduced and the distance between the active regions is also gradually reduced under the requirement of size reduction, so that the manufacturing process thereof also faces many limitations and challenges, and thus cannot meet the product requirements.

SUMMERY OF THE UTILITY MODEL

An objective of the present invention is to provide a semiconductor memory device, wherein an active structure of the semiconductor memory device has a second active region surrounding and disposed outside a first active region, wherein a plurality of openings are further disposed on the second active region, and the positions of the openings can be respectively aligned to a specific bit line and a contact disposed thereon, thereby preventing the bit line from being directly conducted to a word line, so that the semiconductor memory device can achieve a more optimized device performance.

To achieve the above objective, one embodiment of the present invention provides a semiconductor memory device including a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate, and includes a first active region including a plurality of active region cells parallel to each other and extending along a first direction and a second active region. The second active area is disposed outside the first active area, the second active area includes a first side extending along a second direction and a second side extending along a third direction, and the first side and the second side are directly connected to a portion of the active area unit, wherein the second active area includes a plurality of first openings, and the first openings are disposed on the second side. The shallow trench isolation is disposed in the substrate surrounding the active structure.

Drawings

FIGS. 1 to 4 are schematic views of a semiconductor memory device according to a first preferred embodiment of the present invention; wherein

FIG. 1 is a schematic top view of an active structure of a semiconductor memory device according to the present application;

FIG. 2 is a schematic top view of a semiconductor memory device according to the present application;

FIG. 3 is a schematic cross-sectional view of FIG. 2 along line A-A' (the broken line); and

fig. 4 is a schematic sectional view of fig. 2 along the line B-B' (straight line).

FIG. 5 is a schematic diagram of a semiconductor memory device according to a second preferred embodiment of the present invention.

FIG. 6 is a schematic diagram of a semiconductor memory device according to a third preferred embodiment of the present invention.

FIG. 7 is a schematic diagram of a semiconductor memory device according to a fourth preferred embodiment of the present invention.

Wherein the reference numerals are as follows:

100. 200, 300, 400 semiconductor memory device

101 first region

103 second region

110 substrate

120 shallow trench isolation

130 active structure

131 first active region

131a active area unit

132. 134, 232, 234 opening

133 second active region

133a first side edge

133b second side edge

140 buried gate structure

141 dielectric layer

143 gate dielectric layer

145 gate

147 cap layer

150 insulating layer

160. 161, 163 bit line

162 semiconductor layer

164 Barrier layer

166 conductive layer

168 mask layer

170. 171, 173, 190 contact

172 dielectric layer

333c, 433c third side edge

435 projecting part

D1 first direction

D2 second direction

Third direction D3

D4 fourth direction

O1, O2 and O3 pore diameter

Width of T1

Width W

Detailed Description

To further clarify the present application, and to enable one of ordinary skill in the art to which the present application pertains, a more particular description of the preferred embodiments of the present application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Those skilled in the art to which the invention relates will appreciate that other embodiments can be devised which do not depart from the spirit of the invention and which include all the features of the various embodiments described below by way of substitution, recombination and combination of features.

Referring to fig. 1 to 4, a schematic diagram of a semiconductor memory device 100 according to a first preferred embodiment of the present invention is shown, in which fig. 1 and 2 are top view schematic diagrams of the semiconductor memory device 100, and fig. 3 and 4 are cross-sectional schematic diagrams of the semiconductor memory device 100, it should be noted that fig. 3 and 4 respectively depict cross-sectional schematic diagrams along a folding line direction (a tangent line a-a ') and a straight line direction (a tangent line B-B'). The semiconductor memory device 100 includes a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe) or a silicon-on-insulator (SOI) substrate, and at least one Shallow Trench Isolation (STI) 120 is disposed in the substrate 110 to define an active structure (active structure)130 on the substrate 110, i.e., the STI 120 is disposed around the active structure 130. In detail, the active structure 130 further includes a first active region 131 disposed in the first region 101, and a second active region 133 disposed in the second region 103, wherein the first region 101 is, for example, a region with a relatively high device integration level in the semiconductor memory device 100, such as a memory region, and the second region 103 is, for example, a peripheral region in the semiconductor memory device 100, such as, but not limited to, a region with a relatively low device integration level, such as, for example, a peripheral region, and the second region 103 is, for example, disposed outside the first region 101, as shown in fig. 1 and fig. 2.

As shown in fig. 1 and fig. 2, the first active region 131 includes a plurality of active region cells 131a extending in parallel and spaced apart from each other along a first direction D1 and alternately arranged along a first direction D1, wherein the first direction D1 is, for example, not perpendicular to the x-direction (e.g., the second direction D2) or the y-direction (e.g., the third direction D3). In one embodiment, the active area units 131a are sequentially arranged in a plurality of rows along the second direction D2 in the first region 101, and may be arranged in a specific arrangement as a whole, such as the array arrangement (array arrangement) shown in fig. 1 and fig. 2, but not limited thereto. The first active region 131 may be formed by, but is not limited to, a patterning process described below. For example, a mask layer (not shown) is formed on the substrate 110, the mask layer includes a pattern for defining a plurality of active region units 131a of the first active region 131 and exposes a portion of the substrate 110, an etching process is performed using the mask layer to remove the portion of the substrate 110 and form at least one shallow trench (not shown), and then an insulating material (not shown) such as silicon oxide, silicon nitride, or silicon oxynitride is filled into the shallow trench to form the shallow trench isolation 120 with a top surface aligned with the surface of the substrate 110 and define the first active region 131, as shown in fig. 3. In an embodiment, the first active region 131 may be formed by a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but is not limited thereto.

On the other hand, the second active region 133 is disposed around the first active region 131. In the present embodiment, the second active region 133 includes at least one first side 133a extending along the second direction D2 and at least two second sides 133b extending along the third direction D3, wherein the second sides 133b are opposite to each other and are adjacent to and sequentially disposed with the first sides 133a, so that the second active region 133 can be in a rectangular frame shape (not shown) as a whole and directly contact a portion of the active region units 131 a. That is, when the second active region 133 is disposed, a portion of the active region units 131a may be further connected to the first side 133a and the second side 133b of the second active region 133, and another portion of the active region units 131a may be disposed apart from the first side 133a and the second side 133b of the second active region 133, as shown in fig. 1 and fig. 2. In addition, the first side 133a and the second side 133b may have the same width T1, and the width T1 thereof may preferably be greater than the width W of each active area unit 131a, but is not limited thereto. With this arrangement, the second active region 133 can more uniformly bear the stress influence from the active region unit 131a and the shallow trench isolation 120, so as to obtain a more stable structure. However, in other embodiments (not shown), the second active region 133 may not contact the active region unit 131a at all, or the widths T1 of the first side 133a and the second side 133b may be equal to or smaller than the width W of the active region unit 131a according to actual product requirements. It should be understood by those skilled in the art that the specific number of the first sides or the second sides can be adjusted according to actual requirements, or other sides can be further included, so that the second active region can take other shapes as a whole, not limited to the rectangular frame shape.

It should be noted that the second active region 133 further includes a plurality of first openings 132 and a plurality of second openings 134 respectively disposed on the two second sides 133b, that is, the first openings 132 are sequentially disposed on one second side 133b, and the second openings 134 are sequentially disposed on the other second side 133b, as shown in fig. 1 and fig. 2. In an embodiment, the first opening 132 and the second opening 134 are disposed in a staggered manner in the second direction D2, and may have the same aperture O1 in the third direction D3, as shown in fig. 1 and fig. 2, but not limited thereto. It should be noted that, in the present embodiment, the second active region 133 may be formed by a patterning process of the substrate 110, and may be optionally performed together with the patterning process of the first active region 131. That is, in the present embodiment, the patterns of the first active region 131 and the second active region 133 may be simultaneously defined or separately defined by using the same or different mask layers, and then the substrate 110 is etched and filled with the insulating material. Herein, the first active region 131 and the second active region 133 may include the same material (i.e., the material of the substrate 110), and the first side 133a and the second side 133b of the second active region 133 and the active region unit 131a connected thereto may be integrally formed, as shown in fig. 1 and 4. In this case, the portion of the active region unit 131a of the first active region 131 connected to the first side 133a and the second side 133b of the second active region 133 can be regarded as an extension portion of the first side 133a and the second side 133b of the second active region 133 extending into the first region 101, so that the second active region 133 can have a relatively stable and strengthened structure to protect the first active region 131 disposed inside thereof and avoid structure collapse or damage. However, it should be understood by those skilled in the art that the formation of the second active region is not limited to the above-mentioned method, and may be formed by other methods, for example, separately from the manufacturing process of the first active region. For example, in another embodiment, the second active region may be formed before the first active region, the second active region is formed by patterning the substrate, and the first active region is formed by an epitaxial growth process (not shown), wherein the top surfaces of the second active region and the first active region may not be coplanar (not shown); alternatively, in another embodiment, the second active region may be formed after the first active region is formed, the first active region is formed by a patterning process of the substrate, and the second active region is formed by a deposition process (for example, a material different from the substrate, such as polysilicon, a dielectric material, etc.), where the second active region and the first active region may comprise different materials.

Next, a plurality of gate structures, preferably buried gate structures 140, are formed in the substrate 110, as shown in fig. 1 and 4. In the present embodiment, a plurality of trenches (not shown) extending in the third direction D3 are formed in the substrate 110 in parallel and spaced apart from each other. Then, a dielectric layer 141 covering the entire surface of each trench, a gate dielectric layer 143 covering the bottom surface of each trench, a gate 145 filling the bottom of each trench, and a cap layer 147 filling the top of each trench are sequentially formed. Thus, the surface of the cap layer 147 may be aligned with the top surface of the substrate 110, so that the buried gate structure 140 in the substrate 110 may be used as a Word Line (WL) of the semiconductor memory device 100 to receive or transmit a voltage signal of each memory cell (memory cell). Then, an insulating layer 150 is formed on the substrate 110, fully covering the substrate 110 and contacting the buried gate structure 140 and the shallow trench isolation 120 located in the substrate 110, wherein the insulating layer 150 includes, but is not limited to, an oxide-nitride-oxide (ONO) structure.

Then, at least one Bit Line (BL) 160 is formed on the substrate 110, at least one contact 170 is formed on the at least one bit line 160, and a contact 190 is formed on the word line (i.e., the buried gate structure 140) and electrically connected to the at least one bit line 160 or the word line (i.e., the buried gate structure 140), respectively. As shown in fig. 2 and 3, in the present embodiment, a plurality of bit lines 160 and a plurality of contacts 170 and 190 are formed, and the bit lines 160 extend in parallel to each other and spaced apart from each other along the second direction D2, cross the word lines (i.e., the buried gate structures 140) disposed in the substrate 110, and are staggered with the active area units 131 a. Each bit line 160 includes, but is not limited to, a semiconductor layer 162 comprising polysilicon, a barrier layer 164 comprising titanium and/or titanium nitride, a conductive layer 166 comprising a low resistivity metal such as tungsten, aluminum, or copper, and a mask layer 168 comprising silicon oxide, silicon nitride, or silicon oxynitride, which are sequentially stacked on the insulating layer 150. A Bit Line Contact (BLC) is formed below a portion of the bit line 160, and the bit line contact can directly contact a portion of the active region unit 131a to be electrically connected to a transistor device (not shown) in the substrate 110 for receiving or transmitting a voltage signal of each memory cell. Contacts 170, 190 are disposed in dielectric layer 172 above substrate 110 to connect to underlying bit lines 160 or word lines (i.e., buried gate structures 140), respectively.

It is to be noted that each bit line 160 spans over the active structure 130 and partially overlaps the first active region 131 and the second active region 133 therebelow, wherein a portion of the bit line 161 may overlap the second side 133b of one side of the second active region 133 (e.g., the left side of the bit line 161 shown in fig. 2) and pass through the second opening 134 without overlapping the second side 133b of the other side of the second active region 133 (e.g., the right side of the bit line 161 shown in fig. 2), as shown in fig. 1. The upper portion of the bit line 161 is further connected to a contact 171, wherein the contact 171 is disposed at a first end (not shown) of the bit line 161 (e.g., referring to the left end of the bit line 160 shown in fig. 2) and electrically connected thereto. On the other hand, another portion of the bit line 163 may pass through the first opening 132 and overlap the second side 133b of the second active region 133 at the other side, as shown in fig. 1. The other portion of bit line 163 is connected to contact 173, wherein contact 173 is disposed at and electrically connected to a second end (not shown) of bit line 163 (e.g., the right end of bit line 160 shown in fig. 1). As such, from a top view shown in fig. 2, the bit lines 161 and 163 are alternately arranged in sequence in the third direction D3, the contacts 171 and the first openings 132 are alternately arranged in the third direction D3, and the contacts 173 and the second openings 134 are alternately arranged in the third direction D3. That is, each contact 171 can be disposed between any two first openings 132, with each first opening 132 likewise disposed between any two contacts 171, and aligned with each bit line 163 and contact 173 disposed thereon; each contact 173 can be disposed between any two second openings 134, and each second opening 134 can also be disposed between any two contacts 173, for each bit line 161 and contact 171 disposed thereon. In addition, the contact 190 may also have a configuration similar to the contact 170, such that, for example, a portion of the word line (i.e., the buried gate structure 140) may be electrically connected to the contact 190 through one end (not shown, for example, the lower end of the buried gate structure 140 shown in fig. 1 and 2), and another portion of the word line (i.e., the buried gate structure 140) may be electrically connected to another portion of the contact (not shown) through the other end (not shown, for example, the upper end of the buried gate structure 140 shown in fig. 1 and 2), but not limited thereto. With this configuration, the contacts 170 and 190 can not only keep enough process space (process window), but also prevent the voltage signal of the bit line 160 from being directly conducted to the voltage signal of the word line (i.e., the buried gate structure 140) through the second side 133b of the second active region 133, thereby causing a short circuit in the semiconductor memory device 100.

Thus, the semiconductor memory device 100 according to the first preferred embodiment of the present application is completed. The semiconductor memory device 100 has a second active region 133 disposed around the first active region 131, wherein a portion of the active region cells 131a may be further connected to the first side 133a and the second side 133b of the second active region 133, so that the second active region 133 can more uniformly bear the stress influence from the active region cells 131a of the first active region 131 and the shallow trench isolation 120, thereby obtaining a more stable structure. In addition, a plurality of first openings 132 and second openings 134 are further disposed on the second active region 133, wherein the first openings 132 are disposed on the bit line 163 and the contact 173 in the second direction D2, respectively, and the second openings 134 are disposed on the bit line 161 and the contact 173 in the second direction D2, respectively, so as to prevent the bit line 160 and the word line (i.e., the buried gate structure 140) from being directly conducted, so that the semiconductor memory device 100 can achieve better device performance.

However, it should be readily apparent to those skilled in the art that the semiconductor memory device and the fabrication process thereof may have other aspects or may be implemented by other means without being limited to the foregoing. For example, in an embodiment, it is also possible to round the formed corner portions by adjusting the etching conditions during the patterning process of the second active region 133, but not limited thereto. Therefore, further description will be given below with respect to other embodiments or variations of the present application. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present application are denoted by the same reference numerals to facilitate the comparison between the embodiments.

Referring to fig. 5, a schematic diagram of a semiconductor memory device 200 according to a second preferred embodiment of the present application is shown. In this embodiment, the structure of the semiconductor memory device 200 is substantially the same as the semiconductor memory device 100 of the first preferred embodiment, and includes the substrate 110, the shallow trench isolation 120, the active structure 130, the buried gate structure 140 (i.e., the word line), the bit line 160, and the contacts 170 and 190, which are the same and will not be described herein again. The semiconductor memory device 200 of the present embodiment is different from the semiconductor memory device 100 in that the first openings 232 and the second openings 234 formed on the second side 133b may include different apertures O2 and O3.

In detail, the first opening 232 is sequentially disposed on one second side 133b of the second active region 133, and the second opening 234 is sequentially disposed on the other second side 133b of the second active region 133, as shown in fig. 5. In the present embodiment, the first opening 232 and the second opening 234 are disposed in a staggered manner in the second direction D2, wherein the first opening 232 may have the same aperture O2 in the third direction D3, and the second opening 234 may have different apertures O2 and O3 in the third direction D3, but not limited thereto. It should be readily understood that the aperture sizes of the first openings 232 and the second openings 234 may vary according to the actual product requirements, for example, in another embodiment, the apertures of the first openings and the second openings may be different, or the second openings may have uniform first apertures (not shown), and the first openings may have the same or different apertures.

With this arrangement, the first opening 232 is still disposed at the bit line 163 and the contact 173 in the second direction D2, and the second opening 234 is disposed at the bit line 161 and the contact 173 in the second direction D2, so as to prevent the bit line 160 and the word line (i.e., the buried gate structure 140) from being directly conducted. Thus, the semiconductor memory device 200 according to the second preferred embodiment of the present application can achieve more optimized device performance.

Referring to fig. 6, a schematic diagram of a semiconductor memory device 300 according to a third preferred embodiment of the present invention is shown. In this embodiment, the structure of the semiconductor memory device 300 is substantially the same as the semiconductor memory device 100 of the first preferred embodiment, and includes the substrate 110, the shallow trench isolation 120, the active structure 130, the buried gate structure 140 (i.e., the word line), the bit line 160, and the contacts 170 and 190, which are the same and will not be described herein again. The main difference between the semiconductor memory device 300 of the present embodiment and the semiconductor memory device 100 is that the second active region 133 additionally includes at least one third side 333c extending along the first direction D1.

In detail, the third side 333c is, for example, formed between the first side 133a extending along the second direction D2 and the second side 133b extending along the third direction D3, that is, the first side 133a is adjacent to the third side 333c, and the third side 333c is further adjacent to the second side 133b, so that the second active region 133 can be a polygonal frame (not shown) to surround the first active region 131. In the present embodiment, the third side 333c may have a width T1 equal to the first side 133a and the second side 133b, but not limited thereto. In another embodiment, the third side 333c may have a relatively larger width (not shown), such as a width T1 greater than the first side 133a and the second side 133 b. It should be readily understood by those skilled in the art that the extending direction of the third side and the specific number of the third side can be adjusted according to actual requirements, so that the second active region can be in other shapes as a whole, and the foregoing is not limited thereto.

With this configuration, the second active region 133 can obtain a stable and strengthened structure by the third side 333c, so as to improve the stress around the semiconductor memory device and prevent the structure from collapsing or being damaged. Meanwhile, the first opening 132 of the second active region 133 is still located at the bit line 163 and the contact 173 in the second direction D2, and the second opening 134 is still located at the bit line 161 and the contact 171 in the second direction D2, so as to prevent the bit line 160 and the word line (i.e., the buried gate structure 140) from being directly conducted. Thus, the semiconductor memory device 300 according to the third preferred embodiment of the present invention can achieve better device performance.

Referring to fig. 7, a semiconductor memory device 400 according to a fourth preferred embodiment of the present invention is shown. In this embodiment, the structure of the semiconductor memory device 400 is substantially the same as that of the semiconductor memory device 300 of the third preferred embodiment, and includes the substrate 110, the shallow trench isolation 120, the active structure 130, the buried gate structure 140 (i.e., the word line), the bit line 160, and the contacts 170 and 190, which are the same and will not be described herein again. The main difference between the semiconductor memory device 400 of the present embodiment and the semiconductor memory device 300 is that a plurality of protruding portions 435 are additionally disposed on at least one third side 433 c.

In detail, the third side 433c extends along the first direction D1, and is formed between the first side 133a and the second side 133b, so that the second active region 133 may be a polygonal frame (not shown) to surround the first active region 131. The protruding portion 435 is, for example, integrally formed with the third side 433c and disposed on a side of the third side 433c away from the first active region 131, that is, the protruding portion 435 extends outward to the second region 103, for example, along a fourth direction D4 different from the first direction D1, the second direction D2 and the third direction D3, so as to further enhance the structural strength outside the second active region 133.

Therefore, the semiconductor memory device 400 according to the fourth preferred embodiment of the present invention can further enhance the structural strength of the second active region 133 by the third side 433c and the protruding portion 435, so as to improve the stress around the semiconductor memory device 400 and avoid the occurrence of structural collapse or damage. In addition, it should be understood by those skilled in the art that the number, shape, or size of the protruding portions in the foregoing embodiments can be adjusted according to the actual device requirements, and the number shown in fig. 7 is not limited. Meanwhile, the first opening 132 of the second active region 133 is still located at the bit line 163 and the contact 173 in the second direction D2, and the second opening 134 is still located at the bit line 161 and the contact 173 in the second direction D2, so as to prevent the bit line 160 and the word line (i.e., the buried gate structure 140) from being directly conducted. Thus, the semiconductor memory device 400 according to the fourth preferred embodiment of the present invention can achieve better device performance.

The semiconductor memory device of the present application is provided with a second active region surrounding the first active region, and a plurality of openings are further formed in the second active region, so that the positions of the openings can be aligned to specific bit lines and contacts disposed thereon, respectively, thereby preventing the bit lines from being directly conducted to the word lines, and achieving more optimal device performance. Meanwhile, a strengthening structure such as a thickened side edge or a protruding part is additionally arranged on the second active region, so that a stable and strengthened structure can be arranged around the device to protect components at the inner side of the device, and further, the optimized element efficiency is achieved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (14)

1. A semiconductor memory device, characterized by comprising:

a substrate;

an active structure disposed in the substrate, the active structure comprising:

a first active region including a plurality of active region cells parallel to each other and extending along a first direction; and

a second active region disposed outside the first active region, the second active region including a first side extending along a second direction and a second side extending along a third direction, and the first side and the second side directly connecting a portion of the active region units, wherein the second active region includes a plurality of first openings disposed on the second side; and

and the shallow trench isolation is arranged in the substrate and surrounds the active structure.

2. The semiconductor memory device according to claim 1, characterized by further comprising:

at least one bit line disposed on the substrate and interleaved with the active area cells, the at least one bit line extending in the second direction, the second direction being perpendicular to the third direction and not perpendicular to the first direction.

3. The semiconductor memory device according to claim 2, further comprising at least one contact disposed on the at least one bit line to electrically connect the at least one bit line.

4. The semiconductor memory device according to claim 3, wherein the at least one bit line includes a plurality of first bit lines and a plurality of second bit lines, the first bit lines and the second bit lines being sequentially arranged alternately in the third direction.

5. The semiconductor memory device according to claim 4, wherein the at least one contact includes a plurality of first contacts and a plurality of second contacts, wherein the first contacts are respectively disposed on first ends of the first bit lines, and the second contacts are respectively disposed on second ends of the second bit lines.

6. The semiconductor memory device according to claim 5, wherein each of the first openings is provided between any two of the first contacts.

7. The semiconductor memory device according to claim 5, wherein the pair of first openings are located at the second contact.

8. The semiconductor memory device according to claim 5, characterized by further comprising:

a plurality of second openings disposed on another second side edge, wherein the another second side edge extends along the third direction and is opposite to the second side edge, and each of the second openings is disposed between any two of the second contacts.

9. The semiconductor memory device according to claim 8, wherein the pair of second openings are located at the first contact.

10. The semiconductor memory device according to claim 1, wherein the second active region further comprises at least one third side extending along the first direction and located between the first side and the second side.

11. The semiconductor memory device according to claim 10, wherein a width of the third side of the second active region is equal to a width of the second side or a width of the first side.

12. The semiconductor memory device according to claim 10, wherein a width of the at least one third side of the second active region is greater than a width of the second side, a width of the first side, or a width of the active region cell.

13. The semiconductor memory device according to claim 10, characterized by further comprising:

a plurality of protruding portions disposed on the third side of the second active region.

14. The semiconductor memory device according to claim 2, wherein the first side of the second active region and the at least one bit line are parallel to each other.

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