US20230282249A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20230282249A1 US20230282249A1 US18/195,950 US202318195950A US2023282249A1 US 20230282249 A1 US20230282249 A1 US 20230282249A1 US 202318195950 A US202318195950 A US 202318195950A US 2023282249 A1 US2023282249 A1 US 2023282249A1
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- active area
- contact
- semiconductor device
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- area units
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Definitions
- the present disclosure generally relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having active areas and shallow trench isolations, and a method of fabricating the same.
- the size of elements is continuously shrinking and the structure is constantly changing. Therefore, maintaining the performance of small-sized semiconductor elements is the standard purpose of the present industry.
- the semiconductor fabricating process most of the active areas are defined on the substrate as a base element, and then, the required elements are further formed on the active areas.
- the active areas are plural patterns formed within the substrate through the photolithography and etching processes.
- the width of the active areas has been gradually reduced, and the pitch between the active areas has also been gradually reduced thereby, so that, the fabricating process of active areas encounters plenty limitations and challenges that fails to meet the practical product requirements.
- One of the objectives of the present disclosure provides a semiconductor device, in which a relative greater pitch is arranged between an outer-side word line and other word lines adjacent thereto, and a relative smaller pitch is arranged between the inner-side word lines and other word lines adjacent thereto. Accordingly, the process window of the bit line contacts disposed at the outer side may be effectively improved, and also, the direct conduction between the bit lines and the word lines may be successfully avoided.
- one embodiment of the present disclosure provides a semiconductor device including a substrate, and a plurality of word lines.
- the substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation.
- the active structure includes a first active area and a second active area.
- the first active area includes a plurality of active area units parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area to surround all of the active area units.
- the word lines are disposed in the substrate, extending in a second direction to intersect with the active area units and the shallow trench isolation.
- the word lines includes a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged along a third direction perpendicular to the second direction by a first pitch, the second word lines are sequentially arranged along the third direction by a second pitch, and the second pitch is greater than the first pitch.
- one embodiment of the present disclosure provides a semiconductor device including a substrate, and a plurality of word lines.
- the substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation.
- the active structure includes a first active area and a second active area.
- the first active area includes a plurality of active area units parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area to surround all of the active area units.
- the word lines are disposed in the substrate, and the word lines extend along a second direction to intersect with the active area units and the shallow trench isolation.
- the word lines includes a plurality of first word lines and at least one second word line, wherein a part of the active area units have one end directly in contact with the second word lines, and another end directly in contact with the second active area.
- one embodiment of the present disclosure provides a method of fabricating a semiconductor device including the following steps. Firstly, a substrate is provided and the substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation, wherein the active substrate further includes a first active area and a second active area.
- the first active area includes a plurality of active area units parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area to surround all of the active area units.
- a plurality of word lines is formed in the substrate, extending in a second direction to intersect with the active area units and the shallow trench isolation.
- the word lines includes a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged along a third direction perpendicular to the second direction by a first pitch, the second word lines are sequentially arranged along the third direction by a second pitch, and the second pitch is greater than the first pitch.
- FIG. 1 to FIG. 7 are schematic diagrams illustrating a fabricating process of a semiconductor device according to a preferable embodiment in the present disclosure, wherein:
- FIG. 1 is a schematic top view of a semiconductor device after forming an active structure and word lines
- FIG. 2 is a schematic cross-sectional view taken along a cross-line A-A′ in FIG. 1 ;
- FIG. 3 is a schematic top view of a semiconductor device after forming contact openings
- FIG. 4 is a schematic cross-sectional view taken along a cross-line A-A′ in FIG. 3 ;
- FIG. 5 is a schematic top view of a semiconductor device after forming bit lines and contacts
- FIG. 6 is a schematic cross-sectional view taken along a cross-line A-A′ in FIG. 5 ;
- FIG. 7 is a schematic cross-sectional view taken along a cross-line B-B′ in FIG. 5 .
- FIGS. 8 - 9 are schematic diagrams illustrating a fabricating process of a semiconductor device according to another preferable embodiment in the present disclosure, wherein:
- FIG. 8 is a schematic top view of a semiconductor device after forming contact openings.
- FIG. 9 is a schematic cross-sectional view taken along a cross-line A-A′ in FIG. 8 .
- FIGS. 1 - 7 illustrate schematic diagrams of a fabricating process of a semiconductor device 300 according to the preferable embodiment in the present disclosure, with FIG. 1 , FIG. 3 and FIG. 5 respectively illustrating a top view of the semiconductor device 300 at various stages of formation, and with FIG. 2 , FIG. 4 , FIG. 6 , and FIG. 7 respectively illustrating a cross-sectional view of the semiconductor device 300 at various stages of formation.
- the semiconductor device 300 includes a substrate 110 , for example a silicon substrate, a silicon containing substrate (such as SiC or SiGe), or a silicon-on-insulator (SOI) substrate, which includes at least one shallow trench isolation (STI) 120 disposed therein to define an active structure 130 in the substrate 110 .
- STI shallow trench isolation
- the active structure 130 further includes a first active area 131 disposed within a region (for example a region being highly integrity in the semiconductor device 300 ), and a second active area 133 disposed within another region (for example a periphery region being lower integrity in the semiconductor device 300 ).
- the another region for example the periphery region
- the second active area 133 may be disposed around the periphery of the first active area 131 , as shown in FIG. 1 , but not limited thereto.
- the first active area 131 further includes a plurality active area units 131 a, 131 b, 131 c , 131 d which is parallel and separately extended along a first direction D 1 to alternately arrange with each other, wherein the first direction D 1 is for example crossed and not perpendicular to the y-direction (such as a second direction D 2 ) or the x-direction (such as a third direction D 3 ).
- each of the active area units 131 a has the same length L 1 in the first direction D 1 and the same pitch P 1 as well, to sequentially arrange along the first direction D 1 into a plurality of rows, thereby presenting a particular arrangement, such as an array arrangement as shown in FIG. 1 , but not limited thereto.
- the active area units 131 b, 131 c, 131 d respectively have different lengths from the length L 1 , for example, being the lengths L 2 , L 3 , L 4 respectively as shown in FIG.
- the length L 4 may be smaller than the lengths L 1 , L 2 , L 3 , and the length L 3 may be greater than the length L 2 , and the length L 2 may be greater than the length L 1 (L 3 >L 2 >L 1 >L 4 ), but not limited thereto.
- the active area units 131 a, 131 b , 131 c, 131 d are sequentially arranged by the same pitch P 1 along the first direction D 1 into a plurality of rows, with the active area units 131 b, 131 c and 131 d being arranged by the same pitch P 1 outside the periphery of all of the active area units 131 a, such as being disposed at the left side, the bottom side, the right side, and the top side (not shown in the drawings) of all of the active area units 131 a, to present a particular arrangement, such as an array arrangement as shown in FIG. 1 , but not limited thereto.
- the formation of the first active area 131 may but not be limited to be accomplished through the following patterning process.
- a mask layer (not shown in the drawings) may be firstly formed on the substrate 110 , with the mask layer including plural patterns for defining the active area units 131 a, 131 b, 131 c, 131 d of the first active area 131 and with a portion of the substrate 110 being exposed form the mask layer, an etching process is then performed by using the mask layer, to remove the portion of the substrate 110 and to form at least one shallow trench 112 , and an insulating material (not shown in the drawings) for example including silicon oxide (SiO x ), silicon nitride (SiN) or silicon oxiynitride (SiON) is formed to fill in the shallow trench 112 , to form the shallow trench isolation 120 with coplanar surface with the top surface of the substrate 110 , and to simultaneously define the first active area 131 in the substrate 110 , as shown in FIG. 1 and FIG. 2
- the second active area 133 is disposed around the periphery of the first active area 131 .
- the second active area 133 further includes at least two first edge 133 a extended along the second direction D 2 , and at least one second edge 133 b extended along the third direction D 3 .
- the first edges 133 a are opposite to each other and are adjacent to the second edge 133 b to arrange in sequence, such that, the whole second active area 133 may perform like a rectangular frame (not shown in the drawings) to directly in contact with the a part of the active area units 131 b, 131 c, 131 d.
- the part of the active area units 131 b, 131 c , 131 d may further connect to the first edge 133 a and/or the second edge 133 b of the second active area 133 directly, and another part of the active area units 131 a may be spaced apart from the first edge 133 a and/or the second edge 133 b of the second active area 133 , instead of being connected thereto, as shown in FIG. 1 .
- first edge 133 a and the second edge 133 b may include the same width T 1 , and the width T 1 is preferably greater than the width W of each of the active area units 131 a, 131 b, 131 c, 131 d, but is not limited thereto.
- the second active area 133 may be allowable to uniformly disperse the stresses suffered from the active area units 131 b, 131 c, 131 d and the shallow trench isolation 120 , thereby obtaining a further reliable structure.
- the second active area 133 may also not contact any active area units 131 a, 131 b, 131 c, 131 d at all optionally, or the width T 1 of the second edge 133 b and the first edge 133 a may also be the same or smaller than the width W of the active area units 131 a, based on practical product requirements. People in the art should fully realize that the practical disposing number of the first edge or the second edge may be further adjustable due to practical product requirements, or the second active area is not limited to be the aforementioned rectangular frame, for example, further edges may be additionally disposed to make the second active area to perform like various shapes.
- the formation of the second active area 133 may also be accomplished through the patterning process of the substrate 110 , and which may optionally be carried out together with the patterning process of the first active area 131 . That is, in the present embodiment, the same or different mask layer(s) may be used to either simultaneously define or separately define the patterns of the first active area 131 and the second active area 133 , followed by etching the substrate 110 , and filling in the insulating material.
- the first active area 131 and the second active area 133 may include the same material, namely the material of the substrate 110 , and also, the first edge 133 a and the second edges 133 b of the second active area 133 , and the active area units 131 b, 131 c, 131 d which are connected with the first edge 133 a and the second edges 133 b maybe monolithic, as shown in FIG. 1 .
- the active area units 131 b, 131 c, 131 d of the first active area 131 which are connected to the first edge 133 a or the second edges 133 b of the second active area 133 may be serve as an inward extension of the first edge 133 a and the second edges 133 b, so that, the second active area 133 may obtain a relative stable, strengthened structure to protect the first active area 131 , particular to the active area units 131 a, disposed at the inner side thereof. Then, the possible structural collapse or damage of the active area units 131 a may be successfully avoided.
- the formation of the second active area is not limited to be accomplished through the aforementioned process, and may also be formed through other processes, for example being carried out separately from the formation of the first active area.
- the fabricating process of the second active area may be performed before the fabricating process of the first active area, in which, the second active area may be formed firstly through the patterning process of the substrate, and the first active area is then formed by performing an epitaxial growth process (not shown in the drawings). Accordingly, the topmost surfaces of the second active area and first active area may not be leveled with each other.
- the fabricating process of the second active area may also be performed after the fabricating process of the first active area, in which, the first active area is firstly formed through the patterning process of the substrate, and the second active area is then formed through a deposition process.
- the second active area and the first active area may include different materials, for example, the second active area may include polysilicon or a dielectric material which is different from that of the substrate.
- a plurality of gate structure preferably a plurality of buried gate structures 140 , is formed in the substrate 110 .
- a plurality of trenches 141 which is parallel with each other and extends along the second direction D 2 is firstly formed in the substrate 110 .
- an interface dielectric layer 142 entirely covering surfaces of each of the trenches 141 , a gate dielectric layer 143 covering bottom surfaces of each of the trenches 141 , a gate electrode layer 144 filling up the bottom of each of the trenches 141 , and a mask layer 145 filling up the top of each of the trenches 141 are sequentially formed in the trenches 141 .
- each of the buried gate structures 140 embedded in the substrate 110 may therefore function like a word line (WL) of the semiconductor device 300 , wherein each word line is parallel with the first edge 133 a of the second active area 133 to intersect with the active area units 131 a, 131 b, 131 c, 131 d and the shallow trench isolation 120 disposed between the active area units 131 a, 131 b, 131 c, 131 d, for receiving or transmitting voltage signals from each memory cell formed in the subsequent process (not shown in the drawings).
- WL word line
- the word lines are sequentially arranged along the third direction D 3 , and further include a plurality of first word lines 140 a and a plurality of second word lines 140 b, wherein the first word lines 140 a are sequentially arranged by a first pitch P 2 along the third direction D 3 , and the second word lines 140 b are arranged at two opposite sides of all of the first word lines 140 a along the third direction D 3 by a second pitch P 3 , and the second pitch P 3 is greater that the first pitch P 2 , as shown in FIG. 1 and FIG. 2 .
- the first word lines 140 a pass through the middle portions of the active area units 131 a, 131 d, and the second word lines 140 b pass through the middle portions of the active area units 131 c and directly contact the end portions of the active area units 131 b.
- a part of the active area units 131 b directly contact the second word lines 140 b through one end thereof, and directly contact the first edge 133 a of the second active area 133 through another end thereof, as shown in FIG. 1 .
- the insulating layer 150 is formed on the top surface of the substrate 110 , to entirely cover the substrate 110 and to directly contact the buried gate structures 140 and the shallow trench isolation 120 disposed in the substrate 110 .
- the insulating layer 150 for example includes an oxide-nitride-oxide (ONO) structure, but is not limited thereto.
- an etching process is performed to remove a portion of the insulating layer 150 and a portion of the substrate 110 underneath, to form a plurality of contact openings 155 in the substrate 110 , with each of the contact openings 155 being formed between two adjacent ones of the word lines (namely the buried gate structures 140 ) to partially expose the substrate 110 .
- the contact openings 155 further include at least one first contact opening 155 a and at least one second contact opening 155 b, wherein the first contact opening 155 a is disposed on the active area unit 131 a, between two adjacent ones of the first word lines 140 a, and the second contact openings 155 b is also disposed on the active area unit 131 a, between adjacent ones of the first word lines 140 a and the second word lines 140 b. That is, neither the first contact opening 155 a, nor the second contact opening 155 b is disposed on the active area units 131 b, 131 c, 131 d which are further connected to the second active area 133 , as shown in FIG. 3 .
- the first contact opening 155 a includes an aperture O 1 in the first direction D 1
- the second contact opening 155 b includes an aperture O 2 in the first direction D 1 .
- the aperture O 2 of the second contact opening 155 b may also be greater than the aperture O 1 of the first contact opening 155 a, as shown in FIG. 3 .
- the arranged pitch P 3 of the second word lines 140 b may correspondingly enlarge the process window of the second contact opening 155 b.
- bit line (BL) 160 is formed on the substrate 110 .
- BL bit line
- FIG. 5 to FIG. 7 a plurality of bit lines 160 is formed in the present embodiment, wherein each of the bit lines 160 is parallel and separately extended along the third direction D 3 to intersect the word lines (namely the buried gate structures 140 ) and the active area units 131 a, 131 b, 131 c, 131 d.
- Each of the bit lines further includes a semiconductor layer 161 , a barrier layer 162 , a conductive layer 163 , and a mask layer 164 sequentially stacked from bottom to top on the insulating layer 150 , with the semiconductor layer 161 for example including polysilicon, with the barrier layer 162 for example including titanium (Ti) or titanium nitride (TiN), with the conductive layer 163 for example including a low resistant metal like tungsten (W), aluminum (Al) or copper (Cu), and with the mask layer 154 for example including silicon oxide, silicon nitride, or silicon oxynitride, but not limited thereto.
- the semiconductor layer 161 for example including polysilicon
- the barrier layer 162 for example including titanium (Ti) or titanium nitride (TiN)
- the conductive layer 163 for example including a low resistant metal like tungsten (W), aluminum (Al) or copper (Cu)
- the mask layer 154 for example including silicon oxide, silicon nitride
- bit line contacts (namely the contacts 170 ) are integrally formed with the bit lines 160 as shown in FIG. 7 , and directly contact a part of the active area units 131 a, so as to electrically connect to a transistor element (not shown in the drawings) disposed in the substrate 110 for receiving or transmitting voltage signals from each of the memory cells formed in the subsequent processes. It is noted that, in other to clearly present the bit lines 160 , the contacts 170 are not illustrated in FIG.
- the contacts 170 further includes at least one first contact 170 a and at least one second contact 170 b , the first contact 170 a is disposed on the active area unit 131 a , between two adjacent ones of the first word lines 140 a, and the second contact 170 b is also disposed on the active area unit 131 a, between adjacent ones of the first word lines 140 a and the second word lines 140 b.
- the contacts 170 are not disposed on the active area units 131 b, 131 c, 131 d which are further connected to the second active area 133 , and which will not contact thereto. Accordingly, the first contact 170 a may have a relative smaller width O 1 in the first direction D 1 , and the second contact 170 b may have a relative greater width O 2 in the first direction D 1 due to the arranged greater pitch P 3 of the second word lines 140 b, as shown in FIG. 6 and FIG. 7 .
- a plurality of contacts 180 , 190 is formed on the bit lines 160 and the word lines (namely the buried gate structures 140 ) respectively, wherein the contacts 180 are alternately disposed at two ends (not shown in the drawings, for example referring to the right end and the left end of the bit lines 160 as shown in FIG. 5 ) of the bit lines 160 , to electrically connect thereto.
- the contacts 180 may be disposed on the right ends of the odd-numbered bit lines 160 and on the left ends of the even-numbered bit lines 160 , as shown in FIG. 5 , but is not limited thereto.
- the contacts 190 may also be disposed in the same or similar manner of the contacts 180 , for example, the contacts 190 may be disposed on the bottom ends of the odd-numbered word lines (namely, the buried gate structures 140 ) and on the top ends (not shown in the drawings) of the even-numbered word lines (namely, the buried gate structures 140 ), but are not limited thereto. With such arrangements, the contacts 180 , 190 may obtain enough process windows, and which may electrically connect the bit lines 160 and the word lines (namely, the buried gate structure 140 ) respectively through the end portions of the bit lines 160 and the word lines.
- the semiconductor device 300 accordingly to the preferred embodiment is completed.
- the semiconductor device 300 includes the second active area 133 disposed around the periphery of the first active area 131 , with a part of the active area units 131 b, 131 c, 131 d being further connected to the first edge 133 a and/or the second edge 133 b of the second active area 133 , so as to disperse the stresses suffered from the shallow trench isolation 120 , thereby obtaining a further reliable structure.
- the semiconductor device 300 includes the word lines (namely the buried gate structures 140 ) arranged by different pitches, with a relative greater pitch P 3 being arranged between the outer-side word line 140 b and the word line 140 a adjacent thereto, and with a relative smaller pitch P 2 being arranged between the inner-side word lines 140 a and the word lines 140 a adjacent thereto.
- the contact 170 a disposed between two adjacent ones of the word lines 140 a may correspondingly obtain a relative smaller width O 1
- the contact 170 b disposed between adjacent ones of the word lines 140 a, 140 b may correspondingly obtain a relative greater width O 2 , so as to improve the process window of the bit line contacts (namely, the contact 170 a ) disposed at the outer side, and to avoid the direct conduction between the bit lines and the word lines.
- the semiconductor device 300 of the present disclosure may gain better functions and performances thereby.
- the semiconductor device and the fabricating method thereof are not be limited to aforementioned embodiment and may include other examples or may be achieved through other strategies to meet practical product requirements.
- the etching conditions may be further adjusted during the patterning process of the second active area to form the second active area with rounding corners, or to form the second active area with plural openings disposed thereon for further dispersing stresses, but not limited thereto.
- the pitch P 3 ′ of the second word lines 140 b in third direction D 3 may be further enlarged, and the second word lines 140 b may only pass through the middle portions of the active area units 131 b, 131 c without contacting to any of the active area units 131 a. Accordingly, since the pitch P 3 ′ of the second word lines 140 b is further enlarged, the aperture O 2 ′ of the second contact opening 155 b may be enlarged laterally, with the sidewall of the second contact opening 155 b being vertically aligned with the end portion of the active area unit 131 a , as shown in FIGS. 8 - 9 .
- the second word lines 140 b may function like dummy word lines to protect the inner-side first word lines 140 a, and also, the process window of the bit line contacts formed subsequently may be further improved. Then, the semiconductor device 500 of the present disclosure may gain better functions and performances thereby.
Abstract
The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and second word lines arranged by a second pitch, and the second pitch is greater than the first pitch.
Description
- This application is a continuation application of U.S. application Ser. No. 17/387,992, filed on Jul. 28, 2021. The content of the application is incorporated herein by reference.
- The present disclosure generally relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having active areas and shallow trench isolations, and a method of fabricating the same.
- With the miniaturization of semiconductor devices and the complexity of integrated circuits, the size of elements is continuously shrinking and the structure is constantly changing. Therefore, maintaining the performance of small-sized semiconductor elements is the standard purpose of the present industry. In the semiconductor fabricating process, most of the active areas are defined on the substrate as a base element, and then, the required elements are further formed on the active areas. Generally, the active areas are plural patterns formed within the substrate through the photolithography and etching processes. However, due to the sized-shrinking requirements, the width of the active areas has been gradually reduced, and the pitch between the active areas has also been gradually reduced thereby, so that, the fabricating process of active areas encounters plenty limitations and challenges that fails to meet the practical product requirements.
- One of the objectives of the present disclosure provides a semiconductor device, in which a relative greater pitch is arranged between an outer-side word line and other word lines adjacent thereto, and a relative smaller pitch is arranged between the inner-side word lines and other word lines adjacent thereto. Accordingly, the process window of the bit line contacts disposed at the outer side may be effectively improved, and also, the direct conduction between the bit lines and the word lines may be successfully avoided.
- To achieve the purpose described above, one embodiment of the present disclosure provides a semiconductor device including a substrate, and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation. The active structure includes a first active area and a second active area. The first active area includes a plurality of active area units parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area to surround all of the active area units. The word lines are disposed in the substrate, extending in a second direction to intersect with the active area units and the shallow trench isolation. The word lines includes a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged along a third direction perpendicular to the second direction by a first pitch, the second word lines are sequentially arranged along the third direction by a second pitch, and the second pitch is greater than the first pitch.
- To achieve the purpose described above, one embodiment of the present disclosure provides a semiconductor device including a substrate, and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation. The active structure includes a first active area and a second active area. The first active area includes a plurality of active area units parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area to surround all of the active area units. The word lines are disposed in the substrate, and the word lines extend along a second direction to intersect with the active area units and the shallow trench isolation. The word lines includes a plurality of first word lines and at least one second word line, wherein a part of the active area units have one end directly in contact with the second word lines, and another end directly in contact with the second active area.
- To achieve the purpose described above, one embodiment of the present disclosure provides a method of fabricating a semiconductor device including the following steps. Firstly, a substrate is provided and the substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation, wherein the active substrate further includes a first active area and a second active area. The first active area includes a plurality of active area units parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area to surround all of the active area units. Then, a plurality of word lines is formed in the substrate, extending in a second direction to intersect with the active area units and the shallow trench isolation. The word lines includes a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged along a third direction perpendicular to the second direction by a first pitch, the second word lines are sequentially arranged along the third direction by a second pitch, and the second pitch is greater than the first pitch.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 toFIG. 7 are schematic diagrams illustrating a fabricating process of a semiconductor device according to a preferable embodiment in the present disclosure, wherein: -
FIG. 1 is a schematic top view of a semiconductor device after forming an active structure and word lines; -
FIG. 2 is a schematic cross-sectional view taken along a cross-line A-A′ inFIG. 1 ; -
FIG. 3 is a schematic top view of a semiconductor device after forming contact openings; -
FIG. 4 is a schematic cross-sectional view taken along a cross-line A-A′ inFIG. 3 ; -
FIG. 5 is a schematic top view of a semiconductor device after forming bit lines and contacts; -
FIG. 6 is a schematic cross-sectional view taken along a cross-line A-A′ inFIG. 5 ; and -
FIG. 7 is a schematic cross-sectional view taken along a cross-line B-B′ inFIG. 5 . -
FIGS. 8-9 are schematic diagrams illustrating a fabricating process of a semiconductor device according to another preferable embodiment in the present disclosure, wherein: -
FIG. 8 is a schematic top view of a semiconductor device after forming contact openings; and -
FIG. 9 is a schematic cross-sectional view taken along a cross-line A-A′ inFIG. 8 . - To provide a better understanding of the presented disclosure, preferred embodiments will be described in detail. The preferred embodiments of the present disclosure are illustrated in the accompanying drawings with numbered elements. In addition, the technical features in different embodiments described in the following may be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present disclosure.
- Please refer to
FIGS. 1-7 , which illustrate schematic diagrams of a fabricating process of asemiconductor device 300 according to the preferable embodiment in the present disclosure, withFIG. 1 ,FIG. 3 andFIG. 5 respectively illustrating a top view of thesemiconductor device 300 at various stages of formation, and withFIG. 2 ,FIG. 4 ,FIG. 6 , andFIG. 7 respectively illustrating a cross-sectional view of thesemiconductor device 300 at various stages of formation. Thesemiconductor device 300 includes asubstrate 110, for example a silicon substrate, a silicon containing substrate (such as SiC or SiGe), or a silicon-on-insulator (SOI) substrate, which includes at least one shallow trench isolation (STI) 120 disposed therein to define anactive structure 130 in thesubstrate 110. That is, theshallow trench isolation 120 is disposed around theactive structure 130. Theactive structure 130 further includes a firstactive area 131 disposed within a region (for example a region being highly integrity in the semiconductor device 300), and a secondactive area 133 disposed within another region (for example a periphery region being lower integrity in the semiconductor device 300). Preferably, the another region (for example the periphery region) is disposed outside the periphery of the region (for example the region), so that, the secondactive area 133 may be disposed around the periphery of the firstactive area 131, as shown inFIG. 1 , but not limited thereto. - Please referring to
FIG. 1 andFIG. 2 , the firstactive area 131 further includes a pluralityactive area units active area units 131 a has the same length L1 in the first direction D1 and the same pitch P1 as well, to sequentially arrange along the first direction D1 into a plurality of rows, thereby presenting a particular arrangement, such as an array arrangement as shown inFIG. 1 , but not limited thereto. Theactive area units FIG. 1 , wherein the length L4 may be smaller than the lengths L1, L2, L3, and the length L3 may be greater than the length L2, and the length L2 may be greater than the length L1 (L3>L2>L1>L4), but not limited thereto. Also, in the first direction D1, theactive area units active area units active area units 131 a, such as being disposed at the left side, the bottom side, the right side, and the top side (not shown in the drawings) of all of theactive area units 131 a, to present a particular arrangement, such as an array arrangement as shown inFIG. 1 , but not limited thereto. - In one embodiment, the formation of the first
active area 131 may but not be limited to be accomplished through the following patterning process. For example, a mask layer (not shown in the drawings) may be firstly formed on thesubstrate 110, with the mask layer including plural patterns for defining theactive area units active area 131 and with a portion of thesubstrate 110 being exposed form the mask layer, an etching process is then performed by using the mask layer, to remove the portion of thesubstrate 110 and to form at least oneshallow trench 112, and an insulating material (not shown in the drawings) for example including silicon oxide (SiOx), silicon nitride (SiN) or silicon oxiynitride (SiON) is formed to fill in theshallow trench 112, to form theshallow trench isolation 120 with coplanar surface with the top surface of thesubstrate 110, and to simultaneously define the firstactive area 131 in thesubstrate 110, as shown inFIG. 1 andFIG. 2 . In one embodiment, the formation of the firstactive area 131 may also be accomplished by a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but not limited thereto. - Please referring to
FIG. 1 , the secondactive area 133 is disposed around the periphery of the firstactive area 131. In the present embodiment, the secondactive area 133 further includes at least twofirst edge 133 a extended along the second direction D2, and at least onesecond edge 133 b extended along the third direction D3. The first edges 133 a are opposite to each other and are adjacent to thesecond edge 133 b to arrange in sequence, such that, the whole secondactive area 133 may perform like a rectangular frame (not shown in the drawings) to directly in contact with the a part of theactive area units active area 133 is formed, the part of theactive area units first edge 133 a and/or thesecond edge 133 b of the secondactive area 133 directly, and another part of theactive area units 131 a may be spaced apart from thefirst edge 133 a and/or thesecond edge 133 b of the secondactive area 133, instead of being connected thereto, as shown inFIG. 1 . Furthermore, thefirst edge 133 a and thesecond edge 133 b may include the same width T1, and the width T1 is preferably greater than the width W of each of theactive area units active area 133 may be allowable to uniformly disperse the stresses suffered from theactive area units shallow trench isolation 120, thereby obtaining a further reliable structure. However, in another embodiment (not shown in the drawings), the secondactive area 133 may also not contact anyactive area units second edge 133 b and thefirst edge 133 a may also be the same or smaller than the width W of theactive area units 131 a, based on practical product requirements. People in the art should fully realize that the practical disposing number of the first edge or the second edge may be further adjustable due to practical product requirements, or the second active area is not limited to be the aforementioned rectangular frame, for example, further edges may be additionally disposed to make the second active area to perform like various shapes. - It is noted that, in the present embodiment, the formation of the second
active area 133 may also be accomplished through the patterning process of thesubstrate 110, and which may optionally be carried out together with the patterning process of the firstactive area 131. That is, in the present embodiment, the same or different mask layer(s) may be used to either simultaneously define or separately define the patterns of the firstactive area 131 and the secondactive area 133, followed by etching thesubstrate 110, and filling in the insulating material. Then, the firstactive area 131 and the secondactive area 133 may include the same material, namely the material of thesubstrate 110, and also, thefirst edge 133 a and thesecond edges 133 b of the secondactive area 133, and theactive area units first edge 133 a and thesecond edges 133 b maybe monolithic, as shown inFIG. 1 . In this situation, theactive area units active area 131 which are connected to thefirst edge 133 a or thesecond edges 133 b of the secondactive area 133 may be serve as an inward extension of thefirst edge 133 a and thesecond edges 133 b, so that, the secondactive area 133 may obtain a relative stable, strengthened structure to protect the firstactive area 131, particular to theactive area units 131 a, disposed at the inner side thereof. Then, the possible structural collapse or damage of theactive area units 131 a may be successfully avoided. However, people in the art should fully realize that the formation of the second active area is not limited to be accomplished through the aforementioned process, and may also be formed through other processes, for example being carried out separately from the formation of the first active area. As an example, in one embodiment, the fabricating process of the second active area may be performed before the fabricating process of the first active area, in which, the second active area may be formed firstly through the patterning process of the substrate, and the first active area is then formed by performing an epitaxial growth process (not shown in the drawings). Accordingly, the topmost surfaces of the second active area and first active area may not be leveled with each other. Otherwise, in another embodiment, the fabricating process of the second active area may also be performed after the fabricating process of the first active area, in which, the first active area is firstly formed through the patterning process of the substrate, and the second active area is then formed through a deposition process. Accordingly, the second active area and the first active area may include different materials, for example, the second active area may include polysilicon or a dielectric material which is different from that of the substrate. - Next, as shown in
FIG. 1 andFIG. 2 , a plurality of gate structure, preferably a plurality of buriedgate structures 140, is formed in thesubstrate 110. In the present embodiment, a plurality oftrenches 141 which is parallel with each other and extends along the second direction D2 is firstly formed in thesubstrate 110. Then, aninterface dielectric layer 142 entirely covering surfaces of each of thetrenches 141, agate dielectric layer 143 covering bottom surfaces of each of thetrenches 141, agate electrode layer 144 filling up the bottom of each of thetrenches 141, and amask layer 145 filling up the top of each of thetrenches 141, are sequentially formed in thetrenches 141. Then, the topmost surface of themask layer 145 may be coplanar with the top surface of thesubstrate 110, as shown inFIG. 2 . Then, each of the buriedgate structures 140 embedded in thesubstrate 110 may therefore function like a word line (WL) of thesemiconductor device 300, wherein each word line is parallel with thefirst edge 133 a of the secondactive area 133 to intersect with theactive area units shallow trench isolation 120 disposed between theactive area units first word lines 140 a and a plurality of second word lines 140 b, wherein thefirst word lines 140 a are sequentially arranged by a first pitch P2 along the third direction D3, and the second word lines 140 b are arranged at two opposite sides of all of thefirst word lines 140 a along the third direction D3 by a second pitch P3, and the second pitch P3 is greater that the first pitch P2, as shown inFIG. 1 andFIG. 2 . In addition, it is noted that, thefirst word lines 140 a pass through the middle portions of theactive area units active area units 131 c and directly contact the end portions of theactive area units 131 b. In other words, a part of theactive area units 131 b directly contact the second word lines 140 b through one end thereof, and directly contact thefirst edge 133 a of the secondactive area 133 through another end thereof, as shown inFIG. 1 . - Next, as shown
FIG. 3 (in which an insulatinglayer 150 is omitted) andFIG. 4 , the insulatinglayer 150 is formed on the top surface of thesubstrate 110, to entirely cover thesubstrate 110 and to directly contact the buriedgate structures 140 and theshallow trench isolation 120 disposed in thesubstrate 110. The insulatinglayer 150 for example includes an oxide-nitride-oxide (ONO) structure, but is not limited thereto. Then, an etching process is performed to remove a portion of the insulatinglayer 150 and a portion of thesubstrate 110 underneath, to form a plurality ofcontact openings 155 in thesubstrate 110, with each of thecontact openings 155 being formed between two adjacent ones of the word lines (namely the buried gate structures 140) to partially expose thesubstrate 110. Precisely speaking, thecontact openings 155 further include at least one first contact opening 155 a and at least one second contact opening 155 b, wherein the first contact opening 155 a is disposed on theactive area unit 131 a, between two adjacent ones of thefirst word lines 140 a, and thesecond contact openings 155 b is also disposed on theactive area unit 131 a, between adjacent ones of thefirst word lines 140 a and the second word lines 140 b. That is, neither the first contact opening 155 a, nor the second contact opening 155 b is disposed on theactive area units active area 133, as shown inFIG. 3 . Also, the first contact opening 155 a includes an aperture O1 in the first direction D1, and the second contact opening 155 b includes an aperture O2 in the first direction D1. It is noted that, since the pitch P3 of the second word lines 140 b is relative greater, the aperture O2 of the second contact opening 155 b may also be greater than the aperture O1 of the first contact opening 155 a, as shown inFIG. 3 . In other words, the arranged pitch P3 of the second word lines 140 b may correspondingly enlarge the process window of the second contact opening 155 b. - Following these, at least a bit line (BL) 160 is formed on the
substrate 110. As shown inFIG. 5 toFIG. 7 , a plurality ofbit lines 160 is formed in the present embodiment, wherein each of the bit lines 160 is parallel and separately extended along the third direction D3 to intersect the word lines (namely the buried gate structures 140) and theactive area units semiconductor layer 161, abarrier layer 162, aconductive layer 163, and amask layer 164 sequentially stacked from bottom to top on the insulatinglayer 150, with thesemiconductor layer 161 for example including polysilicon, with thebarrier layer 162 for example including titanium (Ti) or titanium nitride (TiN), with theconductive layer 163 for example including a low resistant metal like tungsten (W), aluminum (Al) or copper (Cu), and with the mask layer 154 for example including silicon oxide, silicon nitride, or silicon oxynitride, but not limited thereto. Among them, a part of thebit lines 160 may be overlapped with thecontact openings 155, so that, a portion of thesemiconductor layer 161 may be filled in thecontact openings 155 to form thecontacts 170, to serve as bit line contacts (BLCs) thereby. With these arrangements, the bit line contacts (namely the contacts 170) are integrally formed with thebit lines 160 as shown inFIG. 7 , and directly contact a part of theactive area units 131 a, so as to electrically connect to a transistor element (not shown in the drawings) disposed in thesubstrate 110 for receiving or transmitting voltage signals from each of the memory cells formed in the subsequent processes. It is noted that, in other to clearly present thebit lines 160, thecontacts 170 are not illustrated inFIG. 5 , and the specific locations of thecontacts 170 maybe referred to the locations of thecontact openings 155 shown inFIG. 3 . Precisely speaking, thecontacts 170 further includes at least onefirst contact 170 a and at least onesecond contact 170 b, thefirst contact 170 a is disposed on theactive area unit 131 a, between two adjacent ones of thefirst word lines 140 a, and thesecond contact 170 b is also disposed on theactive area unit 131 a, between adjacent ones of thefirst word lines 140 a and the second word lines 140 b. That is, the contacts 170 (including thefirst contact 170 a and thesecond contact 170 b) are not disposed on theactive area units active area 133, and which will not contact thereto. Accordingly, thefirst contact 170 a may have a relative smaller width O1 in the first direction D1, and thesecond contact 170 b may have a relative greater width O2 in the first direction D1 due to the arranged greater pitch P3 of the second word lines 140 b, as shown inFIG. 6 andFIG. 7 . - Then, as shown in
FIG. 5 , a plurality ofcontacts bit lines 160 and the word lines (namely the buried gate structures 140) respectively, wherein thecontacts 180 are alternately disposed at two ends (not shown in the drawings, for example referring to the right end and the left end of thebit lines 160 as shown inFIG. 5 ) of thebit lines 160, to electrically connect thereto. For example, thecontacts 180 may be disposed on the right ends of the odd-numberedbit lines 160 and on the left ends of the even-numberedbit lines 160, as shown inFIG. 5 , but is not limited thereto. On the other hand, thecontacts 190 may also be disposed in the same or similar manner of thecontacts 180, for example, thecontacts 190 may be disposed on the bottom ends of the odd-numbered word lines (namely, the buried gate structures 140) and on the top ends (not shown in the drawings) of the even-numbered word lines (namely, the buried gate structures 140), but are not limited thereto. With such arrangements, thecontacts bit lines 160 and the word lines (namely, the buried gate structure 140) respectively through the end portions of thebit lines 160 and the word lines. - Through the aforementioned arrangements, the
semiconductor device 300 accordingly to the preferred embodiment is completed. thesemiconductor device 300 includes the secondactive area 133 disposed around the periphery of the firstactive area 131, with a part of theactive area units first edge 133 a and/or thesecond edge 133 b of the secondactive area 133, so as to disperse the stresses suffered from theshallow trench isolation 120, thereby obtaining a further reliable structure. Moreover, thesemiconductor device 300 includes the word lines (namely the buried gate structures 140) arranged by different pitches, with a relative greater pitch P3 being arranged between the outer-side word line 140 b and theword line 140 a adjacent thereto, and with a relative smaller pitch P2 being arranged between the inner-side word lines 140 a and the word lines 140 a adjacent thereto. Accordingly, thecontact 170 a disposed between two adjacent ones of the word lines 140 a may correspondingly obtain a relative smaller width O1, and thecontact 170 b disposed between adjacent ones of the word lines 140 a, 140 b may correspondingly obtain a relative greater width O2, so as to improve the process window of the bit line contacts (namely, thecontact 170 a) disposed at the outer side, and to avoid the direct conduction between the bit lines and the word lines. Based on these arrangements, thesemiconductor device 300 of the present disclosure may gain better functions and performances thereby. - However, people in the art should fully realize that the semiconductor device and the fabricating method thereof are not be limited to aforementioned embodiment and may include other examples or may be achieved through other strategies to meet practical product requirements. For example, in one embodiment, the etching conditions may be further adjusted during the patterning process of the second active area to form the second active area with rounding corners, or to form the second active area with plural openings disposed thereon for further dispersing stresses, but not limited thereto.
- Furthermore, in another embodiment as shown in
FIGS. 8-9 , the pitch P3′ of the second word lines 140 b in third direction D3 may be further enlarged, and the second word lines 140 b may only pass through the middle portions of theactive area units active area units 131 a. Accordingly, since the pitch P3′ of the second word lines 140 b is further enlarged, the aperture O2′ of the second contact opening 155 b may be enlarged laterally, with the sidewall of the second contact opening 155 b being vertically aligned with the end portion of theactive area unit 131 a, as shown inFIGS. 8-9 . In other word, while forming thecontact openings 155, a great portion of theactive area unit 131 a is removed for forming thesecond contact openings 155 b, and the remained portion of theactive area unit 131 a may therefore obtain a reduced length L1′ as shown inFIG. 9 . Through these arrangements, the second word lines 140 b may function like dummy word lines to protect the inner-sidefirst word lines 140 a, and also, the process window of the bit line contacts formed subsequently may be further improved. Then, thesemiconductor device 500 of the present disclosure may gain better functions and performances thereby. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (20)
1. A semiconductor device, comprising;
a substrate comprising a shallow trench isolation and an active structure defined by the shallow trench isolation, the active structure comprising:
a first active area comprising a plurality of active area units being parallel extended along a first direction; and
a second active area disposed outside a periphery of the first active area, to surround all of the active area units; and
a plurality of word lines, disposed in the substrate, extending in a second direction to intersect with the active area units and the shallow trench isolation, wherein the word lines comprises a plurality of first word lines and at least one second word line, the first word lines are sequentially arranged along a third direction perpendicular to the second direction by a first pitch, the at least one second word line is arranged along the third direction by a second pitch, and the second pitch is greater than the first pitch.
2. The semiconductor device according to claim 1 , further comprising:
at least one first contact, disposed on the active area units and between two adjacent ones of the first word lines; and
at least one second contact, disposed on the active area units and between adjacent ones of the first word lines and the at least one second word line, wherein a width of the at least one second contact in the first direction is greater than a width of the at least one first contact in the first direction.
3. The semiconductor device according to claim 2 , wherein one of the active area units connects to the second active area, and the at least one second contact does not contact the one of the active area units.
4. The semiconductor device according to claim 2 , wherein the at least one second word line directly contacts an end portion of one of the active area units.
5. The semiconductor device according to claim 4 , wherein the one of the active area units does not contact the second active area.
6. The semiconductor device according to claim 4 , wherein the one of the active area units directly contacts the second active area.
7. The semiconductor device according to claim 5 , wherein sidewalls of the at least one second word line and the at least one second contact are vertically aligned with each other.
8. The semiconductor device according to claim 2 , further comprising:
a plurality of bit lines, disposed on the substrate to intersect with the word lines, the bit lines extended along the third direction to connect to the at least one first contact and the at least one second contact respectively.
9. The semiconductor device according to claim 8 , wherein the bit lines are integrally formed with the at least one first contact and the at least one second contact, respectively.
10. The semiconductor device according to claim 1 , wherein the second active area comprises a first edge extending along the second direction, and a second edge extending along the third direction, and the first edge is parallel with the word lines.
11. The semiconductor device according to claim 1 , wherein one of the active area units has one end directly in contact with the at least one second word line, and another end directly in contact with the second active area.
12. A semiconductor device, comprising;
a substrate comprising a shallow trench isolation and an active structure defined by the shallow trench isolation, the active structure comprising:
a first active area comprising a plurality of active area units being parallel extended along a first direction; and
a second active area disposed outside a periphery of the first active area, to surround all of the active area units; and
a plurality of word lines, disposed in the substrate, extending in a second direction to intersect with the active area units and the shallow trench isolation, wherein the word lines comprises a plurality of first word lines and at least one second word line, the at least one second word line directly contacts an end portion of one of the active area units.
13. The semiconductor device according to claim 12 , wherein the one of the active area units does not contact the second active area.
14. The semiconductor device according to claim 12 , wherein the one of the active area units directly contacts the second active area.
15. The semiconductor device according to claim 14 , one end of the one of the active area units directly in contact with the at least one second word line and another end of the one of the active area units directly in contact with the second active area.
16. The semiconductor device according to claim 12 , wherein the first word lines are sequentially arranged along a third direction perpendicular to the second direction by a first pitch, the at least one second word line is arranged along the third direction by a second pitch, and the second pitch is greater than the first pitch.
17. The semiconductor device according to claim 16 , further comprising:
at least one first contact, disposed on the active area units and between two adjacent ones of the first word lines; and
at least one second contact, disposed on the active area units and between adjacent ones of the first word lines and the at least one second word line, wherein a width of the at least one second contact in the first direction is greater than a width of the at least one first contact in the first direction.
18. The semiconductor device according to claim 17 , wherein the at least one first contact and the second contact do not contact the one of the active area units.
19. The semiconductor device according to claim 17 , wherein the at least one second contact contacts the one of the active area units, and sidewalls of the at least one second word line and the at least one second contact are vertically aligned with each other.
20. The semiconductor device according to claim 16 , further comprising:
a plurality of bit lines, disposed on the substrate to intersect with the word lines, the bit lines extended along the third direction to connect to the at least one first contact and the at least one second contact respectively, wherein the bit lines, the at least one first contact, and the at least one second contact are monolithic.
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CN202121418739.6U CN215342597U (en) | 2021-06-24 | 2021-06-24 | Semiconductor memory device with a plurality of memory cells |
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