CN215342597U - Semiconductor memory device with a plurality of memory cells - Google Patents

Abstract

The present disclosure discloses a semiconductor memory device including a substrate, an active structure, a shallow trench isolation, and a plurality of word lines. The active structure is disposed in the substrate and further includes a first active region and a second active region. The first active region includes a plurality of active region cells parallel to each other and extending along the first direction, and the second active region is disposed outside the first active region, surrounding all of the active region cells. Shallow trench isolations are disposed in the substrate surrounding the active structures. Word lines are disposed in the substrate and interleaved with the active area cells. The word lines include first word lines arranged at a first pitch and second word lines arranged at a second pitch, wherein the second pitch is greater than the first pitch. Therefore, the manufacturing process space of the bit line contact arranged on the outer side can be improved, and meanwhile, the direct conduction between the word line and the bit line can be avoided.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

The present disclosure relates generally to semiconductor memory devices, and more particularly to a semiconductor memory device including an active structure and shallow trench isolation.

Background

As semiconductor devices are miniaturized and integrated circuits are complicated, device sizes are continuously reduced and structures are continuously changed, so that maintaining the performance of small-sized semiconductor devices is a major goal in the industry. In a semiconductor fabrication process, a plurality of active regions are defined on a substrate as a basis, and then required components are formed on the active regions. Generally, the active regions are formed by photolithography and etching processes to form a plurality of patterns on the substrate, but the width of the active regions is gradually reduced and the distance between the active regions is also gradually reduced under the requirement of size reduction, so that the manufacturing process thereof also faces many limitations and challenges, and thus cannot meet the product requirements.

SUMMERY OF THE UTILITY MODEL

An objective of the present disclosure is to provide a semiconductor memory device, in which a relatively large space is formed between an outer word line and an adjacent word line, and a relatively small space is formed between an inner word line and an adjacent word line, so as to improve a process space of a bit line contact plug disposed on the outer side, and prevent the word line and the bit line from being directly connected. With this arrangement, the semiconductor memory device of the present disclosure can achieve more optimized device performance.

To achieve the above objective, one embodiment of the present disclosure provides a semiconductor memory device including a substrate, an active structure, a shallow trench isolation, and a plurality of word lines. The active structure is disposed in the substrate, and further includes a first active region and a second active region. The first active region includes a plurality of active region cells parallel to each other and extending along a first direction, and the second active region is disposed outside the first active region, surrounding all of the active region cells. The shallow trench isolation is disposed in the substrate surrounding the active structure. The word lines are arranged in the substrate, extend in a second direction and are staggered with the active area units, wherein the second direction is intersected with and not perpendicular to the first direction. The word lines comprise a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged along a third direction perpendicular to the second direction at a first interval, the second word lines are arranged along the third direction at a second interval, and the second interval is larger than the first interval.

To achieve the above objective, one embodiment of the present disclosure provides a semiconductor memory device including a substrate, an active structure, a shallow trench isolation, and a plurality of word lines. The active structure is disposed in the substrate, and further includes a first active region and a second active region. The first active region includes a plurality of active region cells parallel to each other and extending along a first direction, and the second active region is disposed outside the first active region, surrounding all of the active region cells. The shallow trench isolation is disposed in the substrate surrounding the active structure. The word lines are arranged in the substrate, extend in a second direction and are staggered with the active area units, wherein the second direction is intersected with and not perpendicular to the first direction. The word lines comprise a plurality of first word lines and at least one second word line, one end of part of the active region units is directly contacted with the second word lines, and the other end of the part of the active region units is directly contacted with the second active region.

Drawings

FIGS. 1-7 are schematic diagrams illustrating a process for fabricating a semiconductor memory device according to a preferred embodiment of the present disclosure; wherein

FIG. 1 is a top view of a semiconductor memory device after forming an active structure and word lines in accordance with the present disclosure;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a top view of a semiconductor memory device after forming contact openings in accordance with the present disclosure;

FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 3;

FIG. 5 is a top view of a semiconductor memory device after forming bit lines and contacts in accordance with the present disclosure;

FIG. 6 is a schematic cross-sectional view taken along line A-A' of FIG. 5; and

fig. 7 is a schematic cross-sectional view taken along line B-B' of fig. 5.

Wherein the reference numerals are as follows:

300 semiconductor memory device

110 substrate

112 shallow trench

120 shallow trench isolation

130 active structure

131 first active region

131a, 131b, 131c, 131d active area cells

133 second active region

133a first side edge

133b second side edge

140 buried gate structure

140a first word line

140b second word line

141 trench

142 dielectric layer

143 gate dielectric layer

144 gate electrode

145 cap layer

150 insulating layer

155 contact opening

155a first contact opening

155b second contact opening

160 bit line

161 semiconductor layer

162 barrier layer

163 conductive layer

164 cover layer

170 contact

170a first contact

170b second contact

180. 190 third contact

D1 first direction

D2 second direction

Third direction D3

L1, L2, L3, L4 Length

O1, O2 aperture, width

P1, P2 and P3 spaces

Width of T1

Width W

Detailed Description

To further clarify the disclosure and its intended advantages, those skilled in the art will recognize that there is no intent to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims. Those of skill in the art to which the present disclosure pertains will be readily able to devise alternative embodiments, arrangements and mixtures of features which, without departing from the spirit of the present disclosure, are capable of being substituted and reconfigured for additional embodiments.

Referring to fig. 1 to 7, a process of manufacturing a semiconductor memory device 300 according to a preferred embodiment of the present disclosure is illustrated, wherein fig. 1, 3 and 5 are schematic top views of the semiconductor memory device 300 at different stages of formation, and fig. 2, 4, 6 and 7 are schematic cross-sectional views of the semiconductor memory device 300 at different stages of formation. The semiconductor memory device 300 includes a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe) or a silicon-on-insulator (SOI) substrate, and at least one Shallow Trench Isolation (STI) 120 is disposed in the substrate 110 to define an active structure (active structure)130 on the substrate 110, i.e., the STI 120 is disposed around the active structure 130. The active structure 130 further includes a first active region 131 disposed in one region (e.g., a storage region with a relatively high device integration), and a second active region 133 disposed in another region (e.g., a peripheral region with a relatively low device integration). Preferably, the another region (e.g., the peripheral region) is disposed outside the region (e.g., the storage region), such that the second active region 133 can be disposed around the outside of the first active region 131, as shown in fig. 1, but not limited thereto.

Referring to fig. 1 and fig. 2, the detailed portion of the first active region 131 includes a plurality of active region cells 131a, 131b, 131c, 131D extending in parallel and spaced apart from each other along the first direction D1 and alternately arranged, wherein the first direction D1 is, for example, intersecting and not perpendicular to the y direction (e.g., the second direction D2) or the x direction (e.g., the third direction D3). In an embodiment, the active area units 131a have the same length L1 and the same pitch P1 in the first direction D1, and are sequentially arranged in a plurality of rows along the first direction D1, so that a specific arrangement can be shown as a whole, such as the array arrangement (array arrangement) shown in fig. 1, but not limited thereto. The active region units 131b, 131c, 131D respectively have lengths different from the length L1 and different from each other in the first direction D1, such as the lengths L2, L3, and L4 shown in fig. 1, wherein the length L4 may be smaller than the lengths L1, L2, and L3, the length L3 may be larger than the length L2, and the length L2 may be larger than the length L1(L3 > L2 > L1 > L4), but not limited thereto. In the first direction D1, the active area cells 131a, 131b, 131c, and 131D are sequentially arranged in a plurality of rows along the first direction D1 at the same pitch P1, and the active area cells 131b, 131c, and 131D are also sequentially arranged at the same pitch P1 outside all the active area cells 131a, for example, at the left side, the lower side, the right side, and the upper side (not shown) of all the active area cells 131a, so that a specific arrangement can be presented as a whole, such as an array arrangement (array arrangement) shown in fig. 1, but the utility model is not limited thereto.

In an embodiment, the first active region 131 may be formed by, but not limited to, a patterning process described below. For example, a mask layer (not shown) is formed on the substrate 110, the mask layer includes a plurality of patterns for defining a plurality of active region units 131a, 131b, 131c, 131d of the first active region 131 and exposes a portion of the substrate 110, an etching process is performed using the mask layer to remove the portion of the substrate 110 and form at least one shallow trench (shallow trench)112, and then an insulating material (not shown) such as silicon oxide, silicon nitride or silicon oxynitride is filled into the shallow trench 112, so as to form the shallow trench isolation 120 with a top surface aligned with the surface of the substrate 110 and define the first active region 131, as shown in fig. 1 and 2. In an embodiment, the first active region 131 may be formed by a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but is not limited thereto.

Referring to fig. 1 again, the second active region 133 is disposed around the first active region 131. In the present embodiment, the second active region 133 includes at least two first sides 133a extending along the second direction D2 and at least one second side 133b extending along the third direction D3, wherein the first sides 133a are opposite to each other and are adjacent to and sequentially disposed with the second sides 133b, so that the second active region 133 can be in a rectangular frame shape (not shown) as a whole and directly contact a portion of the active region units 131b, 131c, 131D. That is, when the second active region 133 is disposed, a portion of the active region units 131b, 131c, and 131d may be further connected to the first side 133a and/or the second side 133b of the second active region 133, and another portion of the active region units 131a may be disposed apart from the first side 133a and/or the second side 133b of the second active region 133, as shown in fig. 1. In addition, the first side 133a and the second side 133b may have the same width T1, and the width T1 thereof may preferably be greater than the width W of each active area unit 131a, 131b, 131c, 131d, but is not limited thereto. With this arrangement, the second active region 133 can more uniformly bear the stress influence from the active region units 131b, 131c, 131d and the shallow trench isolation 120, so as to obtain a more stable structure. However, in other embodiments (not shown), the second active region 133 may not contact any of the active region units 131a, 131b, 131c, and 131d at all, or the widths T1 of the first side 133a and the second side 133b may be equal to or smaller than the width W of the active region unit 131a according to actual product requirements. It should be understood by those skilled in the art that the specific number of the first sides or the second sides can be adjusted according to actual requirements, or other sides can be further included, so that the second active region can take other shapes as a whole, not limited to the rectangular frame shape.

It should be noted that, in the present embodiment, the second active region 133 may be formed by the patterning process of the substrate 110, and may be optionally performed together with the patterning process of the first active region 131. That is, in the present embodiment, the patterns of the first active region 131 and the second active region 133 may be simultaneously defined or separately defined by using the same or different mask layers, and then the substrate 110 is etched and filled with the insulating material. Herein, the first active region 131 and the second active region 133 may include the same material (i.e., the material of the substrate 110), and the first side 133a and the second side 133b of the second active region 133 and the active region units 131b, 131c, 131d connected thereto may be integrally formed, as shown in fig. 1. In this case, the active region units 131b, 131c, and 131d connected to the first side 133a and the second side 133b of the second active region 133 in the first active region 131 can be regarded as extensions extending inward from the first side 133a and the second side 133b of the second active region 133, so that the second active region 133 can have a relatively stable and strengthened structure to protect the first active region 131, especially the active region unit 131a, disposed inside the second active region 133 and prevent the active region unit 131a from structural collapse or damage. However, it should be understood by those skilled in the art that the formation of the second active region is not limited to the above-mentioned fabrication process, and may be formed by other fabrication processes, for example, separately from the fabrication process of the first active region. For example, in another embodiment, the manufacturing process of the second active region may be performed before the manufacturing process of the first active region, the second active region is formed by a patterning manufacturing process of the substrate, and the first active region is formed by an epitaxial growth process (not shown), where top surfaces of the second active region and the first active region may not be coplanar (not shown); alternatively, in another embodiment, the manufacturing process of the second active region may be performed after the manufacturing process of the first active region, the first active region is formed by a patterning process of the substrate, and then the second active region is formed by a deposition process (for example, a material different from the substrate, such as polysilicon, a dielectric material, etc.), where the second active region and the first active region may comprise different materials.

Next, as shown in fig. 1 and fig. 2, a plurality of gate structures, preferably buried gate structures 140, are formed in the substrate 110. In the present embodiment, a plurality of trenches 141 are formed in the substrate 110, and the trenches 141 are parallel to each other and spaced apart from each other and extend along the second direction D2. Then, a dielectric layer 142 covering the entire surface of each trench 141, a gate dielectric layer 143 covering the surface of the lower half of each trench 141, a gate 144 filling the lower half of each trench 141, and a cap layer 145 filling the upper half of each trench 141 are sequentially formed. Thus, the surface of the cap layer 145 may be cut flush with the top surface of the substrate 110, as shown in fig. 2, so that the buried gate structure 140 in the substrate 110 may be used as a buried Word Line (WL) of the semiconductor memory device 300, wherein each WL is parallel to the first side of the second active region and crosses the active region cells 131a, 131b, 131c, 131d to receive or transmit a voltage signal of each memory cell (not shown). It should be noted that the word lines (i.e., the buried gate structures 140) are sequentially arranged along the third direction D3, and include a plurality of first word lines 140a and a plurality of second word lines 140b, wherein the first word lines 140a are sequentially arranged along the third direction D3 at a first pitch P2, the second word lines 140b are sequentially arranged at a second pitch P3 along the third direction D3 at two opposite outer sides of all the first word lines 140a, and the second pitch P3 is greater than the first pitch P2, as shown in fig. 1 and fig. 2. It is noted that the first word line 140a passes through the middle of the active area cells 131a and 131d, and the second word line 140b passes through the middle of the active area cell 131c and directly contacts the end of the active area cell 131 b. In other words, a portion of the active area unit 131b contacts the second word line 140b at one end and contacts the first side 133a of the second active area 133 at the other end, as shown in fig. 1.

Next, as shown in fig. 3 (the insulating layer 150 is omitted) and fig. 4, an insulating layer 150 is formed on the top surface of the substrate 110, fully covering the substrate 110 and contacting the buried gate structure 140 and the shallow trench isolation 120 in the substrate 110, wherein the insulating layer 150 includes, but is not limited to, an oxide-nitride-oxide (ONO) structure. Then, an etching process is performed to remove a portion of the insulating layer 150 and a portion of the substrate 110 thereunder, so as to form a plurality of contact openings 155 in the substrate 110. Each contact opening 155 is formed between two adjacent word lines (i.e., buried gate structures 140) and exposes a portion of the substrate 110. In detail, the contact opening 155 further includes at least one first contact opening 155a and at least one second contact opening 155b, wherein each first contact opening 155a is disposed on the active area unit 131a and between two adjacent first word lines 140a, and each second contact opening 155b is also disposed on the active area unit 131a but between the adjacent first word lines 140a and second word lines 140b, in other words, neither the first contact opening 155a nor the second contact opening 155b is disposed on the active area units 131b, 131c, 131d that can be further connected to the second active area 133, as shown in fig. 3. In addition, the first contact opening 155a has an aperture O1 in the first direction D1, and the second contact opening 155b has an aperture O2 in the first direction D1. It is noted that, since the pitch P3 of the second word line 140b is larger, the aperture O2 of the second contact opening 155b may also be larger than the aperture O1 of the first contact opening 155a, as shown in fig. 3. In other words, the pitch P3 of the second word line 140b can make the second contact opening 155b have a relatively large manufacturing space (process window).

Subsequently, at least one Bit Line (BL) 160 is formed on the substrate 110, as shown in fig. 5 to 7, in the present embodiment, a plurality of bit lines 160 are formed, and each bit line 160 extends in the third direction D3 in parallel and spaced apart from each other, and crosses the word line (i.e., the buried gate structure 140) and the active area units 131a, 131b, 131c, and 131D. Each bit line 160 includes, but is not limited to, a semiconductor layer 161 (e.g., comprising polysilicon), a barrier layer 162 (e.g., comprising titanium and/or titanium nitride), a conductive layer 163 (e.g., comprising a low-resistivity metal such as tungsten, aluminum, or copper), and a cap layer 164 (e.g., comprising silicon oxide, silicon nitride, or silicon oxynitride) sequentially stacked on the insulating layer 150. A portion of the bit line 160 overlaps the contact opening 155, so that a portion of the semiconductor layer 162 can fill the contact opening 155 and form a contact 170, thereby forming a Bit Line Contact (BLC). With this arrangement, the bit line contact plug (i.e., contact 170) may be integrally formed with the bit line 160 (as shown in fig. 7) and directly contact a portion of the active cell 131a, so as to electrically connect a transistor element (not shown) in the substrate 110 for receiving or transmitting a voltage signal of each memory cell. It is noted that in view of the clear presentation of bit lines 160, contact 170 is not depicted directly in fig. 5, but its specific location can be referenced to contact opening 155 shown in fig. 3. In detail, the contact 170 further includes at least one first contact 170a and at least one second contact 170b, the first contact 170a is disposed on the active area cell 131a between two adjacent first word lines 140a, and the second contact 170b is also disposed on the active area cell 131a between the adjacent first word lines 140a and second word lines 140 b. That is, none of the contacts 170 (including the first contact 170a and the second contact 170b) are disposed on, and do not contact, active region cells 131b, 131c, 131d that may be further connected to the second active region 133. As such, the first contact 170a may have a relatively smaller width O1 in the first direction D1, and the second contact 170b may also have a relatively larger width O2 due to the larger arrangement pitch P3 of the second word line 140b, as shown in fig. 6 and 7.

Then, as shown in fig. 5, a plurality of third contacts 180 and 190 are formed on the bit lines 160 and the word lines (i.e., the buried gate structures 140), respectively. The third contacts 180 are alternately disposed at two ends (not shown) of the bit line 160 (for example, the left end and the right end of the bit line 160 shown in fig. 5) and electrically connected to the bit line 160. For example, the third contact 180 is disposed at the right end of the odd-numbered bit line 160 and disposed at the left end of the even-numbered bit line 160, as shown in fig. 5, but not limited thereto. On the other hand, the third contact 190 may also have a configuration similar to that of the third contact 180, for example, the third contact 190 may be disposed at the lower end of the odd-numbered word lines (i.e., the buried-gate structures 140) and the upper end (not shown) of the even-numbered word lines (i.e., the buried-gate structures 140), but not limited thereto. With this arrangement, the third contacts 180 and 190 can maintain a sufficient process space and be electrically connected through the bit line 160 and the end of the word line (i.e., the buried gate structure 140).

Thus, the semiconductor memory device 300 according to the preferred embodiment of the present disclosure is completed. The semiconductor memory device 300 has the second active region 133 circumferentially disposed outside the first active region 131, such that a portion of the active region cells 131b, 131c, 131d may be further connected to the first side 133a and/or the second side 133b of the second active region 133, thereby dispersing the stress influence from the shallow trench isolation 120 to obtain a more stable structure. In addition, the semiconductor memory device 300 has word lines (i.e., the buried gate structures 140) arranged at different pitches, a relatively larger pitch P3 is provided between the word line 140b disposed at the outer side and the adjacent word line 140a, and a relatively smaller pitch P2 is provided between the word line 140a disposed at the inner side and the adjacent word line 140 a. Accordingly, the contact 170a disposed between the adjacent word lines 140a has a relatively smaller width O1, and the contact 170b disposed between the adjacent word lines 140a, 140b has a relatively larger width O2, so as to improve the process space of the bit line contact plug (i.e., the contact 170a) disposed outside, and prevent the word lines from being directly connected to the bit lines. With this arrangement, the semiconductor memory device of the present disclosure can achieve more optimized device performance.

However, it should be readily apparent to those skilled in the art that the semiconductor memory device and the fabrication process thereof of the present disclosure may have other aspects or may be achieved by other means without being limited to the foregoing embodiments. For example, in an embodiment, it is also possible to round the corner portions formed by adjusting the etching conditions during the patterning process of the second active region, or to form a plurality of openings on the second active region to further distribute the stress, but not limited thereto.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (13)

1. A semiconductor memory device, comprising:

a substrate;

an active structure disposed in the substrate, the active structure comprising:

a first active region including a plurality of active region cells parallel to each other and extending along a first direction; and

the second active region is arranged outside the first active region and surrounds all the active region units;

shallow Trench Isolation (STI) disposed in the substrate surrounding the active structure; and

the word lines are arranged in the substrate, extend in a second direction and are staggered with the active area units, the second direction is intersected and not perpendicular to the first direction, the word lines comprise a plurality of first word lines and a plurality of second word lines, the first word lines are sequentially arranged along a third direction perpendicular to the second direction at a first interval, the second word lines are arranged along the third direction at a second interval, and the second interval is larger than the first interval.

2. The semiconductor memory device according to claim 1, comprising:

at least one first contact arranged on the active area unit and between two adjacent first word lines; and

and at least one second contact arranged on the active area unit and between the adjacent first word line and the second word line, wherein the width of the second contact in the first direction is larger than that of the first contact in the first direction.

3. The semiconductor memory device according to claim 2, wherein a part of the active region cells are connected to the second active region, and the second contact does not contact the part of the active region cells.

4. The semiconductor memory device according to claim 3, wherein the second word line directly contacts an end of the active region cell of the part of the portion.

5. The semiconductor memory device according to claim 2, further comprising:

and the bit lines are arranged on the substrate and are staggered with the word lines, extend in the third direction and are respectively connected with the first contact and the second contact.

6. The semiconductor memory device according to claim 5, wherein the bit lines are formed integrally with the first contact and the second contact, respectively.

7. The semiconductor memory device according to claim 1, wherein the second active region includes a first side extending along the second direction and a second side extending along the third direction, and the first side is parallel to the word line.

8. The semiconductor memory device according to claim 1, wherein one end of a part of the active region cells contacts the second word line, and the other end contacts the second active region.

9. A semiconductor memory device, comprising:

a substrate;

an active structure disposed in the substrate, the active structure comprising:

a first active region including a plurality of active region cells parallel to each other and extending along a first direction; and

the second active region is arranged outside the first active region and surrounds all the active region units;

shallow Trench Isolation (STI) disposed in the substrate surrounding the active structure; and

the word lines are arranged in the substrate, extend in a second direction and are staggered with the active area units, the second direction is intersected and not perpendicular to the first direction, the word lines comprise a plurality of first word lines and at least one second word line, one end of part of the active area units is directly contacted with the second word line, and the other end of the part of the active area units is directly contacted with the second active area.

10. The semiconductor memory device according to claim 9, wherein the first word lines are arranged in sequence at a first pitch along a third direction perpendicular to the second direction, and the second word lines are arranged at a second pitch along the third direction, wherein the second pitch is larger than the first pitch.

11. The semiconductor memory device according to claim 10, comprising:

at least one first contact arranged on the active area unit and between two adjacent first word lines; and

and at least one second contact arranged on the active area unit and between the adjacent first word line and the second word line, wherein the width of the second contact in the first direction is larger than that of the first contact in the first direction.

12. The semiconductor memory device according to claim 11, wherein the first contact and the second contact do not contact the portion of the active area cell.

13. The semiconductor memory device according to claim 11, further comprising:

and a plurality of bit lines arranged on the substrate and interlaced with the word lines, wherein the bit lines extend in the third direction and are respectively connected with the first contact and the second contact, and the bit lines are integrally formed with the first contact and the second contact.

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