CN211700281U

CN211700281U - Memory device

Info

Publication number: CN211700281U
Application number: CN202020684894.1U
Authority: CN
Inventors: 童宇诚; 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-04-29
Filing date: 2020-04-29
Publication date: 2020-10-16
Anticipated expiration: 2030-04-29

Abstract

The utility model provides a memory, a plurality of node contact structure form on the substrate, and are formed with the air gap in the node contact structure, and the node contact structure passes through the opening electrical property and keeps apart, the opening with air gap intercommunication, insulating layer are filled at least the opening. In the utility model, the opening is communicated with the air gap, and the insulating layer at least fills the opening, so that the air gap can remain part to reduce the parasitic capacitance between the node contact structures and prevent the data retention characteristic of the memory from deteriorating, thereby causing the problem of malfunction; in addition, the requirement for preparing the node contact structure is not required to be improved in order to avoid the occurrence of a cavity in the node contact structure, and the process window for preparing the node contact structure is widened; and even if the insulating layer completely fills the air gap, the insulating layer in the air gap can also play a role of isolating the adjacent node contact structure, and the performance of the memory cannot be adversely affected.

Description

Memory device

Technical Field

The utility model belongs to the technical field of the semiconductor manufacturing technique and specifically relates to a memory.

Background

A Memory, such as a Dynamic Random Access Memory (DRAM), generally has a Memory cell array including a plurality of Memory cells arranged in an array. The memory further comprises a plurality of bit line structures, each bit line structure is electrically connected with a corresponding memory cell, the memory further comprises a capacitor structure, the capacitor structure is used for storing charges representing stored information, and the memory cells can be electrically connected with the capacitor structure through a node contact structure, so that the storage function of each memory cell is realized.

As the device size shrinks, the cross-sectional area of the capacitor structure in the lateral direction (the horizontal direction parallel to the surface of the substrate) decreases. In order to compensate for the reduced area, the length in the longitudinal direction (in the height direction perpendicular to the surface of the substrate) of the capacitance structure is increased, whereby the capacitance structure can be ensured to have a sufficiently large capacitance value. Meanwhile, the difficulty in forming the node contact structure is higher due to the increase of the height of the node contact structure for electrically connecting the capacitor structure, and the distance between the adjacent node contact structures is shortened, so that the parasitic capacitance is increased, the data retention characteristic of the capacitor structure is deteriorated, and the malfunction (malfunction) and other problems occur.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a memory to solve the great problem of parasitic capacitance between the adjacent node contact structure.

In order to achieve the above object, the present invention provides a memory, including:

a substrate;

a plurality of node contact structures extending upwardly from the substrate, the node contact structures having air gaps formed therein;

a plurality of openings between adjacent node contact structures to electrically isolate the node contact structures, and the openings communicate with the air gaps; and the number of the first and second groups,

and the insulating layer at least fills the opening.

Optionally, the insulating layer covers a communication part of the air gap and the opening; alternatively, the insulating layer fills a portion of the air gap.

Optionally, the insulating layer completely fills the air gap.

Optionally, the node contact structure is formed with a first air gap and a second air gap, a bottom of the first air gap is higher than a top of the second air gap, and the opening is in communication with at least the first air gap.

Optionally, the bottom of the opening is lower than the bottom of the first air gap and higher than the top of the second air gap.

Optionally, the method further includes:

an isolation pillar extending in a first direction and located between the substrate and the opening;

a bit line structure extending in a second direction and located between the substrate and the opening; and the number of the first and second groups,

the node contact structure is positioned in a node contact window defined by the isolation column and the bit line structure, and the positions of the isolation column and the opening and the positions of the bit line structure and the opening are offset in the direction vertical to the height direction.

Optionally, the node contact structure is divided into an upper node contact and a lower node contact by taking the height position of the bottom of the opening as a limit, and the maximum width dimension of the upper node contact is greater than the maximum width dimension of the lower node contact in the direction perpendicular to the height direction.

The utility model provides an in the memory, a plurality of node contact structures form on the substrate, just be formed with the air gap in the node contact structure, the node contact structure passes through opening electrical property isolation, the opening with the air gap intercommunication, the insulating layer is filled at least the opening. In the present invention, the opening is communicated with the air gap, and the insulating layer at least fills the opening, so that the air gap can be partially reserved to reduce the parasitic capacitance between the node contact structures, thereby preventing the data retention characteristic of the memory from deteriorating and further causing malfunction; in addition, the process requirement for preparing the node contact structure is not required to be improved in order to avoid the occurrence of voids in the node contact structure, and the process window for preparing the node contact structure is widened; and even if the insulating layer completely fills the air gap, the insulating layer in the air gap can also play a role of isolating the adjacent node contact structures, and the performance of the memory cannot be adversely affected.

Drawings

Fig. 1 is a flowchart of a method for forming a memory according to an embodiment of the present invention;

fig. 2a to fig. 2d are schematic structural diagrams formed by a method for forming a memory according to an embodiment of the present invention;

fig. 2e is a simplified layout of a memory according to an embodiment of the present invention, in which fig. 2a to fig. 2d are schematic cross-sectional views of the structure in fig. 2e along a-a 'and/or b-b';

fig. 3 is a schematic structural diagram of a memory according to a second embodiment of the present invention;

fig. 4 is a schematic structural diagram of a memory according to a third embodiment of the present invention;

fig. 5 is a schematic structural diagram of a memory according to a fourth embodiment of the present invention;

wherein the reference numerals are:

100-a substrate; AA-active region; SIT-trench isolation structure; 300-an isolation column; 500-an isolation layer; 510-a layer of isolating material; 600-node contact window; 800. 810, 820-air gap; 900-opening; 910-an insulating layer;

a WL-word line structure; 200 a-gate oxide layer; 200 b-a gate conductive layer; 200 c-a gate insulating layer;

a BL-bit line structure; 400 a-a first bit line conductive layer; 400 b-a second bit line conductive layer; 400 c-a third bitline conductive layer; 400 d-bit line masking layer; 400 e-isolation side wall;

an SC-node contact structure; 700 a-a first layer of conductive material; 700 b-a second layer of conductive material; 700 c-a conductive contact layer;

x1 — maximum width dimension of upper node contact;

x2-maximum width dimension of lower node contact.

Detailed Description

The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Example one

Fig. 2d is a schematic diagram of a partial structure of the memory in this embodiment, and fig. 2e is a simplified layout of the memory in fig. 2d, wherein fig. 2d is a schematic cross-sectional diagram of the memory in fig. 2e in a direction a-a 'and a direction b-b'.

As shown in fig. 2d and 2e, the memory includes: a substrate 100 and a word line structure WL formed within the substrate 100. Wherein a plurality of active areas AA extending in a third predetermined direction (Z-direction) and trench isolation structures STI are formed in the substrate 100, the trench isolation structures STI separating adjacent active areas AA. The active areas AA are arranged in an array mode, and the active areas AA are mutually independent through the groove isolation structure STI, so that mutual interference among the active areas AA is avoided.

Further, a word line trench is formed in the substrate 100, and the word line trench is used for accommodating the word line structure WL. Specifically, the word line trench extends along a first predetermined direction (X direction) to pass through the respective active area AA and the trench isolation structure STI, and the word line trench has a portion therein located in the trench isolation structure STI and a portion therein located in the active area AA.

In this embodiment, the size of the opening of the word line trench in the trench isolation structure STI is larger than the size of the opening of the word line trench in the active area AA. Further, the bottom position of the word line trench in the trench isolation structure STI is also lower than the bottom position of the word line trench in the active area AA.

As described above, the word line trench passes through the corresponding active area AA and the trench isolation structure STI, and thus the word line structure WL also passes through the active area AA and the trench isolation structure STI accordingly. In this embodiment, the bottom position of the word line structure WL in the trench isolation structure STI is lower than the bottom position of the word line structure WL in the active area AA, and the top position of the word line structure WL is located at the same height position. The word line structure WL is formed in the word line trench, so a channel region buried in the active region AA to have a bent structure may be formed. Thus, the curved channel region can have a relatively large length as compared with the linear channel region, and short channel effects of the transistor can be improved.

With continued reference to fig. 2d and 2e, the word line structure WL includes a gate dielectric layer 200a, a gate conductive layer 200b and a gate insulating layer 200c, wherein the gate dielectric layer 200a covers an inner wall of the word line trench, the gate conductive layer 200b is located on the gate dielectric layer 200a and fills the word line trench with a partial depth, and the gate insulating layer 200c is located on the gate conductive layer 200b and fills the remaining depth of the word line trench.

Further, the active area AA is used to form a memory transistor, for example, a source drain area may also be formed in the active area AA, where the source drain area includes a first source/drain area and a second source/drain area, and the first source/drain area and the second source/drain area are respectively located at two sides of the word line structure WL to form the memory transistor together. It is understood that the bottom portions of the first and second source/drain regions are lower than the top portion of the gate conductive layer 200b, so that there is an overlapping region between the first and second source/drain regions and the gate conductive layer 200 b.

With continued reference to fig. 2d and 2e, a plurality of bit line structures BL are formed on the substrate 100 and extend along a second predetermined direction (Y direction) to pass through the corresponding active areas AA. Referring to fig. 2d, the bit line structure BL includes a first bit line conductive layer 400a, a second bit line conductive layer 400b, and a third bit line conductive layer 400c stacked in sequence. The material of the first bit line conductive layer 400a includes, for example, doped polysilicon, the material of the second bit line conductive layer 400b includes, for example, titanium nitride, and the material of the third bit line conductive layer 200c includes, for example, tungsten.

Further, the bit line structure BL may further include a bit line shielding layer 400d and an isolation sidewall spacer 400 e. The bit line shielding layer 400d is formed above the bit line conductive layers stacked in sequence, and the isolation sidewall 400e at least covers the sidewalls of the bit line conductive layers stacked in sequence and the sidewalls of the bit line shielding layer 400 d.

The bit line structure BL has a portion located on the trench isolation structure STI and a portion located in the active area AA. That is, a portion of the bit line structure BL is located on the substrate 100 and directly above the trench isolation structure STI; another portion of the bit line structures BL extend from above the substrate 100 into the active area AA and are located between adjacent word line structures WL.

With continued reference to fig. 2d and 2e, a plurality of isolation pillars 300 are formed on the substrate 100 and extend along a first predetermined direction, and each of the isolation pillars 300 is located directly above the word line structure WL.

The isolation pillar 300 and the bit line structure BL define a node contact 600, and the node contact 600 is used for accommodating a node contact structure SC. For example, the extension directions of the isolation pillar 300 and the bit line structure BL may be perpendicular to each other (the first predetermined direction and the second predetermined direction are perpendicular to each other), so that the isolation pillar 300 and the bit line structure BL intersect to surround the node contact window 600.

Wherein at least a portion of the bottom of the node contact 600 may further extend into the substrate 100. The defined node contact windows 600 are aligned in both the first predetermined direction and the second predetermined direction, and the node contact windows 600 are arranged in an array to form a node contact window array, for example. At this time, it can be considered that the plurality of node contact windows 600 are arranged in a plurality of rows in both the first predetermined direction and the second predetermined direction.

With continued reference to fig. 2e, the node contact structures SC fill the node contact windows 600 and are correspondingly arranged in a plurality of rows, and the node contact structures SC are electrically connected to the corresponding active areas AA.

Referring next to fig. 2d, the memory further includes an isolation layer 500, where the isolation layer 500 covers a top surface of the bit line structure BL, and in this embodiment, the isolation layer 500 correspondingly covers the bit line shielding layer 400d of the bit line structure BL. As described above, the adjacent bit line structures BL are used to define the node contact 600, and it is considered that the height of the node contact 600 can be further increased by the isolation layer 500 above the bit line structures BL.

With continued reference to fig. 2d, the node contact structures SC fill the node contact windows 600, and in the present embodiment, the node contact structures SC may be correspondingly arranged in an array to form a node contact structure array. Further, the top position of each node contact structure SC is further higher than the top position of the node contact window 600.

With continued reference to fig. 2d, the node contact structure SC includes a conductive contact layer 700c, and the conductive contact layer 700c fills a partial depth of the node contact window 600 to electrically connect with the active area AA. Further, the node contact structure SC further includes an electrically conductive layer filling the node contact window and formed on the conductive contact layer 700c to be electrically connected to the conductive contact layer 700 c. In this embodiment, the electrically conductive material layer includes a first conductive layer 700a and a second conductive layer 700b, the second conductive layer 700b covers the inner wall of the node contact 600, and the first conductive layer 700a fills the node contact 600 and extends upward to be higher than the node contact 600.

Further, adjacent node contact structures SC are separated by an opening 900. In this embodiment, a portion of the opening 900 extends from a position flush with the top of the node contact structure SC into the isolation layer 500 at the top of the bit line structure BL (and a portion of the isolation layer 500 is cut away); and, another portion of the opening 900 is extended into the isolation pillar 300 from a position flush with the top of the node contact structure SC (and a portion of the isolation pillar 300 is cut away), so that the adjacent node contact structures 300b can be separated by the opening 900.

With continued reference to fig. 2d, in the present embodiment, the opening 900 is located on the bit line structure BL and the isolation pillar 300. But in a direction perpendicular to the height direction, the bottom of the opening 900 is lower than the insulating layer 500 and the isolation pillar 300; the position of the opening 900 is not directly opposite to the bit line structure BL, but is shifted to the right by a certain distance relative to the bit line structure BL; accordingly, the opening 900 is not located directly opposite the isolation column 300, but is offset to the right by a certain distance with respect to the isolation column 300. In this way, the planar shape of the opening 900 is not an array but a honeycomb shape, thereby saving area and reducing device size. Of course, in other embodiments, the positions of the opening 900 and the bit line structure BL and the positions of the opening 900 and the isolation pillar 300 in the direction perpendicular to the height direction may also be opposite, and the present invention is not limited thereto.

It should be understood that the bottom of the opening 900 needs to be at least higher than the bottom of the isolation layer 500, so that the isolation layer 500 at least covers the bit line structure BL, thereby preventing the bit line structure BL from being interfered by moisture or signals, such as the outside.

In this embodiment, the node contact structure SC includes an upper node contact portion and a lower node contact portion, the upper node contact portion is located above the height position of the bottom of the opening 900, and the lower node contact portion is located below the height position of the bottom of the opening 900. It can also be understood that the node contact structure SC is divided into an upper node contact and a lower node contact by using the height position of the bottom of the opening 900 as a boundary, the maximum width dimension X1 of the upper node contact is greater than the maximum width dimension X2 of the lower node contact in the direction perpendicular to the height direction, and the width dimension of the upper node contact is greater, so that the difficulty in manufacturing the node contact structure 300b can be reduced.

As shown in fig. 2d, each node contact structure SC has an air gap 800 formed therein, and in the present embodiment, the air gap 800 is located in an opening region of the node contact 600. Also, the air gap 800 is located near the centerline of the node contact 600. That is, the air gap 800 is not located at a region close to the sidewall of the node contact 600, so that the opening 900 can communicate with the air gap 800 under the condition that the opening 900 is shifted to the right by a certain distance with respect to the isolation pillar 300 and the bit line structure BL.

Of course, the air gap 800 in the present invention is not limited to be located near the center line of the node contact 600, but it can also be located in the area close to the sidewall of the node contact 600, so that when the opening 900 and the isolation pillar 300 and the opening 900 and the bit line structure BL are all right opposite to each other, the opening 900 and the air gap 800 can also be ensured to communicate.

It should be understood that the size and shape of the air gaps 800 in the node contact structure SC may be the same or different, and the present invention is not limited thereto; the air gap 800 is not limited to an open region located at the node contact 600, and may be formed in the node contact 600.

In this embodiment, a portion of the bottom of the opening 900 is lower than the bottom of the air gap 800, and a portion of the bottom of the opening 900 is higher than the bottom of the air gap 800. Of course, in other embodiments, the bottom of the opening 900 may be equal to the bottom of the air gap 800, the present invention is not limited thereto,

with continued reference to fig. 2d, an insulating layer 910 is formed in each of the openings 900, and the insulating layer 910 completely fills the openings 900, such that adjacent node contact structures 300b are electrically isolated by the insulating layer 910. In this embodiment, the material of the insulating layer 910 is silicon oxide, and as an alternative embodiment, the material of the insulating layer 910 may also be nitride, carbon-doped nitride (e.g. carbon-doped silicon nitride), carbide (e.g. silicon carbide), or other oxide (e.g. tantalum oxide, titanium oxide), etc., without limitation.

Further, the insulating layer 910 may be a single film layer, or may be a composite structure film formed by combining at least two film layers, for example, a composite structure film layer of an oxide and a nitride, which is not limited by the present invention.

Referring to fig. 2d, in the present embodiment, the insulating layer 910 covers the communication between the air gap 800 and the opening 900, that is, the insulating layer 910 is only filled in the opening 900 and does not enter the air gap 800, which is equivalent to blocking the communication between the air gap 800 and the opening to close the air gap 800. It is understood that after the air gap 800 is sealed, the air gap 800 is located between the insulating layer 910 and the node contact structure SC, and the conductive performance of the node contact structure SC is not affected; meanwhile, an air gap 800 is also formed between the adjacent node contact structures SC, and because the air gap 800 has a lower dielectric constant than the insulating layer 910, the parasitic capacitance between the adjacent node contact structures 300b can be reduced, thereby preventing the data retention characteristic of the memory from being degraded and further preventing the problem of malfunction.

The method for forming the memory device according to the present embodiment will be described in detail with reference to fig. 1 and fig. 2a to 2 e. Fig. 1 is a schematic flow chart of a method for forming a memory according to an embodiment of the present invention, and fig. 2a to 2e are schematic diagrams of structures formed in a manufacturing process of the memory according to an embodiment of the present invention.

As shown in fig. 1, the method for forming the memory includes:

step S100: providing a substrate;

step S200: forming a plurality of node contact structures on the substrate, the node contact structures extending upward from the substrate and having air gaps formed therein;

step S300: forming a plurality of openings between adjacent node contact structures, the openings electrically isolating the node contact structures and communicating with the air gaps; and the number of the first and second groups,

step S400: an insulating layer is formed in the opening, wherein the insulating layer at least fills the opening.

Specifically, referring to fig. 2a, step S100 is performed to provide a substrate 100, wherein a trench isolation structure STI is formed in the substrate 100, and a plurality of active regions AA extending along a third predetermined direction are defined by the trench isolation structure SIT.

Continuing next with fig. 2a, word line structures WL are formed in the substrate 100, the word line structures WL extending in a first predetermined direction and passing through the respective active areas AA and trench isolation structures STI. Further, the lateral width (width dimension in the direction perpendicular to the height) of the word line structure WL located in the active area AA is smaller than the lateral width of the word line structure WL located in the trench isolation structure STI; the bottom of the word line structure WL located in the active area AA is lower than the bottom of the word line structure WL located in the trench isolation structure STI.

The steps of forming the word line structure WL may be as follows:

forming a word line trench (not shown) in the substrate 100 and extending in a first predetermined direction;

forming a gate dielectric layer 200a on the substrate 100, wherein the gate dielectric layer 200a covers the inner wall of the word line trench, and the gate dielectric layer 200a can be used as an insulating layer for isolating the word line from the active area AA;

next, a gate conductive layer 200b is formed in the word line trench, and the gate conductive layer 200b is a conductive film, such as polysilicon or tungsten. The gate conductive layer 200b fills a partial depth of the word line trench; specifically, the height of the gate conductive layer 200b in the word line trench may be reduced by, for example, an etch-back process, so that the top surface of the gate conductive layer 200b is lower than the upper surface of the substrate 100. Thus, the lower portion of the word line trench is filled with the gate conductive layer 200b, and the upper portion of the word line trench is still in an empty state;

forming a gate insulating layer 200c on the gate conductive layer 200b, wherein the gate insulating layer 200c covers the gate conductive layer 200b and completely fills the word line trench, and the gate dielectric layer 200a, the gate conductive layer 200b and the gate insulating layer 200c together form the word line structure WL.

It should be noted that although the drawings of the present embodiment do not show a mask layer on the surface of the substrate 100, it should be appreciated that, during the etching process of the substrate 100 to form the word line trench, a mask layer is usually formed on the surface of the substrate 100 to prevent the etching of the region of the substrate 100 that is not corresponding to the trench.

With continued reference to fig. 2a, the method of forming the memory further comprises: forming a source drain region in the substrate 100, wherein a side edge boundary of the source drain region extends to a side wall of the word line trench close to the top opening, and a bottom boundary of the source drain region is lower than the top position of the gate conductive layer 200b, so that the source drain region and the gate conductive layer 200b have mutually opposite overlapping regions, and in the overlapping regions, the gate conductive layer 200b and the source drain region are mutually separated by using the gate dielectric layer 200 a.

Specifically, the source and drain regions include a first source/drain region S/D1 and a second source/drain region S/D2, and the first source/drain region S/D1 and the second source/drain region S/D2 are respectively located at two sides of the word line structure WL. In this embodiment, the side edge boundary of the first source/drain region S/D1 also extends to the sidewall of the trench isolation structure STI.

It should be noted that, in this embodiment, after the word line trench is formed and the word line structure WL is formed, the source and drain regions are prepared. However, in other embodiments, the source and drain regions may be formed first, and then the word line trench and the word line structure WL are sequentially prepared, which is not limited herein.

Referring to fig. 2a, a plurality of isolation pillars 300 and a plurality of bit line structures BL are formed on the substrate 100, the isolation pillars 300 and the bit line structures BL both extend along a second predetermined direction, a plurality of node contact windows 600 are defined by the isolation pillars 300 and the bit line structures BL on the substrate 100, and the node contact windows 600 are aligned and arranged in a plurality of rows in both a first predetermined direction and a second predetermined direction.

Further, the isolation pillars 300 are located on the word line structures WL, and in the height direction, the isolation pillars 300 are located opposite to the word line structures WL; and the bit line structure BL is vertically intersected with the word line structure WL.

Specifically, when the bit line structure BL is formed, the bit line trench needs to be formed first, and since the bit line trench forms the bit line structure BL in a subsequent step, the bit line trench needs to extend along the second predetermined direction. A part of the bit line trench extends into the active area AA of the substrate 100 and is located between two word line structures WL in the active area AA, and another part is located above the shallow trench isolation structure STI.

A bit line structure BL is then formed in the bit line trench. The bit line structure BL comprises three layers of conductive material layers which are sequentially stacked. Based on this, the formed bit line structure BL includes the first bit line conductive layer 400a, the second bit line conductive layer 400b, and the third bit line conductive layer 400 c. Further, the bit line structure BL further includes a bit line shielding layer 400d, and the bit line shielding layer 400d may be a patterned film layer and is formed above the three conductive material layers. Alternatively, for example, the patterned bit line shielding layer 400d is used to sequentially perform a patterning process on the underlying conductive material layer. In this embodiment, the method for forming the bit line structure BL further includes: isolation spacers 400e are formed on the sidewalls of the first bit line conductive layer 400a, the second bit line conductive layer 400b, the third bit line conductive layer 400c, and the bit line shielding layer 400 d.

As shown in fig. 2a, in the present embodiment, the top surfaces of the isolation pillars 300 are flush, and the top surfaces of the isolation pillars 300 are higher than the top surface of the bit line structure BL, so that an isolation material layer 510 is formed on the bit line structure BL, so that the bit line structure BL is flush with the top surfaces of the isolation pillars 300. The isolation material layer 510, the bit line structure BL and the isolation pillars 300 therebelow form a plurality of isolation lines, and the isolation lines define a node contact array. In a specific embodiment, the isolation material layer 510 and the underlying bit line structure BL form a first isolation line extending along the extending direction of the bit line, for example, along a second predetermined direction, and the isolation pillar 300 forms a second isolation line extending along the first predetermined direction, for example, to intersect with the first isolation line, thereby defining the node contact array.

Referring to fig. 2b, step S200 is performed, and further, after the node contact array is defined, the step of further etching the substrate 100 at the bottom of the node contact 600 is further included, so that at least a portion of the bottom of the node contact 600 further extends into the active region of the substrate 100, so that the subsequently formed node contact structure has a better electrical connection effect with the active region AA.

Continuing with fig. 2b, steps S200 and S300 are performed to form a conductive material layer 700 on the substrate 100, wherein the conductive material layer 700 fills the node contact window 600 and extends to cover the top of the bit line structure BL and the isolation pillar 300. The conductive material layer 700 is used to form a node contact structure, and the material thereof may include a conductive material containing silicon, such as amorphous silicon, polysilicon, and other conductive materials, such as a metal conductive material. For example, a lower portion of the conductive material layer 700 may be a conductive material containing silicon, and an upper portion of the conductive material layer 700 may be a lower resistivity metal conductive material such as tungsten, but not limited thereto. In addition, a metal silicide layer may be optionally formed between the lower portion and the upper portion of the conductive material layer 700 to reduce the contact resistance between the conductive material containing silicon and the metal conductive material, but not limited thereto.

Continuing with fig. 2b, an electrically conductive layer (in this embodiment, the electrically conductive layer includes a first conductive layer 700a and a second conductive layer 700b) is formed, which fills a portion of the node contact and further extends to cover the top of the isolation material layer 510 and the top of the isolation pillar 300.

Optionally, before forming the electrically conductive layer, the method further includes: a conductive contact layer 700c is formed in the node contact window. That is, in the present embodiment, in forming the electrically conductive layer, the electrically conductive layer is formed on the electrically conductive contact layer 700c, and the electrically conductive contact layer 700c and the electrically conductive layer are used to constitute the electrically conductive material layer 700.

The method of forming the conductive contact layer 700c includes: the conductive contact layer 700c is filled in at least a portion of the node contact window 600. In this embodiment, the conductive contact layer 700c is filled in the node contact 600 to electrically connect with the active region exposed in the node contact 600.

With continued reference to fig. 2b, after the conductive contact layer 700c is formed, an electrically conductive layer is formed. In this embodiment, the method for forming the electrically conductive material layer may specifically include the following steps.

A first step of forming a second conductive layer 700b, wherein the second conductive layer 700b covers sidewalls of the node contact window 600 and a top of the conductive contact layer 700 c.

A second step of forming a first conductive layer 700a, the first conductive layer 700a filling the node contact window 600 and also covering the top surface of the isolation material layer 510. In this embodiment, the first conductive layer 700a is a planarization film layer.

It should be understood that, due to the shrinking device size, the aspect ratio of the node contact 600 is increasing, and the requirement on the process is very high to avoid an air gap in the first conductive layer 700a when the first conductive layer 700a is formed, so as to avoid the air gap from affecting the conductive performance of the subsequently formed node contact structure. In this embodiment, the process for forming the first conductive layer 700a is not critical, and an air gap may be formed in the first conductive layer 700 a. In this embodiment, the air gap 800 is formed on the first conductive layer 700a corresponding to the node contact 600, and the air gap 800 is located in the opening region of the node contact 600, but the air gap 800 in this application does not affect the conductive performance of the node contact structure, which will be described below.

Referring to fig. 2b and 2c, the conductive material layer 700 (specifically, the first conductive layer 700a), a portion of the height of the isolation material layer 510 at the top of the bit line structure BL, and a portion of the height of the isolation pillars 300 are etched to form a plurality of openings 900, where the openings 900 correspond to the bit line structure BL and the isolation pillars 300. As shown in fig. 3, the openings 900 separate the remaining conductive material layer 700, and the remaining conductive material layer 700 may form a plurality of node contact structures SC, each node contact structure SC being electrically isolated from each other by the openings 900.

With continued reference to fig. 2c, the remaining spacer material layer 510 forms the spacer layer 500, since the spacer material layer 510 is etched to a partial height. By further etching the isolation material layer 510 and the isolation pillars 300 between adjacent electrically conductive layers, the conductive material between adjacent electrically conductive layers can be effectively removed to ensure the isolation between adjacent electrically conductive layers.

Referring to fig. 2c, in the present embodiment, in a direction perpendicular to the height direction (i.e., the thickness direction of the substrate 100), the positions of the bit line structure BL and the opening 900 are offset (shifted to the right), and the positions of the isolation pillars 300 and the opening 900 are offset (shifted to the right), so that the process window of the opening 900 is widened, and the area saving is facilitated. Meanwhile, due to the offset of the opening 900, when the opening 900 is formed, the air gap 800 is easily etched, so that the opening 900 is communicated with the air gap 800.

Of course, as an alternative embodiment, in the direction perpendicular to the height direction, the positions of the bit line structure BL and the opening 900 may be opposite, and the positions of the isolation pillar 300 and the opening 900 may also be opposite, which is not limited by the present invention.

Referring to fig. 2d, an insulating layer 910 is formed in the opening 900. In this embodiment, the forming method of the insulating layer 910 includes, for example: firstly, depositing an insulating material layer, wherein the insulating material layer fills the opening 900 and covers the top of the node contact structure SC; then, an etch-back process is performed to remove a portion of the insulating material layer covering the top of the node contact structure SC and a portion of the insulating material layer higher than the node contact structure SC.

Referring to fig. 2d, in the present embodiment, the insulating layer 910 only fills the opening 900 and does not enter the air gap 800. In this way, the communication between the air gap 800 and the opening 900 is covered by the insulating layer 910 to close the air gap again. Further, the air gap 800 is located between adjacent node contact structures SC, so that parasitic capacitance between adjacent node contact structures SC can be reduced, and the air gap 800 is not located in the node contact structures SC, so that the conductivity of the node contact structures SC is not adversely affected.

Example two

Fig. 3 is a partial structural diagram of the memory in this embodiment. As shown in fig. 3, the difference from the first embodiment is that, in the present embodiment, the insulating layer 910 fills the opening 900 and completely fills the air gap 800.

Specifically, referring to fig. 3, after the insulating layer 910 fills the opening 900, the insulating layer also extends from the connection between the air gap 800 and the opening 900 to the air gap 800 until the air gap 800 is filled. It is understood that, at this time, the air gap 800 is also filled with an insulating material, and the opening 900 and the air gap 800 jointly isolate the adjacent node contact structures SC. In this embodiment, although the air gap 800 cannot reduce the parasitic capacitance between the adjacent node contact structures SC, it does not adversely affect the conductivity of the node contact structures SC.

With reference to fig. 3, a method for forming the memory of the present embodiment may be the same as the method for forming the memory of the first embodiment. Except that when the insulating layer 910 is formed, the insulating layer 910 can better enter the air gap 800 and completely fill the air gap 800 by controlling the process parameters for preparing the insulating layer 910. For example, the insulating layer 910 is formed by a deposition process with better trench filling capability, or the deposition process for preparing the insulating layer 910 is slowed down, so that the insulating layer 910 can simultaneously fill the opening 900 and the air gap 800.

EXAMPLE III

Fig. 4 is a schematic diagram of a partial structure of the memory in this embodiment. As shown in fig. 4, the difference between the first embodiment and the second embodiment is that, in the present embodiment, the insulating layer 910 fills the opening 900 and a portion of the air gap 800.

Specifically, referring to fig. 4, after the insulating layer 910 fills the opening 900, the insulating layer also extends from the connection between the air gap 800 and the opening 900 to the air gap 800 until the air gap 800 is filled partially. At this time, the air gap 800 is partially filled with the insulating layer, but still remains partially, thereby reducing the parasitic capacitance between adjacent node contact structures SC and not adversely affecting the conductivity of the node contact structures SC.

Specifically, the insulating layer 910 may fill an inner wall of the air gap 800, for example, and a central region of the air gap 800 is not filled; alternatively, the insulating layer 910 may fill the upper portion of the air gap 800 after entering the air gap 800 from the air gap 800, and the lower portion of the air gap 800 is not filled; alternatively, the insulating layer 910 can also separate the air gap 800 into two separate air holes. Of course, the present embodiment is not limited to the above three filling manners, and the insulating layer 910 may fill part of the air gap 800 in any possible manner.

With reference to fig. 4, a method for forming the memory of the present embodiment may be the same as the method for forming the memory of the first embodiment. Except that, when the insulating layer 910 is formed, the insulating layer 910 can enter the air gap 800 and fill a portion of the air gap 800 by controlling the process parameters for preparing the insulating layer 910. For example, the insulating layer 910 is formed by a deposition process with a better trench filling capability, so that the insulating layer 910 can enter the air gap 800, and then the deposition process for preparing the insulating layer 910 is accelerated, so that the insulating layer 910 can be closed quickly, and since the size of the communication between the air gap 800 and the opening 900 is smaller, the communication between the air gap 800 and the opening 900 is sealed by the insulating layer 910 after the air gap 800 is filled partially, so that the air gap 800 is not completely filled. Or, the insulating layer 910 may be formed by a deposition process with better trench filling capability instead, so that the insulating layer 910 can enter the air gap 800, then the deposition process for preparing the insulating layer 910 is slowed down, and after the insulating layer 910 fills a part of the air gap 800, the reaction is stopped immediately, so that the air gap 800 is not completely filled.

Example four

Fig. 5 is a schematic diagram of a partial structure of the memory in this embodiment. As shown in fig. 5, the difference from the first, second and third embodiments is that in this embodiment, a first air gap 810 and a second air gap 820 are formed in the node contact structure SC, the bottom of the first air gap 810 is higher than the top of the second air gap 820, and the opening 900 is at least communicated with the first air gap 810.

Specifically, the first air gap 810 and the second air gap 820 are formed in the first conductive layer 700a, wherein the first air gap 810 is located at the opening of the node contact 600, and the second air gap 820 is located in the node contact 600. That is, the first conductive layer 700a may be formed in two steps or a composite structure film including several layers, and when the aspect ratio of the node contact 600 is large, it is difficult for the first conductive layer 700a to well fill the node contact 600, so that the first air gap 810 and the second air gap 820 distributed in the height direction may be formed in the first conductive layer 700 a.

In this embodiment, the opening 900 is only communicated with the first air gap 810, and a part of the bottom of the opening 900 is lower than the bottom of the first air gap 810 and higher than the top of the second air gap 820, and a part of the bottom of the opening 900 is higher than the bottom of the first air gap 810.

However, it should be understood that the opening 900 in the present invention is not limited to communicating with only the first air gap 810, and the opening 900 may also communicate with both the first air gap 810 and the second air gap 820 under the condition that the bottom of the opening 900 is not lower than the top of the bit line structure BL (ensuring that the bit line structure BL is not disturbed by the outside). The bottoms of the openings 900 may be lower than the bottom of the first air gap 810 and higher than the top of the second air gap 820, or higher than the bottom of the first air gap 810, which is not limited by the present invention.

With reference to fig. 5, a method for forming the memory of the present embodiment may be the same as the method for forming the memory of the first embodiment. The only difference is that when the first conductive layer 700a is formed in the node contact 600, a second air gap 820 is formed in the portion of the first conductive layer 700a located in the node contact 600, a first air gap 810 is formed in the portion located in the opening of the node contact 600, and whether the opening 900 is communicated with the second air gap 820 depends on the height position of the second air gap 820.

In summary, the embodiment of the present invention provides a memory, wherein a plurality of node contact structures are formed on a substrate, and an air gap is formed in each node contact structure, the node contact structures are electrically isolated by an opening, the opening is communicated with the air gap, and an insulating layer at least fills the opening. In the present invention, the opening is communicated with the air gap, and the insulating layer at least fills the opening, so that the air gap can be partially reserved to reduce the parasitic capacitance between the node contact structures, thereby preventing the data retention characteristic of the memory from deteriorating and further causing malfunction; in addition, the requirement for preparing the node contact structure is not required to be improved in order to avoid the occurrence of voids in the node contact structure, and the process window for preparing the node contact structure is widened; and even if the insulating layer completely fills the air gap, the insulating layer in the air gap can also play a role of isolating the adjacent node contact structures, and the performance of the memory cannot be adversely affected.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should also be noted that, although the present invention has been described with reference to the preferred embodiments, the above-mentioned embodiments are not intended to limit the present invention. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still belong to the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.

Claims

1. A memory, comprising:

a substrate;

and the insulating layer at least fills the opening.

2. The memory of claim 1, wherein the insulating layer covers a communication between the air gap and the opening; alternatively, the insulating layer fills a portion of the air gap.

3. The memory of claim 1, wherein the insulating layer completely fills the air gap.

4. The memory of any one of claims 1-3, wherein the node contact structure is formed with a first air gap and a second air gap, a bottom of the first air gap being higher than a top of the second air gap, the opening being in communication with at least the first air gap.

5. The memory of claim 4, wherein a bottom of the opening is lower than a bottom of the first air gap and higher than a top of the second air gap.

6. The memory of claim 1, further comprising:

a bit line structure extending in a second direction and located between the substrate and the opening;

7. The memory of claim 1, wherein the node contact structure is divided into an upper node contact and a lower node contact bounded by a height position of a bottom of the opening, a maximum width dimension of the upper node contact being greater than a maximum width dimension of the lower node contact in a direction perpendicular to the height direction.