CN117525117B

CN117525117B - Transistor device and method for manufacturing the same

Info

Publication number: CN117525117B
Application number: CN202311827363.8A
Authority: CN
Inventors: 纪状
Original assignee: Changxin Jidian Beijing Memory Technologies Co Ltd
Current assignee: Changxin Jidian Beijing Memory Technologies Co Ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-04-19
Anticipated expiration: 2043-12-28
Also published as: CN117525117A

Abstract

The embodiment of the disclosure relates to a transistor device and a preparation method thereof, wherein the transistor device comprises: source and drain regions spaced apart on the well region, the well region surrounding side and bottom surfaces of the source and drain regions, the well region between the side surfaces of the source and drain regions in a direction proximate to each other filling a gap between the source and drain regions and contacting the side surfaces of the source and drain regions in a direction proximate to each other, the top surface of the source region, the top surface of the drain region, and the top surface of the well region between the source and drain regions being level, the source and drain regions being of a different conductivity type than the well region; the barrier layer is positioned between the bottom surface of the source electrode region and the well region and between the bottom surface of the drain electrode region and the well region, and is contacted with at least part of the bottom surface of the source electrode region and at least part of the bottom surface of the drain electrode region; and a gate structure located on the top surface of the well region between the source region and the drain region. The transistor device provided by the embodiment of the disclosure can reduce the leakage current of the transistor.

Description

Transistor device and method for manufacturing the same

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a transistor device and a preparation method thereof.

Background

The memory is an important component of the computer structure and has the function of memory. A transistor is a semiconductor device that can be used to build memory, for example, DRAM (Dynamic Random Access Memory ) or SRAM (Static Random Access Memory, static random access memory). For DRAM, each data bit may be stored by one transistor and one capacitor. In order to increase the storage capacity of a memory, a memory is typically required to be built up from a large number of transistors.

The transistor generally includes a well region and a source/drain electrode in the well region, and a depletion layer is generated between the source/drain electrode and the well region, which can prevent conduction between the source/drain electrode and the well region, but also can cause leakage current of the transistor.

With the increase of the integration level of the memory, the transistor size is further reduced, and in static and working states, the leakage current is increased, so that the off-state performance of the transistor is deteriorated, the static power consumption is increased, and the performance of the transistor is reduced.

Disclosure of Invention

The embodiment of the disclosure provides a transistor device and a preparation method thereof, which can at least reduce leakage current of a transistor.

The embodiment of the disclosure provides a transistor device, comprising: a substrate including a well region; source and drain regions spaced apart on the well region, the well region surrounding side and bottom surfaces of the source and drain regions, the well region between the side surfaces of the source and drain regions in a direction proximate to each other filling a gap between the source and drain regions and contacting the side surfaces of the source and drain regions in a direction proximate to each other, the top surface of the source region, the top surface of the drain region, and the top surface of the well region between the source and drain regions being level, the source region and the well region being different in conductivity type, the drain region and the source region being the same in conductivity type; the barrier layer is positioned between the bottom surface of the source electrode region and the well region and between the bottom surface of the drain electrode region and the well region, and is contacted with at least part of the bottom surface of the source electrode region and at least part of the bottom surface of the drain electrode region; and a gate structure on a top surface of the well region between the source region and the drain region.

In some embodiments, the barrier layer is in contact with all of the bottom surface of the source region and with all of the bottom surface of the drain region, and both sides of the barrier layer at the bottom surface of the source region and the barrier layer at the bottom surface of the drain region in a direction toward each other are in contact with the well region, and in a thickness direction of the substrate, sides of the barrier layer at the bottom surface of the source region near the drain region are coplanar with sides of the source region near the drain region, and sides of the barrier layer at the bottom surface of the drain region near the source region are coplanar with sides of the drain region near the source region.

In some embodiments, the barrier layer is in contact with a portion of the bottom surface of the source region and in contact with a portion of the bottom surface of the drain region, the ratio of the width of the barrier layer at the bottom surface of the source region to the width of the source region being at least 2/3 and the ratio of the width of the barrier layer at the bottom surface of the drain region to the width of the drain region being at least 2/3 in a horizontal direction along the source region toward the drain region; and a barrier layer positioned on the bottom surface of the source region is arranged close to one side of the drain region, a barrier layer positioned on the bottom surface of the drain region is arranged close to one side of the source region, the barrier layer positioned on the bottom surface of the source region and the barrier layer positioned on the bottom surface of the drain region are both in contact with the well region on the side surface in the direction close to each other, the side surface of the barrier layer positioned on the bottom surface of the source region close to the drain region is coplanar with the side surface of the source region close to the drain region along the thickness direction of the substrate, and the side surface of the barrier layer positioned on the bottom surface of the drain region close to the source region is coplanar with the side surface of the drain region close to the source region.

In some embodiments, the barrier layer also covers sides of the source and drain regions in a direction away from each other.

In some embodiments, the doping concentration of the doping element within the well region is gradually increased in a direction along the thickness direction of the substrate and in a direction along the source region or the drain region toward the barrier layer.

In some embodiments, the ratio of the thickness of the barrier layer at the bottom of the source region to the thickness of the source region in the thickness direction of the substrate ranges from (1.5 to 2): 1, the ratio of the thickness of the barrier layer at the bottom of the drain region to the thickness of the drain region ranges from (1.5 to 2): 1, the thickness of the barrier layer at the bottom of the source region is equal to the thickness of the barrier layer at the bottom of the drain region, and the thickness of the source region is equal to the thickness of the drain region.

In some embodiments, in the thickness direction of the substrate, the sum of the thickness of the barrier layer at the bottom surface of the source region and the thickness of the source region is a, the sum of the thickness of the barrier layer at the bottom surface of the drain region and the thickness of the drain region is b, and the thickness of the substrate is h, wherein a is h= (0.5-0.9): 1, b is h= (0.5-0.9): 1, and a=b; and/or in the horizontal direction pointing to the drain region along the source region, the width of the source region is c, the width of the drain region is d, c is a=1 (1.1-1.5), d is b=1 (1.1-1.5), and c=d.

In some embodiments, the material of the well region is different from the material of the source and drain regions, the material of the well region comprises silicon, the material of the source region comprises polysilicon, the material of the drain region comprises polysilicon, and the material of the barrier layer comprises an insulating material.

Correspondingly, the embodiment of the disclosure also provides a preparation method of the transistor device, which comprises the following steps: providing a substrate, wherein the substrate comprises a well region; forming barrier layers which are arranged at intervals on the well region, wherein the top surfaces of the barrier layers are lower than the top surfaces of the well regions positioned between the barrier layers; forming a source layer and a drain layer on the barrier layer which are arranged at intervals, wherein the top surface of the source layer, the top surface of the drain layer and the top surface of a well region between the source layer and the drain layer are flush, the well region surrounds the side surfaces and the bottom surface of the source layer and the drain layer, the well region between the side surfaces of the source layer and the drain layer in the approaching direction fills the gap between the source layer and the drain layer and contacts with the side surfaces of the source layer and the drain layer in the approaching direction, the barrier layer is arranged between the bottom surface of the source layer and the well region and between the bottom surface of the drain layer and the well region, and the barrier layer contacts with at least part of the bottom surface of the source layer and at least part of the bottom surface of the drain layer; forming a gate structure on a top surface of the well region between the source layer and the drain layer; the source and drain layers are doped to convert the source and drain layers into source and drain regions, respectively, the source and well regions being of different conductivity types and the drain and source regions being of the same conductivity type.

In some embodiments, forming a barrier layer on the well region at intervals includes: two grooves which are arranged at intervals are formed in the substrate, the two grooves extend from the top surface of the substrate to the bottom surface of the substrate along the thickness direction of the substrate, and the bottoms and the side walls of the two grooves are exposed out of the well region; depositing a blocking material in the two grooves to form a blocking layer, wherein the blocking layer is in contact with the well regions exposed at the bottoms of the two grooves, and the blocking layer does not fill the two grooves; forming a source layer and a drain layer on the barrier layers disposed at intervals, respectively, comprising: and depositing source-drain materials on the barrier layer which is not filled with the two grooves to form a source electrode layer and a drain electrode layer in the two grooves respectively, wherein the source electrode layer and the drain electrode layer are filled with the residual spaces of the two grooves respectively, and the top surfaces of the source electrode layer, the drain electrode layer and the well region between the source electrode layer and the drain electrode layer are flush.

In some embodiments, the two trenches are identical and the aspect ratio is (1.1-1.5): 1; and/or the ratio of the depth of the two grooves to the thickness of the substrate is (0.5-0.9): 1 in the thickness direction of the substrate.

In some embodiments, the ratio of the thickness of the barrier layer located at the bottom surface of the source layer to the thickness of the source layer in the thickness direction of the substrate ranges from (1.5 to 2): 1, the ratio of the thickness of the barrier layer located at the bottom surface of the drain layer to the thickness of the drain layer ranges from (1.5 to 2): 1, the thickness of the barrier layer located at the bottom surface of the source layer is equal to the thickness of the barrier layer located at the bottom surface of the drain layer, and the thickness of the source layer is equal to the thickness of the drain layer; and/or, in the horizontal direction along the source layer towards the drain layer, the ratio of the width of the barrier layer positioned on the bottom surface of the source layer to the width of the source layer is (2-3): 3, the ratio of the width of the barrier layer positioned on the bottom surface of the drain layer to the width of the drain layer is (2-3): 3, the width of the barrier layer positioned on the bottom surface of the source layer is equal to the width of the barrier layer positioned on the bottom surface of the drain layer, and the width of the source layer is equal to the width of the drain layer.

In some embodiments, the material of the well region is different from the material of the source and drain layers, the material of the well region comprises silicon, the material of the source layer comprises polysilicon, the material of the drain layer comprises polysilicon, and the material of the barrier layer comprises an insulating material.

In some embodiments, each trench comprises a first sub-trench and a second sub-trench which are communicated in the thickness direction of the substrate, the second sub-trench is positioned at the bottom of the first sub-trench, and the ratio of the width of the second sub-trench to the width of the first sub-trench in the horizontal arrangement direction of the two trenches is in the range of (2-3): 3; the side wall surfaces of the two second sub-grooves in the direction close to each other are coplanar with the side wall surfaces of the two first sub-grooves in the direction close to each other respectively, wherein the barrier layer is filled in the second sub-grooves, and the source electrode layer and the drain electrode layer are filled in the two first sub-grooves respectively.

In some embodiments, the source layer includes a first source layer region and a second source layer region stacked in a thickness direction of the substrate, the drain layer includes a first drain layer region and a second drain layer region stacked in the thickness direction of the substrate, the second source layer region and the second drain layer region are in contact with the barrier layer, doping the source layer and the drain layer, including: performing a first doping process on the first source electrode layer region and the first drain electrode layer region, and implanting a first doping element into the first source electrode layer region and the first drain electrode layer region, wherein the conductivity type of the first doping element is different from that of the well region; and performing a second doping process on the second source electrode layer region and the second drain electrode layer region, and implanting a second doping element into the second source electrode layer region and the second drain electrode layer region, wherein the conductivity type of the second doping element is the same as that of the well region.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

in the transistor device provided by the embodiment of the disclosure, the well region located between the sides of the source region and the drain region in the approaching direction to each other fills the gap between the source region and the drain region. That is, the source region and the drain region are all well regions therebetween, so that the well region located between the source region and the drain region can form a channel of the transistor, and the source region and the drain region can form a source and a drain of the transistor, respectively. The conductivity types of the source region and the drain region are the same, and the conductivity types of the source region and the well region are different, that is, the source region and the well region contacted with the source region form a PN junction, and the drain region and the well region contacted with the drain region form a PN junction. The barrier layer is in contact with at least a portion of the bottom surface of the source region and with at least a portion of the bottom surface of the drain region. Therefore, at least part of the bottom surface of the source region contacted with the barrier layer and at least part of the bottom surface of the drain region contacted with the barrier layer are not in direct contact with the well region, so that PN junctions are not formed between the bottom surface of the source region and the well region isolated by the barrier layer, the area of the bottom surface depletion layer of the source region is reduced or the generation of the bottom surface depletion layer of the source region is avoided, PN junctions are not formed between the bottom surface of the drain region isolated by the barrier layer and the well region, the area of the depletion layer of the bottom surface of the drain region is reduced or the generation of the bottom surface depletion layer of the source region is avoided, the problem that serious leakage current is generated in the transistor due to overlarge area generated by the depletion layer is avoided, the power consumption of the transistor is reduced, the speed of the transistor is improved, the service life of the transistor is prolonged, and the performance of the transistor is improved.

It is not difficult to find that the barrier layer is located on the bottom surface of the source region and the bottom surface of the drain region, but is not located on the side surfaces of the source region and the drain region in the direction close to each other, so that on one hand, the generation of a depletion layer on the bottom surfaces of the source region and the drain region can be reduced, and on the other hand, the leakage current can be reduced, and on the other hand, the conduction of a channel between the source region and the drain region can not be prevented, and the normal performance of the transistor is ensured.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic cross-sectional structure of a first transistor device according to an embodiment of the disclosure;

fig. 2 is a schematic cross-sectional structure of a second transistor device according to an embodiment of the disclosure;

fig. 3 is a schematic cross-sectional structure of a third transistor device according to an embodiment of the disclosure;

fig. 4 is a schematic cross-sectional structure of a fourth transistor device according to an embodiment of the present disclosure;

fig. 5 is a schematic cross-sectional structure of a fifth transistor device according to an embodiment of the present disclosure;

fig. 6 is a schematic cross-sectional structure diagram corresponding to a step of forming a well region in a method for manufacturing a transistor device according to an embodiment of the disclosure;

fig. 7 is a schematic cross-sectional structure corresponding to a step of forming a trench in a method for manufacturing a transistor device according to an embodiment of the present disclosure;

fig. 8 is a schematic cross-sectional structure corresponding to a step of forming a trench in another method for manufacturing a transistor device according to an embodiment of the present disclosure;

Fig. 9 is a schematic cross-sectional structure corresponding to a step of forming a trench in a method for manufacturing a transistor device according to another embodiment of the present disclosure;

fig. 10 is a schematic cross-sectional structure corresponding to a step of forming a trench in a method for manufacturing a transistor device according to another embodiment of the present disclosure;

fig. 11 is a schematic cross-sectional structure corresponding to a step of forming an initial barrier layer in a method for manufacturing a transistor device according to an embodiment of the disclosure;

fig. 12 is a schematic cross-sectional structure diagram corresponding to a step of forming a barrier layer in a method for manufacturing a transistor device according to an embodiment of the disclosure;

Fig. 13 is a schematic cross-sectional structure corresponding to a step of forming a barrier layer in another method for manufacturing a transistor device according to an embodiment of the disclosure;

Fig. 14 is a schematic cross-sectional structure corresponding to a step of forming a barrier layer in a method for manufacturing a transistor device according to another embodiment of the disclosure;

fig. 15 is a schematic cross-sectional structure corresponding to a step of forming a barrier layer in a method for manufacturing a transistor device according to another embodiment of the present disclosure;

fig. 16 is a schematic cross-sectional structure corresponding to a step of forming an initial source-drain material in a method for manufacturing a transistor device according to an embodiment of the disclosure;

Fig. 17 is a schematic cross-sectional structure corresponding to a step of forming a source layer and a drain layer in a method for manufacturing a transistor device according to an embodiment of the disclosure;

Fig. 18 is a schematic cross-sectional structure diagram corresponding to a step of forming a source layer and a drain layer in another method for manufacturing a transistor device according to an embodiment of the disclosure;

fig. 19 is a schematic cross-sectional structure diagram corresponding to a step of forming an initial gate dielectric layer and an initial conductive layer in a method for manufacturing a transistor device according to an embodiment of the disclosure;

Fig. 20 is a schematic cross-sectional structure corresponding to a step of forming a gate structure in a method for manufacturing a transistor device according to an embodiment of the disclosure.

Detailed Description

The current leakage current of the transistor is increased, and the static power consumption is increased. One of the reasons for this problem is that a PN junction is formed between the source and drain regions and the well region, and the PN junction causes the generation of a depletion layer. Without a threshold voltage applied to the gate, the depletion layer between the transistors blocks conduction of the source drain region. However, after the channel is conducted, leakage current is generated in the depletion layer, particularly, a depletion layer with a larger area is generated between the bottom surface of the source drain region and the well region, when the area of the depletion layer is too large, more serious leakage current is generated, and the threshold voltage of the transistor is increased and the power consumption is increased due to the too large depletion region.

The embodiment of the disclosure provides a transistor device, wherein a blocking layer is arranged between the bottom surface of a source region and a well region and between the bottom surface of a drain region and the well region, and is contacted with at least part of the bottom surface of the source region and at least part of the bottom surface of the drain region. Therefore, at least part of the bottom surface of the source region contacted with the barrier layer and at least part of the bottom surface of the drain region are not in direct contact with the well region, a PN junction is not formed between the bottom surface of the source region and the well region, which are isolated by the barrier layer, the generation of depletion layer on the bottom surface of the source region is reduced or the generation of depletion layer on the bottom surface of the source region is avoided, a PN junction is not formed between the bottom surface of the drain region isolated by the barrier layer and the well region, the generation of depletion layer on the bottom surface of the drain region is reduced or the generation of depletion layer on the bottom surface of the drain region is avoided, the problem that a transistor generates serious leakage current due to overlarge area generated by the depletion layer is avoided, and the power consumption of the transistor is reduced.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. The technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Fig. 1 is a schematic cross-sectional structure of a first transistor device according to an embodiment of the disclosure; fig. 2 is a schematic cross-sectional structure of a second transistor device according to an embodiment of the disclosure; fig. 3 is a schematic cross-sectional structure of a third transistor device according to an embodiment of the disclosure; fig. 4 is a schematic cross-sectional structure of a fourth transistor device according to an embodiment of the present disclosure; fig. 5 is a schematic cross-sectional structure of a fifth transistor device according to an embodiment of the present disclosure.

Referring to fig. 1 to 5, a transistor device includes: a substrate comprising well region 100. The transistor device further includes: the source region 101 and the drain region 102 are disposed on the well region 100 at intervals, the well region 100 surrounds the sides and the bottom of the source region 101 and the drain region 102, the well region 100 between the sides of the source region 101 and the drain region 102 in the approaching direction to each other fills the gap between the source region 101 and the drain region 102 and contacts the sides of the source region 101 and the drain region 102 in the approaching direction to each other, the top surface of the source region 101, the top surface of the drain region 102, and the top surface of the well region 100 between the source region 101 and the drain region 102 are flush, the conductivity types of the source region 101 and the well region 100 are different, and the conductivity types of the drain region 102 and the source region 101 are the same. The transistor device further includes: a barrier layer 103 is located between the bottom surface of the source region 101 and the well region 100 and between the bottom surface of the drain region 102 and the well region 100, and the barrier layer 103 is in contact with at least part of the bottom surface of the source region 101 and with at least part of the bottom surface of the drain region 102. The transistor device further includes: a gate structure 104 is located on the top surface of the well region 100 between the source region 101 and the drain region 102.

All between the source region 101 and the drain region 102 is the well region 100, and when a voltage is applied to the gate structure 104, the well region 100 between the source region 101 and the drain region 102 can be turned on, so that the source region 101 and the drain region 102 are connected, and carriers of the source region 101 are transferred to the drain region 102. That is, the well region 100 located between the source region 101 and the drain region 102 can form a channel of a transistor, and the source region 101 and the drain can form a source and a drain of the transistor, respectively, thereby constituting the transistor.

The conductivity type of the source region 101 is the same as that of the drain region 102, and the conductivity type of the source region 101 and the drain region 102 is different from that of the well region 100. For example, the doping element types of the source region 101 and the drain region 102 are N-type, and the doping element types of the well region 100 are P-type. A PN junction may be formed at the interface where the source region 101 and the well region 100 are in contact, and a PN junction may be formed at the interface where the drain region 102 and the well region 100 are in contact. The PN junction may cause the generation of a depletion layer.

The barrier layer 103 is in contact with at least a portion of the bottom surface of the source region 101 and the barrier layer 103 is in contact with at least a portion of the bottom surface of the drain region 102 such that the barrier layer 103 isolates the source region 101 from the well region 100 and isolates the drain region 102 from the well region 100. Wherein, each of the bottom surface of the source region 101 and the bottom surface of the drain region 102 may have a barrier layer 103.

Due to the presence of the barrier layer 103, no contact is made between the bottom surface of the source region 101, which is in contact with the barrier layer 103, and the well region 100, and no PN junction is formed there, so that no contact is made between the bottom surface of the drain region 102, which is in contact with the barrier layer 103, and the well region 100, and no PN junction is formed there. In this way, the area of the depletion layer generated on the bottom surfaces of the source region 101 and the drain region 102 can be reduced as much as possible, the problem of serious leakage of the transistor due to the excessively large area of the depletion layer can be improved, leakage current can be reduced, and power consumption of the transistor can be further reduced. In addition, the area of the depletion layer generated at the bottom surfaces of the source region 101 and the drain region 102 is reduced, and the problem of power consumption increase due to an excessive threshold voltage of the transistor can be avoided.

In the embodiment of the disclosure, the barrier layer 103 is not disposed on the side surface of the source region 101 and the drain region 102, which is close to each other, so that the well region 100 between the source region 101 and the drain region 102 is better in contact with the source region 101 and the drain region 102, and the conduction of the transistor is not affected while the leakage current is reduced.

In some implementations, the material of the substrate may be silicon. In some embodiments, the material of the substrate may also be germanium, silicon germanium, or silicon on insulator. The substrate may expose a top surface of the well region 100 between the source region 101 and the drain region 102. In other words, the top surface of the substrate and the top surface of the well region 100 between the source region 101 and the drain region 102 may be the same surface.

The gate structure 104 is located on the top surface of the well region 100 between the source region 101 and the drain region 102, and is capable of conducting the well region between the source region 101 and the drain region 102 when a voltage is applied to the gate structure 104, thereby connecting the source region 101 and the drain region 102.

In some embodiments, the gate structure 104 may include: a gate dielectric layer 111 and a conductive layer 112 stacked in a direction away from the well region 100. The gate dielectric layer 111 covers a portion of the top surface of the well region 100, and the conductive layer 112 covers the top surface of the gate dielectric layer 111. After the conductive layer 112 applies a threshold voltage, the well region 100 between the source region 101 and the drain region 102 is turned on by an electric field coupling effect of the gate dielectric layer 111.

In some embodiments, the material of the conductive layer 112 may be a polysilicon material or a metal-based material, for example, may include a metal, a metal nitride, a metal silicide, or a combination thereof. The metal may be, for example, at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or titanium.

In some embodiments, the material of the gate dielectric layer 111 may be silicon oxide.

In some embodiments, the ratio of the thickness of the source region 101, the thickness of the gate dielectric layer 111 to the thickness of the conductive layer 112 may be 1 (0.1-0.2): (0.6-0.8) in the thickness direction of the substrate, and the thickness of the source region 101 and the thickness of the drain region 102 may be equal.

In some embodiments, the ratio of the width of the source region 101 to the width of the conductive layer 112 along the first direction X may be 1 (1.4-1.6), the width of the source region 101 may be equal to the width of the drain region 102, the width of the conductive layer 112 may be equal to the width of the gate dielectric layer 111, and the first direction X is the horizontal direction of the source region 101 pointing to the drain region 102.

Referring to fig. 1, in some embodiments, the barrier layer 103 may contact all of the bottom surface of the source region 101 and all of the bottom surface of the drain region 102, and both sides of the barrier layer 103 at the bottom surface of the source region 101 and the barrier layer 103 at the bottom surface of the drain region 102 in a direction approaching each other contact the well region 100, and in a thickness direction of the substrate, sides of the barrier layer 103 at the bottom surface of the source region 101 near the drain region 102 are coplanar with sides of the source region 101 near the drain region 102, and sides of the barrier layer 103 at the bottom surface of the drain region 102 near the source region 101 are coplanar with sides of the drain region 102 near the source region 101.

That is, the barrier layer 103 is located on the bottom surfaces of the source region 101 and the drain region 102, and covers the entire bottom surface of the source region 101 and the entire bottom surface of the drain region 102. The side of the barrier layer 103 located at the bottom of the source region 101 near the drain region 102 is coplanar with the side of the source region 101 near the drain region 102, and the side of the barrier layer 103 located at the bottom of the drain region 102 near the source region 101 is coplanar with the side of the drain region 102 near the source region 101. In this way, the generation of the depletion layer on the bottom surface of the source region 101 and the bottom surface of the drain region 102 can be avoided to the maximum extent, and the leakage current can be further reduced.

In a specific example, the front projection of the barrier layer 103 located at the bottom surface of the source region 101 on the top surface of the substrate may coincide with the front projection of the source region 101 on the top surface of the substrate, and the front projection of the barrier layer 103 located at the bottom surface of the drain region 102 on the top surface of the substrate may coincide with the front projection of the drain region 102 on the top surface of the substrate.

Referring to fig. 2 to 4, in some embodiments, the barrier layer 103 may also be in contact with a portion of the bottom surface of the source region 101 and a portion of the bottom surface of the drain region 102, where in the first direction X, the width of the barrier layer 103 at the bottom surface of the source region 101 is w1, the width of the source region 101 is c, the ratio of w1 to c is at least 2/3, the width of the barrier layer 103 at the bottom surface of the drain region 102 is w2, the width of the drain region 102 is d, the ratio of w2 to d is at least 2/3, and the first direction X is the horizontal direction in which the source region 101 points to the drain region 102.

Referring to fig. 2, in some embodiments, the barrier layer 103 located at the bottom of the source region 101 is disposed near the side of the drain region 102, the barrier layer 103 located at the bottom of the drain region 102 is disposed near the side of the source region 101, both sides of the barrier layer 103 located at the bottom of the source region 101 and the barrier layer 103 located at the bottom of the drain region 102 in a direction approaching each other are in contact with the well region 100, and in a thickness direction of the substrate, sides of the barrier layer 103 located at the bottom of the source region 101 near the drain region 102 are coplanar with sides of the source region 101 near the drain region 102, and sides of the barrier layer 103 located at the bottom of the drain region 102 near the source region 101 are coplanar with sides of the drain region 102 near the source region 101.

The ratio of the width of the barrier layer 103 at the bottom of the source region 101 to the width of the source region 101 is at least 2/3, and the ratio of the width of the barrier layer 103 at the bottom of the drain region 102 to the width of the drain region 102 is at least 2/3. In this range, the width of the barrier layer 103 is not too small compared with the width of the source region 101 and the width of the drain region 102, so that the barrier layer 103 covers more of the bottom surfaces of the source region 101 and the drain region 102, thereby effectively reducing the generation of depletion layers on the bottom surfaces of the source region 101 and the drain region 102 and reducing leakage current.

Further, the barrier layer 103 provided on the bottom surface of the source region 101 is provided near the side of the drain region 102, and the barrier layer 103 provided on the bottom surface of the drain region 102 is provided near the side of the source region 101, so that the generation of the depletion layer on the bottom surface of the source region 101 near the side of the drain region 102 and the generation of the depletion layer on the bottom surface of the drain region 102 near the side of the source region 101 can be reduced. In this way, the generation of leakage current can be reduced more effectively.

This is because, for the depletion layers generated at the bottom surfaces of the source region 101 and the drain region 102, the degree of leakage current is not uniform at different positions of the depletion layers. In general, the depletion layer corresponding to the source region 101 and the drain region 102 close to each other on the direction side causes more leakage than the depletion layer corresponding to the source region 101 and the drain region 102 distant from each other on the direction side. Based on this, the barrier layer 103 located at the bottom surface of the source region 101 is located near the side of the drain region 102, the barrier layer 103 located at the bottom surface of the drain region 102 is located near the side of the source region 101, and the side surface of the barrier layer 103 located at the bottom surface of the source region 101 near the drain region 102 is coplanar with the side surface of the source region 101 near the drain region 102, and the side surface of the barrier layer 103 located at the bottom surface of the drain region 102 near the source region 101 is coplanar with the side surface of the drain region 102 near the source region 101, so that leakage current can be reduced more effectively.

Referring to fig. 3, in other embodiments, the barrier layer 103 contacts with a portion of the bottom surface of the source region 101 and contacts with a portion of the bottom surface of the drain region 102, so that a side of the barrier layer 103 located at the bottom surface of the source region 101 away from the drain region 102 may be coplanar with a side of the source region 101 away from the drain region 102, and a side of the barrier layer 103 located at the bottom surface of the drain region 102 away from the source region 101 may be coplanar with a side of the drain region 102 away from the source region 101.

Referring to fig. 4, in further embodiments, the barrier layer 103 contacts with a portion of the bottom surface of the source region 101 and contacts with a portion of the bottom surface of the drain region 102, so that a side of the barrier layer 103 located at the bottom surface of the source region 101 away from the drain region 102 may not be coplanar with both a side of the source region 101 away from the drain region 102 and a side of the source region 101 near the drain region 102, and a side of the barrier layer 103 located at the bottom surface of the drain region 102 away from the source region 101 may not be coplanar with both a side of the drain region 102 away from the source region 101 and a side of the drain region 102 near the source region 101.

Referring to fig. 5, in some embodiments, the barrier layer 103 also covers sides of the source region 101 and the drain region 102 in a direction away from each other. The well region 100 also surrounds the sides of the source region 101 and the drain region 102 in the direction away from each other. Therefore, the barrier layer 103 is provided to cover the sides of the source region 101 and the drain region 102 in the direction away from each other so that the sides of the source region 101 and the drain region 102 in the direction away from each other do not directly contact the well region 100, thereby avoiding the generation of a PN junction, further reducing the generation of a depletion layer between the source region 101 and the well region 100, and further reducing the generation of a depletion layer between the drain region 102 and the well region 100, thereby further reducing the leakage current.

Specifically, the barrier layer 103 located at the bottom surface of the source region 101 may extend to the side of the source region 101 away from the drain region 102, and the barrier layer 103 located at the bottom surface of the drain region 102 may extend to the side of the drain region 102 away from the source region 101.

In some embodiments, the barrier layer 103 may cover the entire side of the source region 101 away from the drain region 102, or may cover only a portion of the side of the source region 101 away from the drain region 102.

In some embodiments, the barrier layer 103 may cover the entire side of the drain region 102 remote from the source region 101, or may cover only a portion of the side of the drain region 102 remote from the source region 101.

In some embodiments, the sides and bottom of barrier layer 103 are in contact with well region 100, whether barrier layer 103 covers a portion of the bottom surfaces of source region 101 and drain region 102, or covers the entire bottom surfaces of source region 101 and drain region 102.

In some embodiments, the doping concentration of the doping element within the well region 100 gradually increases in a direction along the thickness direction of the substrate and along the direction in which the source region 101 or the drain region 102 is directed toward the barrier layer 103. Thus, retrograde well can be formed, suppressing the conductive path in the well region 100, and further reducing the leakage current.

In some embodiments, the doping concentration of the doping element within the well region 100 may also be constant in the direction along the thickness of the substrate and along the direction of the source region 101 or the drain region 102 towards the barrier layer 103.

In some embodiments, the thickness of the barrier layer 103 located at the bottom of the source region 101 is greater than the thickness of the source region 101, and the thickness of the barrier layer 103 located at the bottom of the drain region 102 is greater than the thickness of the drain region 102. The barrier layer 103 is provided with a larger thickness, so that the bottom surface of the source region 101 and the well region 100 can be better isolated, and the bottom surface of the drain region 102 and the well region 100 can be isolated, and the generation of depletion layers on the bottom surfaces of the source region 101 and the drain region 102 can be effectively reduced.

Specifically, referring to fig. 1, in some embodiments, in a thickness direction along the substrate, a thickness of the barrier layer 103 located on the bottom surface of the source region 101 is w3, a thickness of the source region 101 is w4, and a ratio of w3 to w4 ranges from (1.5 to 2): 1; the thickness of the barrier layer 103 at the bottom of the drain region 102 is w5, the thickness of the drain region 102 is w6, the ratio of w5 to w6 is (1.5-2): 1, the thickness of the barrier layer 103 at the bottom of the source region 101 is equal to the thickness of the barrier layer 103 at the bottom of the drain region 102, and the thickness of the source region 101 is equal to the thickness of the drain region 102.

Within the above thickness ratio, it is ensured that the thickness of the barrier layer 103 is not too large compared to the thickness of the source region 101, and that the thickness of the barrier layer 103 is not too large compared to the thickness of the drain region 102, so as to avoid excessive volume of the barrier layer 103 in the well region 100. On the other hand, in the above thickness ratio range, the thickness of the barrier layer 103 is made to be sufficient to isolate the bottom surface of the source region 101 from the well region 100 and the bottom surface of the drain region 102 from the well region 100, reducing or avoiding the generation of a depletion layer in the bottom surfaces of the source region 101 and the drain region 102.

With continued reference to fig. 1, in some embodiments, the sum of the thickness of the barrier layer 103 at the bottom of the source region 101 and the thickness of the source region 101 is a (shown in fig. 1), the sum of the thickness of the barrier layer 103 at the bottom of the drain region 102 and the thickness of the drain region 102 is b (shown in fig. 1), and the thickness of the substrate is h (shown in fig. 1), where a: h= (0.5-0.9): 1, b: h= (0.5-0.9): 1, a = b.

That is, the barrier layer 103 and the source region 101 do not extend through the entire thickness of the substrate, and the barrier layer 103 and the drain region 102 do not extend through the entire thickness of the substrate. The bottom surface of the barrier layer 103, which is located at the bottom surface of the source region 101 and the drain region 102, is still covered by the substrate. And the overall thickness of the barrier layer 103 and the source region 101 at the bottom of the source region 101 is the same as the overall thickness of the barrier layer 103 and the drain region 102 at the bottom of the drain region 102. Specifically, the thickness of the source region 101 may be equal to the thickness of the drain region 102, and the thickness of the barrier layer 103 located at the bottom surface of the source region 101 may be equal to the thickness of the barrier layer 103 located at the bottom surface of the drain region 102.

In the thickness ratio range, the ratio of the overall thickness of the barrier layer 103 to the overall thickness of the source region 101 is larger than that of the entire substrate, and the ratio of the overall thickness of the barrier layer 103 to the overall thickness of the drain region 102 is larger than that of the entire substrate, so that the barrier layer 103 can be ensured to have a sufficiently large thickness to isolate the source region 101 from the well region 100 and isolate the drain region 102 from the well region 100, thereby effectively preventing the generation of a depletion layer. The barrier layer 103 does not penetrate the substrate and can remain intact at the bottom of the substrate so that the substrate can have sufficient strength to support the entire transistor device. In addition, the problem of damaging the performance of the transistor due to the excessive damage of the barrier layer 103 can be avoided.

In some embodiments, in a horizontal direction along the first direction X, i.e., the direction in which the source region 101 points to the drain region 102, the width of the source region 101 is c, the width of the drain region 102 is d, c: a=1 (1.1-1.5), d: b=1 (1.1-1.5), and c=d.

That is, the ratio of the width of the source region 101 to the total thickness of the barrier layer 103 and the source region 101 located at the bottom surface of the source region 101 is 1 (1.1 to 1.5), the ratio of the width of the drain region 102 to the total thickness of the barrier layer 103 and the drain region 102 located at the bottom surface of the drain region 102 is 1 (1.1 to 1.5), and the width of the source region 101 is equal to the width of the drain region 102.

If the barrier layer 103 located on the bottom surface of the source region 101 and the entire source region 101 are regarded as a first stack structure and the barrier layer 103 located on the bottom surface of the drain region 102 and the entire drain region 102 are regarded as a second stack structure, the aspect ratio of the first stack structure is (1.1 to 1.5): 1, and the aspect ratio of the second stack structure is (1.1 to 1.5): 1 within the above thickness ratio range. In the aspect ratio range, in the process of actually forming the first stacking structure and the second stacking structure, the influence of the excessively high aspect ratio on the process precision can be avoided, and the first stacking structure and the second stacking structure which accord with the expected morphology can be formed. Further, it can be ensured that the barrier layer 103 can cover the bottom surface of the source region 101 and the bottom surface of the drain region 102 as much as possible, and the thickness of the barrier layer 103 formed is sufficiently large to block the formation of the depletion layer.

In some embodiments, the material of the well region 100 is different from the material of the source region 101 and the drain region 102, the material of the well region 100 comprises silicon, the material of the source region 101 comprises polysilicon, the material of the drain region 102 comprises polysilicon, and the material of the barrier layer 103 comprises an insulating material.

Polysilicon has the same element as silicon, and therefore, the lattice matching coefficient of polysilicon and silicon is high. The sides of the source region 101 and the drain region 102 in the direction approaching each other are in contact with the well region 100, the source region 101 and the drain region 102 are provided with polysilicon, and if the well region 100 is made of silicon, the lattice matching degree between the source region 101 and the drain region 102 and the well region 100 is high, so that electric leakage caused by material mismatch between the source region 101 and the drain region 102 and the well region 100 can be reduced. The resistance of the polysilicon is not too large or too small, and the source region 101 and the drain region 102 formed of polysilicon can ensure good electrical performance of the transistor.

Providing the barrier layer 103 insulating can reduce transistor leakage current while also avoiding additional electrical interference to the transistor device.

In some embodiments, the barrier layer 103 may be a single layer structure, and the material of the barrier layer 103 may be silicon oxide.

In some embodiments, the barrier layer 103 may also be a multi-layer structure, for example, the barrier layer 103 may include a first sub-layer and a second sub-layer stacked in a direction away from the source region 101 or the drain region 102, the first sub-layer being in contact with the bottom surface of the source region 101 or the drain region 102, and the second sub-layer being in contact with the well region 100, wherein a material of the first sub-layer may be different from a material of the second sub-layer, a material of the first sub-layer may be silicon nitride, and a material of the second sub-layer may be silicon oxide.

That is, the material of the barrier layer 103 in direct contact with the well region 100 is set to silicon oxide. When the substrate material is silicon, it is easier to grow silicon oxide on the surface of silicon, so that the material for providing the barrier layer 103 is silicon oxide, the process difficulty for generating the barrier layer 103 can be reduced, and the formed barrier layer 103 has better morphology.

In the transistor device provided in the above embodiment, the blocking layer 103 is in contact with at least part of the bottom surface of the source region 101 and in contact with at least part of the bottom surface of the drain region 102. In this way, at least part of the bottom surface of the source region 101 and at least part of the bottom surface of the drain region 102, which are in contact with the barrier layer 103, are not in direct contact with the well region 100, so that a PN junction is not formed between the bottom surface of the source region 101 and the well region 100, which are isolated by the barrier layer 103, the generation of a depletion layer on the bottom surface of the source region 101 is reduced, a PN junction is not formed between the bottom surface of the drain region 102 and the well region 100, which are isolated by the barrier layer 103, the generation of a depletion layer on the bottom surface of the drain region 102 is reduced or avoided, so that the problem that a transistor generates serious leakage current due to the overlarge area generated by the depletion layer is avoided, and the power consumption of the transistor is reduced.

Accordingly, the embodiment of the present disclosure further provides a method for manufacturing a transistor device, which may be used to manufacture the transistor device provided in the foregoing embodiment, and the transistor device provided in one embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

The preparation method of the transistor device comprises the following steps.

Fig. 6 is a schematic cross-sectional structure corresponding to a step of forming a well region in a method for manufacturing a transistor device according to an embodiment of the disclosure.

First, referring to fig. 6, a substrate including a well region 100 is provided.

In some implementations, the material of the substrate may be silicon. In some embodiments, the material of the substrate may also be germanium, silicon germanium, or silicon on insulator.

In some embodiments, a doping process may be performed on the substrate to form the well region 100, and the substrate exposes a top surface of the well region 100. For example, a P-type doping element may be implanted into the substrate to form the P-type well region 100. In other examples, an N-type doping element may be implanted into the substrate to form the N-type well region 100. The doping process may be an ion implantation process.

Referring to fig. 7 to 18, barrier layers 103 are formed on the well region 100 at intervals, and the top surfaces of the barrier layers 103 are lower than the top surfaces of the well region 100 between the barrier layers 103. The source layer 31 and the drain layer 32 are formed on the barrier layer 103 disposed at intervals, respectively, the top surface of the source layer 31, the top surface of the drain layer 32, and the top surface of the well region 100 between the source layer 31 and the drain layer 32 are flush, the well region 100 surrounds the side surfaces and bottom surfaces of the source layer 31 and the drain layer 32, the well region 100 between the side surfaces of the source layer 31 and the drain layer 32 in the approaching direction to each other fills the gap between the source layer 31 and the drain layer 32, and contacts the side surfaces of the source layer 31 and the drain layer 32 in the approaching direction to each other, the barrier layer 103 is located between the bottom surface of the source layer 31 and the well region 100, and between the bottom surface of the drain layer 32 and the well region 100, and the barrier layer 103 contacts at least a portion of the bottom surface of the source layer 31 and at least a portion of the bottom surface of the drain layer 32.

The barrier layer 103 can isolate the bottom surface of the source region and the well region 100, which are formed later, and isolate the bottom surface of the drain region and the well region 100, which are formed later, and thus can reduce the area of the depletion layer generated on the bottom surface of the source region and the bottom surface of the drain region, and reduce the leakage current.

In some embodiments, the material of the well region 100 is different from the material of the source layer 31 and the drain layer 32, the material of the well region 100 includes silicon, the material of the source layer 31 includes polysilicon, the material of the drain layer 32 includes polysilicon, and the material of the barrier layer 103 includes an insulating material.

In some embodiments, the barrier layer 103 is formed on the well region 100 at intervals, including the following steps.

Fig. 7 is a schematic cross-sectional structure corresponding to a step of forming a trench in a method for manufacturing a transistor device according to an embodiment of the present disclosure; fig. 8 is a schematic cross-sectional structure corresponding to a step of forming a trench in another method for manufacturing a transistor device according to an embodiment of the present disclosure; fig. 9 is a schematic cross-sectional structure corresponding to a step of forming a trench in a method for manufacturing a transistor device according to another embodiment of the present disclosure; fig. 10 is a schematic cross-sectional structure corresponding to a step of forming a trench in a method for manufacturing a transistor device according to another embodiment of the disclosure.

First, referring to fig. 7 to 10, two trenches 10 are formed in a substrate in a spaced arrangement, both trenches 10 extending from a top surface of the substrate to a bottom surface of the substrate in a thickness direction of the substrate, and bottoms and sidewalls of both trenches 10 are exposed to a well region 100.

In some embodiments, the trench 10 may be formed using a dry etching process. Specifically, a patterning process may be first used to define a mask pattern to be etched on the top surface of the substrate, where the mask pattern is used to define an opening pattern of the trench 10, and then the substrate is etched based on the mask pattern to form the trench 10.

In some embodiments, the two trenches 10 are identical and the aspect ratio is (1.1-1.5): 1. That is, the shapes of the two grooves 10 may be identical. The aspect ratio referred to herein is the ratio of the maximum depth H of the trench 10 (shown in fig. 7-10) to the maximum width D1 of the trench 10 (shown in fig. 7-10). In the above aspect ratio range, the aspect ratio of the trench 10 is not larger, so that the etching process has higher precision, the formed trench 10 has better morphology, and the width dimension of the trench 10 has smaller variation in the direction from the top of the trench 10 to the bottom of the trench 10, i.e. the width dimension of the trench 10 at different depth positions is more uniform. In this way, the morphology of the barrier layer 103 formed in the trench 10 is better, and further, the barrier layer 103 can cover more of the bottom surface of the source region 101 and the bottom surface of the drain region 102 which are formed later.

Referring to FIG. 7, in some embodiments, the maximum depth of the trench 10 is H along the thickness of the substrate, the thickness of the substrate is H, and the ratio of H to H ranges from (0.5 to 0.9): 1. That is, the trench 10 does not penetrate the substrate, and can remain intact at the bottom of the substrate, so that the substrate can have sufficient strength to support the entire transistor device. In addition, the problem of damaging the performance of the transistor due to the trench 10 damaging the substrate too much can be avoided.

In some embodiments, in the horizontal arrangement direction along the two trenches 10, i.e., in the first direction X, the maximum width of the trench 10 is D1, the width of the well region 100 between the two trenches 10 is D2, and the ratio of D1 to D2 is 1 (1.4-1.6). Within this range, the width dimensions of the source region 101, the drain region 102, and the well region 100 between the source region 101 and the drain region 102, which are formed later, are matched, ensuring excellent performance of the transistor formed.

Referring to fig. 7, in some embodiments, the cross-sectional shape of the trench 10 may be rectangular or nearly rectangular in the direction of arrangement of the two trenches 10, i.e., the width dimension of the trench 10 is constant or nearly constant in the direction of the top of the trench 10 toward the bottom of the trench 10. In this way, the barrier layer 103 subsequently formed in the trench 10 may entirely cover the bottom surface of the source region 101 or the drain region 102.

Referring to fig. 8 to 10, in some embodiments, each trench 10 may also include a first sub-trench 11 and a second sub-trench 12 that are communicated along the thickness direction of the substrate, the second sub-trench 12 is located at the bottom of the first sub-trench 11, the width of the second sub-trench 12 is L2 along the horizontal alignment direction of the two trenches 10 (i.e. along the first direction X), the width of the first sub-trench 11 is L1, and the ratio of L2 to L1 is (2-3): 3. Subsequently, the barrier layer 103 may be filled in the second sub-trench 12, and the source layer 31 and the drain layer 32 may be filled in the two first sub-trenches 11, respectively, so that the barrier layer 103 may also be in contact with a portion of the bottom surface of the source region 101 and a portion of the bottom surface of the drain region 102.

Referring to fig. 8, in one example, the side wall surfaces of the two second sub-grooves 12 in the approaching direction to each other are coplanar with the side wall surfaces of the two first sub-grooves 11 in the approaching direction to each other, respectively. It is understood that the sidewall surface is the surface on which the sidewall is located.

Referring to fig. 9, in another example, the side wall surfaces of the two second sub-grooves 12 in the direction away from each other are coplanar with the side wall surfaces of the two first sub-grooves 11 in the direction away from each other, respectively.

Referring to fig. 10, in still another example, the side wall surfaces of the two second sub-grooves 12 in the approaching direction and the side wall surfaces of the two first sub-grooves 11 in the approaching direction are not coplanar, nor are the side wall surfaces of the two second sub-grooves 12 in the separating direction and the side wall surfaces of the two first sub-grooves 11 in the separating direction.

Fig. 11 is a schematic cross-sectional structure corresponding to a step of forming an initial barrier layer in a method for manufacturing a transistor device according to an embodiment of the disclosure; fig. 12 is a schematic cross-sectional structure diagram corresponding to a step of forming a barrier layer in a method for manufacturing a transistor device according to an embodiment of the disclosure; fig. 13 is a schematic cross-sectional structure corresponding to a step of forming a barrier layer in another method for manufacturing a transistor device according to an embodiment of the disclosure.

Referring to fig. 12 to 13, after forming the trenches 10, a barrier material is deposited in the two trenches 10 to form a barrier layer 103, the barrier layer 103 is in contact with the well region 100 exposed at the bottom of the two trenches 10, and the barrier layer 103 does not fill the two trenches 10. The subsequently formed source region 101 or drain region 102 may fill the remaining trench 10 and contact the top surface of the barrier layer 103.

In particular, the method of forming the barrier layer 103 may include the following steps.

Referring to fig. 11, first, an initial barrier layer 20 is formed, the initial barrier layer 20 fills up both trenches 10, and the initial barrier layer 20 is higher than the top of the trenches 10, and the initial barrier layer 20 higher than the top of the trenches 10 also covers the top surface of the well region 100.

In some embodiments, the thickness of the initial barrier layer 20 covering the top surface of the well region 100 is e (shown in fig. 11), the thickness of the initial barrier layer 20 in the trench 10 is f (shown in fig. 11), and the ratio of e to f may be (0.1-0.3): 1.

In some embodiments, the initial barrier layer 20 may be formed using a deposition process, for example, an atomic layer deposition process may be used. The material of the initial barrier layer 20 may be silicon oxide.

Referring to fig. 12 and 13, an etch back process is performed on the initial barrier layer 20, removing the initial barrier layer 20 higher than the top of the trench 10, and etching a portion of the thickness of the initial barrier layer 20 located in the trench 10, the remaining initial barrier layer 20 acting as the barrier layer 103. Wherein the thickness of the barrier layer 103 is w3 (shown in fig. 12), the depth of the remaining trench 10 is m (shown in fig. 12), and the ratio of w3 to m may be (1.5-2): 1. Within this range, the thickness of the finally formed barrier layer 103 is made larger, ensuring a good insulating effect.

Fig. 14 is a schematic cross-sectional structure corresponding to a step of forming a barrier layer in a method for manufacturing a transistor device according to another embodiment of the disclosure; fig. 15 is a schematic cross-sectional structure corresponding to a step of forming a barrier layer in a method for manufacturing a transistor device according to another embodiment of the disclosure.

Referring to fig. 8 and 13 to 15, in some embodiments, each trench 10 may also include a first sub-trench 11 and a second sub-trench 12 that are communicated in the thickness direction of the substrate, the second sub-trench 12 is located at the bottom of the first sub-trench 11, and the barrier layer 103 is filled in the second sub-trench 12. In this way, after the source region 101 and the drain region 102 are formed subsequently, the barrier layer 103 covers only a portion of the bottom surface of the source region 101, and the barrier layer 103 covers only a portion of the bottom surface of the drain region 102.

In some embodiments, after forming the barrier layer 103, forming the source layer 31 and the drain layer 32 on the barrier layer 103 disposed at intervals, respectively, includes: source and drain materials are deposited on the barrier layer 103 that does not fill the two trenches 10 to form a source layer 31 and a drain layer 32, respectively, within the two trenches 10, the source layer 31 and the drain layer 32 fill the remaining spaces of the two trenches 10, respectively, and the top surface of the source layer 31, the top surface of the drain layer 32, and the top surface of the well region 100 between the source layer 31 and the drain layer 32 are flush.

In some embodiments, the method of forming the source layer 31 and the drain layer 32 includes the following steps.

Fig. 16 is a schematic cross-sectional structure corresponding to a step of forming an initial source-drain material in a method for manufacturing a transistor device according to an embodiment of the disclosure.

First, referring to fig. 16, an initial source drain material 30 is formed to fill both trenches 10, the initial source drain material 30 being higher than the top of the trench also covering the top surface of the well region 100. In some embodiments, the thickness of the initial source drain material 30 above the top surface of the trench is j (shown in fig. 16), the thickness of the initial source drain material 30 within the trench is k (shown in fig. 16), and the ratio of j to k is (0.5-0.65): 1.

In some embodiments, the initial source drain material 30 may be polysilicon, and the initial source drain material 30 may be formed using an atomic layer deposition process.

Fig. 17 is a schematic cross-sectional structure corresponding to a step of forming a source layer and a drain layer in a method for manufacturing a transistor device according to an embodiment of the disclosure.

Referring to fig. 17, an etch back process is performed on the initial source drain material 30 to remove the initial source drain material 30 above the top of the trench 10, with the remaining initial source drain material 30 constituting the source layer 31 and the drain layer 32.

In some embodiments, the thickness of the barrier layer 103 located on the bottom surface of the source layer 31 along the thickness direction of the substrate is w3 (shown in fig. 17), the thickness of the source layer 31 is w7 (shown in fig. 17), and the ratio of w3 to w7 is in the range of (1.5-2): 1. The thickness of the barrier layer 103 on the bottom surface of the drain layer 32 is w5 (shown in fig. 17), the thickness of the drain layer 32 is w8 (shown in fig. 17), and the ratio of w5 to w8 is in the range of (1.5-2): 1. The thickness of the barrier layer 103 located at the bottom surface of the source layer 31 is equal to the thickness of the barrier layer 103 located at the bottom surface of the drain layer 32, and the thickness of the source layer 31 is equal to the thickness of the drain layer 32.

In some embodiments, the cross-sectional shape of the trench 10 may be rectangular or nearly rectangular in the direction along the first direction X, i.e. in the direction of alignment of the two trenches 10, i.e. the width dimension of the trench 10 is constant or nearly constant in the direction of the top of the trench 10 towards the bottom of the trench 10. In this manner, the barrier layer 103 may be formed to entirely cover the bottom surface of the source layer 31 or the drain layer 32.

Fig. 18 is a schematic cross-sectional structure corresponding to a step of forming a source layer and a drain layer in another method for manufacturing a transistor device according to an embodiment of the disclosure.

Referring to fig. 18, in some embodiments, each trench includes a first sub-trench and a second sub-trench that are communicated in a thickness direction of the substrate, the barrier layer 103 is filled in the second sub-trench, and the source layer 31 and the drain layer 32 are respectively filled in the two first sub-trenches, so that the barrier layer 103 covers only a portion of the bottom surface of the source layer 31, and the barrier layer 103 covers only a portion of the bottom surface of the drain layer 32.

Referring to fig. 18, in some embodiments, the barrier layer 103 covers only a portion of the bottom surface of the source layer 31, and the barrier layer 103 covers only a portion of the bottom surface of the drain layer 32, then in the first direction X, that is, in a horizontal direction along the source layer 31 toward the drain layer 32, the width of the barrier layer 103 located at the bottom surface of the source layer 31 is w1 (shown in fig. 18), the width of the source layer 31 is c1 (shown in fig. 18), the ratio of w1 to c1 may be in the range of (2-3): 3, the width of the barrier layer 103 located at the bottom surface of the drain layer 32 is w2 (shown in fig. 18), the width of the drain layer 32 is d1 (shown in fig. 18), the ratio of w2 to d1 may be in the range of (2-3): 3, the width of the barrier layer 103 located at the bottom surface of the source layer 31 is equal to the width of the barrier layer 103 located at the bottom surface of the drain layer 32, and the width of the source layer 31 is equal to the width of the drain layer 32.

In the above range, the width of the barrier layer 103 is not too small compared with the width of the source region 101 and the width of the drain region 102, so that the barrier layer 103 covers more of the bottom surfaces of the source region 101 and the drain region 102, thereby effectively reducing the generation of depletion layers on the bottom surfaces of the source region 101 and the drain region 102 and reducing leakage current.

Specifically, in one example, the side wall surfaces of the two second sub-grooves 12 in the approaching direction to each other are coplanar with the side wall surfaces of the two first sub-grooves 11 in the approaching direction to each other. Then, the side of the barrier layer 103 located at the bottom surface of the source layer 31, which is close to the drain layer 32, is coplanar with the side of the source layer 31, which is close to the drain layer 32, and the side of the barrier layer 103 located at the bottom surface of the drain layer 32, which is close to the source layer 31, is coplanar with the side of the drain layer 32, which is close to the source layer 31.

In another example, the sidewall surfaces of the two second sub-grooves 12 in the direction away from each other are coplanar with the sidewall surfaces of the two first sub-grooves 11 in the direction away from each other. The side of the barrier layer 103 located on the bottom surface of the source layer 31 away from the drain layer 32 may be coplanar with the side of the source layer 31 away from the drain layer 32, and the side of the barrier layer 103 located on the bottom surface of the drain layer 32 away from the source layer 31 may be coplanar with the side of the drain layer 32 away from the source layer 31.

In yet another example, the side wall surfaces of the two second sub-grooves 12 in the approaching direction to each other are not coplanar with the side wall surfaces of the two first sub-grooves 11 in the approaching direction to each other, and the side wall surfaces of the two second sub-grooves 12 in the separating direction to each other are also not coplanar with the side wall surfaces of the two first sub-grooves 11 in the separating direction to each other. The side of the barrier layer 103 on the bottom surface of the source layer 31 away from the drain layer 32 may not be coplanar with the side of the source layer 31 away from the drain layer 32 and the side of the source layer 31 close to the drain layer 32, and the side of the barrier layer 103 on the bottom surface of the drain layer 32 away from the source layer 31 may not be coplanar with the side of the drain layer 32 away from the source layer 31 and the side of the drain layer 32 close to the source layer 31.

Fig. 19 is a schematic cross-sectional structure diagram corresponding to a step of forming an initial gate dielectric layer and an initial conductive layer in a method for manufacturing a transistor device according to an embodiment of the disclosure; fig. 20 is a schematic cross-sectional structure corresponding to a step of forming a gate structure in a method for manufacturing a transistor device according to an embodiment of the disclosure.

Referring to fig. 20, after forming the source layer 31 and the drain layer 32, a gate structure is formed on the top surface of the well region 100 between the source layer 31 and the drain layer 32.

In some embodiments, the gate structure may include a gate dielectric layer 111 and a conductive layer 112 stacked in a direction away from the well region 100. The gate dielectric layer 111 covers the top surface of the well region 100, and the conductive layer 112 covers the top surface of the gate dielectric layer 111.

In some embodiments, a method of forming a gate structure may include the following steps.

Referring to fig. 19, an initial gate dielectric layer 41 and an initial conductive layer 42 are formed on a substrate sequentially stacked, wherein the initial gate dielectric layer 41 covers the top surface of the source layer 31, the top surface of the drain layer 32, and the top surface of the well region 100 between the source layer 31 and the drain layer 32. In some embodiments, the initial gate dielectric layer 41 may be formed using either a chemical vapor deposition process or an atomic layer deposition process, and the initial conductive layer 42 may be formed using an atomic layer deposition process.

Referring to fig. 19, in some embodiments, in the thickness direction of the substrate, the thickness of the barrier layer 103 located on the bottom surface of the source layer 31 is denoted as w3, the thickness of the source layer 31 is denoted as w7, the thickness of the initial gate dielectric layer 41 is denoted as p, and the thickness of the initial conductive layer 42 is denoted as q, where w3:w7:p:q may be (1.5-2): 1 (0.1-0.2): 0.6-0.8. The gate structure 104 formed in this ratio range has a better control over the transistor.

Referring to fig. 20, an initial gate dielectric layer 41 and a portion of an initial conductive layer 42 on top of a source layer 31 and a top of a drain layer 32 are etched, and the remaining portion of the initial gate dielectric layer 41 and the initial conductive layer 42 are located on top of a well region 100, serve as a gate dielectric layer 111 and a conductive layer 112, and form a gate structure. In some embodiments, in the first direction X, the width of the barrier layer 103 on the bottom surface of the source layer 31 is denoted as w1, the width of the source layer 31 is denoted as c1, and the width of the conductive layer 112 is denoted as z, where w1:c1:z may be 1:1 (1.4-1.6), and the width of the source layer 31 is equal to the width of the drain layer 32.

After the gate structure 104 is formed, the source layer 31 and the drain layer 32 are doped to convert the source layer 31 and the drain layer 32 into a source region 101 and a drain region 102, respectively, the source region 101 and the well region 100 being different in conductivity type, and the drain region 102 and the source region 101 being the same in conductivity type.

Referring to fig. 20, in some embodiments, the source layer 31 includes a first source layer region 311 and a second source layer region 312 stacked in a thickness direction of the substrate, the drain layer 32 includes a first drain layer region 321 and a second drain layer region 322 stacked in the thickness direction of the substrate, the second source layer region 312 and the second drain layer region 322 are in contact with the barrier layer 103, and doping the source layer 31 and the drain layer 32 to form the source region 101 and the drain region 102 may include the following steps.

First, a first doping process is performed on the first source layer region 311 and the first drain layer region 321, and a first doping element is implanted into the first source layer region 311 and the first drain layer region 321, and a conductivity type of the first doping element is different from that of the well region 100. For example, the first doping element may be an N-type element, and the well region 100 may be a P-type well region 100, so that the finally formed transistor is an N-type transistor, the formed source region 101 and the drain region 102 may respectively form a PN junction with the well region 100, and the PN junction may form a depletion region to prevent the source region 101 and the drain region 102 from being turned on.

The first source layer region 311 and the first drain layer region 321 doped with the first doping element may form an LDD (Lightly Doped Drain ) structure, which can share a drain-source voltage for the source region 101 and the drain region 102, so as to effectively reduce the maximum lateral electric field strength in the channel.

In some embodiments, the first doping process may be an ion implantation process.

Thereafter, a second doping process is performed on the second source layer region 312 and the second drain layer region 322, and a second doping element is implanted into the second source layer region 312 and the second drain layer region 322, and a conductivity type of the second doping element is the same as that of the well region 100. In some embodiments, the doping element concentration of the second doping element is less than the doping element concentration of the first doping element.

The second source layer region 312 and the second drain layer region 322 doped with the second doping element may form a blocking structure having a doping element concentration greater than that of the well region 100, forming heavy doping, which can effectively inhibit diffusion of the depletion layers of the source region 101 and the drain region 102 into the channel, prevent punch-through of the source region 101 and the drain region 102, and effectively reduce leakage current.

In some embodiments, the second doping process may be an ion implantation process.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be assessed accordingly to that of the appended claims.

Claims

1. A transistor device, comprising:

A substrate comprising a well region;

A source region and a drain region disposed on the well region at intervals, the well region surrounding side surfaces and a bottom surface of the source region and the drain region, the well region between the side surfaces of the source region and the drain region in a direction close to each other filling a gap between the source region and the drain region and being in contact with the side surfaces of the source region and the drain region in a direction close to each other, a top surface of the source region, a top surface of the drain region, and a top surface of the well region between the source region and the drain region being flush, the source region and the well region being different in conductivity type, the drain region and the source region being the same in conductivity type;

A barrier layer between the bottom surface of the source region and the well region and between the bottom surface of the drain region and the well region, the barrier layer being in contact with at least a portion of the bottom surface of the source region and with at least a portion of the bottom surface of the drain region, the barrier layer not being disposed on sides of the source region and the drain region that are in close proximity to each other;

A gate structure on a top surface of the well region between the source region and the drain region;

Wherein, in the thickness direction of the substrate, the ratio of the thickness of the blocking layer positioned at the bottom surface of the source region to the thickness of the source region is (1.5-2): 1, the ratio of the thickness of the blocking layer positioned at the bottom surface of the drain region to the thickness of the drain region is (1.5-2): 1, the thickness of the blocking layer positioned at the bottom surface of the source region is equal to the thickness of the blocking layer positioned at the bottom surface of the drain region, and the thickness of the source region is equal to the thickness of the drain region;

The side surface, close to the drain region, of the barrier layer located on the bottom surface of the source region is coplanar with the side surface, close to the drain region, of the source region along the thickness direction of the substrate, and the side surface, close to the source region, of the barrier layer located on the bottom surface of the drain region is coplanar with the side surface, close to the source region, of the drain region.

2. The transistor device according to claim 1, wherein the barrier layer is in contact with all of the bottom surface of the source region and with all of the bottom surface of the drain region, and wherein sides of the barrier layer at the bottom surface of the source region and the barrier layer at the bottom surface of the drain region in a direction approaching each other are in contact with the well region.

3. The transistor device of claim 1, wherein the barrier layer is in contact with a portion of the bottom surface of the source region and with a portion of the bottom surface of the drain region, wherein a ratio of a width of the barrier layer at the bottom surface of the source region to a width of the source region in a horizontal direction along the source region toward the drain region is at least 2/3, and wherein a ratio of a width of the barrier layer at the bottom surface of the drain region to a width of the drain region is at least 2/3; and

The barrier layer on the bottom surface of the source region is arranged close to one side of the drain region, the barrier layer on the bottom surface of the drain region is arranged close to one side of the source region, and the barrier layer on the bottom surface of the source region and the barrier layer on the bottom surface of the drain region are both in contact with the well region on the sides in the direction of approaching each other.

4. The transistor device of claim 1, wherein the barrier layer also covers sides of the source region and the drain region in a direction away from each other.

5. The transistor device according to any one of claims 1 to 4, wherein a doping concentration of the doping element within the well region gradually increases in a direction along a thickness direction of the substrate and along a direction in which the source region or the drain region is directed toward the barrier layer.

6. The transistor device according to any one of claims 1 to 4, wherein a sum of a thickness of the barrier layer located at a bottom surface of the source region and a thickness of the source region in a thickness direction of the substrate is a, a sum of a thickness of the barrier layer located at a bottom surface of the drain region and a thickness of the drain region is b, and a thickness of the substrate is h, wherein,

A, h= (0.5-0.9): 1, b, h= (0.5-0.9): 1, a=b; and/or the number of the groups of groups,

In the horizontal direction pointing to the drain region along the source region, the width of the source region is c, the width of the drain region is d, c is a=1 (1.1-1.5), d is b=1 (1.1-1.5), and c=d.

7. The transistor device of any of claims 1-4, wherein a material of the well region is different from a material of the source region and the drain region, wherein a material of the well region comprises silicon, wherein a material of the source region comprises polysilicon, wherein a material of the drain region comprises polysilicon, and wherein a material of the barrier layer comprises an insulating material.

8. A method of manufacturing a transistor device, comprising:

Providing a substrate, wherein the substrate comprises a well region;

forming barrier layers which are arranged at intervals on the well region, wherein the top surfaces of the barrier layers are lower than the top surfaces of the well regions between the barrier layers;

Forming a source layer and a drain layer on the barrier layer which are arranged at intervals, wherein the top surface of the source layer, the top surface of the drain layer and the top surface of the well region between the source layer and the drain layer are flush, the well region surrounds the side surfaces and the bottom surface of the source layer and the drain layer, the well region between the side surfaces of the source layer and the drain layer in the approaching direction fills the gap between the source layer and the drain layer and contacts the side surfaces of the source layer and the drain layer in the approaching direction, the barrier layer is positioned between the bottom surface of the source layer and the well region and between the bottom surface of the drain layer and the well region, and the barrier layer contacts at least part of the bottom surface of the source layer and at least part of the bottom surface of the drain layer;

forming a gate structure on a top surface of the well region between the source layer and the drain layer;

Doping the source layer and the drain layer to convert the source layer and the drain layer into a source region and a drain region, respectively, the source region and the well region being different in conductivity type, the drain region and the source region being the same in conductivity type, the barrier layer not being disposed on sides of the source region and the drain region that are adjacent to each other;

Wherein, in the thickness direction of the substrate, the ratio of the thickness of the barrier layer positioned on the bottom surface of the source layer to the thickness of the source layer is 1.5-2, the ratio of the thickness of the barrier layer positioned on the bottom surface of the drain layer to the thickness of the drain layer is 1.5-2, the thickness of the barrier layer positioned on the bottom surface of the source layer is equal to the thickness of the barrier layer positioned on the bottom surface of the drain layer, and the thickness of the source layer is equal to the thickness of the drain layer;

9. The method of manufacturing a transistor device according to claim 8, wherein forming a barrier layer on the well region at intervals comprises: forming two grooves which are arranged at intervals in the substrate, wherein the two grooves extend from the top surface of the substrate to the bottom surface of the substrate along the thickness direction of the substrate, and the bottoms and the side walls of the two grooves are exposed out of the well region; depositing a barrier material in the two trenches to form the barrier layer, wherein the barrier layer is in contact with the well region exposed at the bottoms of the two trenches, and the barrier layer does not fill the two trenches;

forming a source layer and a drain layer on the barrier layer arranged at intervals respectively, including:

Depositing source-drain materials on the barrier layer which is not filled with the two grooves to form the source electrode layer and the drain electrode layer in the two grooves respectively, wherein the source electrode layer and the drain electrode layer are filled with the residual spaces of the two grooves respectively, and the top surfaces of the source electrode layer, the drain electrode layer and the well region between the source electrode layer and the drain electrode layer are flush.

10. The method for manufacturing a transistor device according to claim 9, wherein the two trenches are identical and have an aspect ratio of (1.1-1.5): 1; and/or the number of the groups of groups,

And the ratio of the depth of the two grooves to the thickness of the substrate along the thickness direction of the substrate is (0.5-0.9): 1.

11. A method for manufacturing a transistor device according to any of the claims 8-10, characterized in that,

The ratio of the width of the barrier layer located at the bottom surface of the source layer to the width of the source layer in the horizontal direction along the source layer toward the drain layer is (2-3): 3, the ratio of the width of the barrier layer located at the bottom surface of the drain layer to the width of the drain layer is (2-3): 3, the width of the barrier layer located at the bottom surface of the source layer is equal to the width of the barrier layer located at the bottom surface of the drain layer, and the width of the source layer is equal to the width of the drain layer.

12. The method of any of claims 8-10, wherein the well region is of a different material than the source and drain layers, the well region is of a material comprising silicon, the source layer is of a material comprising polysilicon, the drain layer is of a material comprising polysilicon, and the barrier layer is of a material comprising an insulating material.

13. The method of manufacturing a transistor device according to claim 10, wherein each of the trenches includes a first sub-trench and a second sub-trench which are communicated in a thickness direction of the substrate, the second sub-trench is located at a bottom of the first sub-trench, and a ratio of a width of the second sub-trench to a width of the first sub-trench in a horizontal arrangement direction of the two trenches ranges from (2 to 3): 3; the side wall surfaces of the two second sub-grooves in the direction close to each other are coplanar with the side wall surfaces of the two first sub-grooves in the direction close to each other respectively, wherein the barrier layer is filled in the second sub-grooves, and the source electrode layer and the drain electrode layer are filled in the two first sub-grooves respectively.

14. The method of manufacturing a transistor device according to any one of claims 8 to 10, wherein the source layer includes a first source layer region and a second source layer region stacked in a thickness direction of the substrate, the drain layer includes a first drain layer region and a second drain layer region stacked in the thickness direction of the substrate, the second source layer region and the second drain layer region are in contact with the barrier layer, and the source layer and the drain layer are doped, comprising:

performing a first doping process on the first source electrode layer region and the first drain electrode layer region, and implanting a first doping element into the first source electrode layer region and the first drain electrode layer region, wherein the conductivity type of the first doping element is different from that of the well region;

And carrying out a second doping process on the second source electrode layer region and the second drain electrode layer region, and implanting a second doping element into the second source electrode layer region and the second drain electrode layer region, wherein the conductivity type of the second doping element is the same as that of the well region.