CN116581161A - SiC UMOSFET with discontinuous P+ shielding layer and preparation method thereof - Google Patents
SiC UMOSFET with discontinuous P+ shielding layer and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 201
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000002344 surface layer Substances 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 27
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 21
- 238000010586 diagram Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 229910018540 Si C Inorganic materials 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 241001391944 Commicarpus scandens Species 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to a SiC UMOSFET with a discontinuous P+ shielding layer and a preparation method thereof, wherein the UMOSFET comprises: a substrate layer; the N-type drift layer is positioned on the upper surface of the substrate layer; the P-doped region is positioned in the surface layer of the N-type drift layer; the N+ doped region is positioned in the surface layer of the P-doped region; the polygonal annular groove is positioned at the periphery of the N+ doped region, and the depth is larger than the sum of the thicknesses of the N+ doped region and the P-doped region; the shielding layers are respectively positioned at each corner of the polygonal annular groove; the P+ column is positioned in the middle of the N+ doped region, penetrates through the N+ doped region and the P-doped region and extends into the N-type drift layer. The invention also provides a preparation method of the SiC UMOSFET with the discontinuous P+ shielding layer. The UMOSFET of the invention improves the current path of the device and reduces the on-resistance while protecting the oxide layer at the bottom of the trench from breakdown.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a SiC UMOSFET with a discontinuous P+ shielding layer and a preparation method thereof.
Background
Based on the excellent performance of the power semiconductor device in the electric energy field, the market scale of the global power semiconductor device is gradually increasing, and the market ratio of the global power semiconductor device is steadily increasing in China. As power semiconductor devices are increasingly moving toward high power, high frequency, and low power consumption, metal-Oxide-semiconductor field effect transistors (MOSFETs) are increasingly taking up a large market share.
MOSFETs of silicon carbide material are classified into lateral and vertical MOSFETs, and conventional vertical MOSFETs without a shielding layer have a small specific on-resistance, so that a large current can be obtained. However, the extremely high electric field formed at the bottom corner of the trench gate of the conventional U-shaped trench Metal-Oxide-Semiconductor Field-Effect Transistor (UMOSFET) without the shielding layer is extremely easy to break down at the corner of the gate Oxide layer due to the two-dimensional effect, and the static characteristics of the device are reduced; at the same time the intrinsic capacitance of the UMOSFET can have adverse effects in high speed switching applications, primarily in terms of gate-drain capacitance, such that the device experiences voltage gain when switching (operating in the saturation region) and exhibits the miller effect.
The continuous P (Positive) type heavily doped (P+) shielding layer is introduced into the traditional UMOSFET structure, so that the oxide layer at the bottom of the groove can be prevented from being broken down to a great extent, but the continuous P+ shielding layer not only increases the on-resistance of the device so that the current path of the device is reduced, but also the gate-source capacitance Cgs is rapidly increased.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a SiC UMOSFET with a discontinuous P+ shielding layer and a preparation method of the SiC UMOSFET with the discontinuous P+ shielding layer. The technical problems to be solved by the invention are realized by the following technical scheme:
a first aspect of an embodiment of the present invention provides a SiC UMOSFET with a discontinuous p+ shield layer, comprising:
a substrate layer;
the N-type drift layer is positioned on the upper surface of the substrate layer;
the P-doped region is positioned in the surface layer of the N-type drift layer;
the N+ doped region is positioned in the surface layer of the P-doped region;
the polygonal annular groove is positioned at the periphery of the N+ doped region, and the depth is larger than the sum of the thicknesses of the N+ doped region and the P-doped region;
the shielding layers are respectively positioned at each corner of the polygonal annular groove and extend to the upper surface of the N+ doped region and the N-type drift layer;
the P+ column is positioned in the middle of the N+ doped region, penetrates through the N+ doped region and the P-doped region and extends into the N-type drift layer;
and the electrode structure is connected with the polygonal annular groove, the N+ doped region and the substrate layer.
In one embodiment of the invention, the electrode structure comprises:
the gate oxide layer covers the surface of the polygonal annular groove;
a gate electrode on the gate oxide layer;
the source electrode is covered on the N+ doped region and the shielding layer on the upper surface of the N+ doped region;
and the drain electrode is positioned on the lower surface of the substrate layer.
In one embodiment of the present invention, the doping type of the shielding layer is p+ type doping.
In one embodiment of the invention, the material of the substrate layer is 4H-SiC doped with N+ type.
In one embodiment of the present invention, the gate electrode is made of PolySi.
The second aspect of the embodiment of the present invention provides a method for preparing a SiC UMOSFET with a discontinuous p+ shielding layer, which is applied to preparing a SiC UMOSFET with a discontinuous p+ shielding layer provided in the first aspect of the embodiment of the present invention, and includes the following steps:
s1: growing an original N-type drift layer on the substrate layer; ion implantation is carried out in the original N-type drift layer to form an original P-doped region and an original N+ doped region; the original P-doped region is positioned in the surface layer of the N-type drift layer, and the original N+ doped region is positioned in the surface layer of the original P-doped region;
s2: ion implantation is carried out in the middle of the original N+ doped region, so that a P+ column is formed; the P+ column penetrates through the original N+ doped region and the original P-doped region and extends into the original N-type drift layer;
s3: performing ion implantation at each corner of the original N+ doped region to form a plurality of ion implantation regions;
the ion implantation region penetrates through the original N+ doped region and the original P-doped region and extends into the original N-type drift layer;
s4: etching the edge of the original N+ doped region into the ion implantation region along the circumferential direction of the original N+ doped region to form a polygonal annular groove, and forming an N-type drift layer, a P-doped region, an N+ doped region and an original shielding layer;
s5: preparing an electrode structure on the product prepared in the step S4, and forming a shielding layer; the shielding layer is distributed at each corner of the polygonal annular groove and extends to the upper surface of the N+ doped region and the N-type drift layer.
In one embodiment of the present invention, step S5 includes:
s501: oxidizing the surface of the polygonal annular groove to form a gate oxide layer and forming the shielding layer;
s502: preparing a gate electrode on the gate oxide layer;
s503: depositing source metal on the surfaces of the N+ doped region and the shielding layer positioned on the upper surface of the N+ doped region to form a source electrode;
s504: and preparing a drain electrode on the lower surface of the substrate layer.
In one embodiment of the present invention, step S3 includes:
s301: forming a protective layer on the upper surface of the original N+ doped region;
s302: forming an opening at a corner on the protective layer;
s303: ion implantation is carried out on the open hole area to form a plurality of ion implantation areas distributed at corner positions of the original N+ doped area; the ion implantation region penetrates through the original N+ doped region and the original P-doped region and extends into the original N-type drift layer;
s304: and removing the protective layer.
In one embodiment of the present invention, the doping type of the shielding layer is p+ type doping.
In one embodiment of the present invention, step S502 includes: and filling PolySi on the gate oxide layer to form the gate electrode.
Compared with the prior art, the invention has the beneficial effects that:
the invention introduces a very small Junction Field-Effect Transistor (JFET) region by forming a discontinuous P+ shielding layer, improves the current path of the device and reduces the on-resistance while protecting the oxide layer at the bottom of the trench from breakdown, and greatly reduces the gate-source capacitance Cgs due to the fact that the shielding layer connected with the source region is greatly reduced compared with a UMOSFET with a continuous shielding layer.
Drawings
FIG. 1 is a schematic diagram of an electrodeless structure of a SiC UMOSFET with a discontinuous P+ shield layer in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of a quarter-configuration of an electrodeless structure of a SiC UMOSFET with a discontinuous P+ shield layer in accordance with an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional structure of a SiC UMOSFET with a discontinuous P+ shield layer in accordance with an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a product prepared in step S1 of a preparation method of a SiC UMOSFET with a discontinuous p+ shield layer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a product prepared in step S3 of a preparation method of a SiC UMOSFET with a discontinuous p+ shield layer according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a product prepared in step S4 of a preparation method of a SiC UMOSFET with a discontinuous p+ shield layer according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a product prepared in step S502 of a preparation method of a SiC UMOSFET with a discontinuous p+ shield layer according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a product prepared in step S504 of a method for preparing a SiC UMOSFET with a discontinuous p+ shield layer according to an embodiment of the present invention;
fig. 9 is a simulated diagram of the turn-on instant of a prior art UMOSFET without a shield layer;
fig. 10 is a simulation diagram of the turn-on instant of a prior art UMOSFET with a continuous shield layer;
fig. 11 is a simulation diagram of the turn-on instant of a SiC UMOSFET with a discontinuous p+ shield layer in accordance with an embodiment of the present invention.
Reference numerals:
1: a substrate layer; 2: an N-type drift layer; 3: a P-doped region; 4: an N+ doped region; 5: a P+ column; 6: a shielding layer; 7: an ion implantation region; 8: a gate oxide layer; 9: a gate electrode; 10: a source electrode; 11: a drain electrode; 201: an original N-type drift layer; 301: an original P-doped region; 401: an original n+ doped region; 601: an original shielding layer.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, 2 and 3, a SiC UMOSFET with a discontinuous p+ shield layer, comprising: the semiconductor device comprises a substrate layer 1, an N-type drift layer 2, a P-doped region 3, an N+ doped region 4, a polygonal annular groove, a plurality of shielding layers 6, P+ columns 5 and an electrode structure.
The N-type drift layer 2 is positioned on the upper surface of the substrate layer 1; the P-doped region 3 is positioned in the surface layer of the N-type drift layer 2; the N+ doped region 4 is positioned in the surface layer of the P-doped region 3; the polygonal annular groove is positioned around the N+ doped region 4, and the depth of the polygonal annular groove is larger than the sum of the thicknesses of the N+ doped region 4 and the P-doped region 3; a plurality of shielding layers 6 are respectively positioned at each corner of the polygonal annular groove and extend to the upper surface of the N+ doped region 4 and the N-type drift layer 2; the P+ column 5 is positioned in the middle of the N+ doped region 4, and the P+ column 5 penetrates through the N+ doped region 4 and the P-doped region 3 and extends into the N-type drift layer 2; the electrode structure is connected with the polygonal annular groove, the N+ doped region 4 and the substrate layer 1.
Wherein the p+ column 5 places the P-doped region 3 and the n+ doped region 4 at the same potential.
Specifically, the electrode structure includes: a gate oxide layer 8, a gate electrode 9, a source electrode 10 and a drain electrode 11.
The gate oxide layer 8 covers the surface of the polygonal annular groove; a gate electrode 9 is located on the gate oxide layer 8; the source electrode 10 covers the N+ doped region 4 and the shielding layer 6 on the upper surface of the N+ doped region 4; the drain electrode 11 is located on the lower surface of the substrate layer 1.
Preferably, the doping type of the shielding layer 6 is P+ type doping, and the doping concentration of the shielding layer 6 at a depth of 2.5 μm from the bottom of the gate oxide layer 8 is 1E17cm -3 The doping concentration of the shielding layer 6 on the upper surface of the N+ doped region 4 is 2E19cm -3 . The material of the substrate layer 1 is doped with 2E19cm -3 4H-SiC doped with n+ type. The doping concentration of the N+ doped region 4 is 2E19cm -3 The doping concentration of the P+ column 5 is 2E19cm -3 . The doping concentration of the P-doped region 3 was 8E16cm -3 The gate electrode 9 material is polysilicon (Polycrystalline silicon, polySi).
Wherein, a basic Si-C diatomic layer composed of an Si atomic layer and a C atomic layer is taken as a basic structural layer, and is periodically piled up in a sequence of ABCBABCB …, and the silicon carbide (SiC) crystal formed by the basic Si-C diatomic layer is called 4H-SiC. Wherein the number 4 represents the number of Si-C diatomic layers in one period, "H" represents the hexagonal crystal form. P-is P-type light doping, N+ is N-type heavy doping.
In this embodiment, the polygonal ring-shaped trench is a quadrangular ring-shaped trench, and the bottom of the quadrangular ring-shaped trench is located in the N-type drift layer 2. The shielding layers 6 are four, the four shielding layers 6 are respectively positioned at four corners of the quadrangular annular groove, and the four shielding layers 6 are arranged at intervals and are symmetrical to each other.
Referring to fig. 9 to 11, id represents a drain electrode current, vd represents a drain electrode voltage, and Vg represents a gate electrode voltage. The power consumption, miller mesa length, cgs, and Cgd (gate drain capacitance) size relationships of the prior art UMOSFET without a shield layer, the prior art UMOSFET with a continuous shield layer, and the discontinuous shield layer UMOSFET of this embodiment can be compared. The current conduction capacities of the three are adjusted to the same level, and the power consumption of the three is 81.42E-6J (UMOSFET with a continuous shielding layer), 29.764E-6J (UMOSFET without a shielding layer) and 36.761E-6J (UMOSFET without a shielding layer), and the power consumption obtained after normalization treatment is 11.523 (UMOSFET with a continuous shielding layer), 11.757 (UMOSFET without a shielding layer) and 17.314 (UMOSFET without a shielding layer).
The structure in this embodiment introduces a very small JFET region by forming a plurality of discontinuous shielding layers 6 on the N-type drift layer 2, and the parallel state of the JFET region and the JFET region can be formed between the middle part of the device without shielding layer and the plurality of shielding layers 6, so that the current path of the device is improved and the on-resistance is reduced while the oxide layer at the bottom of the trench is prevented from being broken down, and the on-resistance of the device is enhanced. Meanwhile, compared with UMOSFETs with continuous shielding layers, the shielding layers connected with the source regions are greatly reduced, and Cgs are greatly optimized. In addition, compared with the traditional UMOSFET without the shielding layer, the miller capacitance Cgd is optimized, the length of the miller platform is obviously reduced, and the miller platform is obviously optimized. Although Cgd is affected, resulting in a slight increase in the miller plateau during switching, the miller plateau gap is very small and the miller effect is hardly affected, compared to a continuous shield UMOSFET.
Example two
Referring to fig. 4 to 8, a method for preparing a SiC UMOSFET with a discontinuous p+ shielding layer includes the following steps:
s1: growing an original N-type drift layer 201 on the substrate layer 1; ion implantation is performed in the original N-type drift layer 201 to form an original P-doped region 301 and an original N+ doped region 401; the original P-doped region 301 is located in the surface layer of the original N-type drift layer 201 and the original n+ doped region 401 is located in the surface layer of the original P-doped region 301. Specifically, the original P-doped region 301 is formed by ion implantation on the surface of the original N-type drift layer 201, and then the original n+ doped region 401 is formed by ion implantation on the surface, as shown in fig. 4.
Preferably, the material of the substrate layer 1 is N+ type doped 4H-SiC with the doping concentration of 2E19cm -3 . Illustratively, an acceptor impurity (boron) is ion-implanted to form the original P-doped region 301, and then a donor impurity (phosphorus) is ion-implanted to form the original n+ doped region 401.
S2: ion implantation is carried out in the middle of the original N+ doped region 401 to form a P+ column 5; the p+ column 5 penetrates the original n+ doped region 401 and the original P-doped region 301 and extends into the original N-type drift layer 201. Wherein the p+ column 5 places the original P-doped region 301 and the original n+ doped region 401 at the same potential.
Specifically, the p+ column 5 is a p+ doped region formed by ion implantation, the p+ column 5 is located at the middle of the original n+ doped region 401, and the bottom is located in the original N-type drift layer 201. Preferably, the doping concentration of the P+ column 5 is 2E19cm -3 。
S3: ion implantation is performed at each corner of the original n+ doped region 401, forming a plurality of ion implantation regions 7; the ion implantation region 7 penetrates the original n+ doped region 401 and the original P-doped region 301 and extends into the original N-type drift layer 201, as shown in fig. 5.
Specifically, step S3 includes S301-S304:
s301: a protective layer is formed on the upper surface of the original n+ doped region 401.
S302: and openings are formed at the corners of the protective layer.
S303: ion implantation is carried out on the open hole areas to form a plurality of ion implantation areas 7 distributed at corner positions of the original N+ doped region 401; the ion implantation region 7 penetrates the original n+ doped region 401 and the original P-doped region 301 and extends into the original N-type drift layer 201; wherein each ion implantation region 7 may be formed by multiple implants.
S304: and removing the protective layer.
In this embodiment, four ion implantation regions 7 are respectively located at four corners of the original n+ doped region 401, and the four ion implantation regions 7 are spaced apart and symmetrical to each other. The bottom of the ion implantation region 7 is in the original N-type drift layer 201. The four ion implantation regions 7 may be formed with different doping concentrations by multiple ion implantations.
S4: etching is started from the edge of the original N+ doped region 401 into the ion implantation region along the circumferential direction of the original N+ doped region 401 to form a polygonal annular groove, and an N-type drift layer 2, a P-doped region 3, an N+ doped region 4 and an original shielding layer 601 are formed, as shown in FIG. 6.
In the present embodiment, the polygonal annular groove is a quadrangular annular groove, and four original shield layers 601 are distributed at each corner of the quadrangular annular groove and cover side surfaces and lower surfaces of the four corners. The four original shielding layers 601 are spaced apart and symmetrical to each other.
Preferably, the P-doped region 3 has a doping concentration of 8E16cm -3 The doping concentration of the N+ doped region 4 is 2E19cm -3 。
S5: preparing an electrode structure on the product prepared in the step S4, and forming a shielding layer 6; the shielding layer 6 is distributed at each corner of the polygonal annular trench and extends into the upper surface of the n+ doped region 4 and into the N-type drift layer 2.
Specifically, step S5 includes S501-S504:
s501: oxidizing the surface of the polygonal ring-shaped channel to form a gate oxide layer 8, a gateThe original shielding layer below the oxide layer 8 is the shielding layer 6. The doping concentration of the shielding layer 6 at a depth of 2.5 μm from the bottom of the gate oxide layer 8 was 1E17cm -3 The doping concentration of the shielding layer 6 on the upper surface of the N+ doped region 4 is 2E19cm -3 。
S502: a gate electrode 9 is prepared on the gate oxide layer 8.
Specifically, the specific step of step S502 is to fill PolySi on the gate oxide layer 8 to form the gate electrode 9, as shown in fig. 7.
S503: source metal is deposited on the surface of the n+ doped region 4 and the shielding layer 6 on the upper surface of the n+ doped region 4 to form a source electrode 10.
S504: a drain electrode 11 was prepared on the lower surface of the substrate layer 1, and as shown in fig. 8, the preparation was completed to obtain the SiCUMOSFET of example one.
In the present embodiment, the polygonal annular groove is a quadrangular annular groove, and four shield layers 6 are distributed at each corner of the quadrangular annular groove and cover the side surfaces and the lower surfaces of the four corners. The four shielding layers 6 are spaced apart and symmetrical to each other.
The SiC UMOSFET with the discontinuous P+ shielding layer prepared by the method of the embodiment forms the discontinuous P+ shielding layer 6 on the N-type drift layer 2, introduces a very small JFET region, optimizes the defect that the traditional UMOSFET is easy to break down at the bottom of a groove, and simultaneously solves the problems of large on-resistance and small current path of a continuous P+ shielding layer device. In addition, compared with the traditional UMOSFET without the shielding layer, the miller capacitance Cgd is optimized, the length of the miller platform is obviously reduced, and the miller platform is obviously optimized; compared with UMOSFETs with continuous shielding layers, the shielding layers connected with the source region are greatly reduced, cgs are greatly optimized, and although Cgd is affected, the miller platform is slightly increased in the switching process, the miller platform gap is extremely small, and the miller effect is hardly affected.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. A SiC UMOSFET with a discontinuous p+ shield layer, comprising:
a substrate layer (1);
an N-type drift layer (2) positioned on the upper surface of the substrate layer (1);
a P-doped region (3) located in the surface layer of the N-type drift layer (2);
an N+ doped region (4) located in the surface layer of the P-doped region (3);
the polygonal annular groove is positioned around the N+ doped region (4) and has a depth greater than the sum of the thicknesses of the N+ doped region (4) and the P-doped region (3);
a plurality of shielding layers (6) respectively positioned at each corner of the polygonal annular groove and extending to the upper surface of the N+ doped region (4) and the N-type drift layer (2);
the P+ column (5) is positioned in the middle of the N+ doped region (4), penetrates through the N+ doped region (4) and the P-doped region (3) and extends into the N-type drift layer (2);
and the electrode structure is connected with the polygonal annular groove, the N+ doped region (4) and the substrate layer (1).
2. The SiCUMOSFET with a discontinuous p+ shield of claim 1 wherein the electrode structure comprises:
a gate oxide layer (8) covering the surface of the polygonal annular groove;
a gate electrode (9) on the gate oxide layer (8);
a source electrode (10) covering the N+ doped region (4) and a shielding layer (6) on the upper surface of the N+ doped region (4);
and a drain electrode (11) positioned on the lower surface of the substrate layer (1).
3. SiC UMOSFET with discontinuous p+ shield according to claim 1, characterized in that the doping type of the shield layer (6) is p+ type doping.
4. SiC UMOSFET with discontinuous p+ shield according to claim 1 characterized in that the material of the substrate layer (1) is n+ doped 4H-SiC.
5. SiC UMOSFET with discontinuous p+ shield according to claim 2, characterized in that the gate electrode (9) material is PolySi.
6. A method for preparing a SiC UMOSFET with a discontinuous p+ shield layer, which is characterized by being applied to preparing the SiC UMOSFET with a discontinuous p+ shield layer according to any one of claims 1 to 5, comprising the following steps:
s1: growing an original N-type drift layer (201) on the substrate layer (1); ion implantation is performed in the original N-type drift layer (201) to form an original P-doped region (301) and an original N+ doped region (401); the original P-doped region (301) is located in the surface layer of the original N-type drift layer (201), and the original N+ doped region (401) is located in the surface layer of the original P-doped region (301);
s2: ion implantation is carried out in the middle of the original N+ doped region (401) to form a P+ column (5); the P+ column (5) penetrates the original N+ doped region (401) and the original P-doped region (301) and extends into the original N-type drift layer (201);
s3: performing ion implantation at each corner of the original n+ doped region (401) to form a plurality of ion implantation regions (7);
the ion implantation region (7) penetrates the original N+ doped region (401) and the original P-doped region (301) and extends into the original N-type drift layer (201);
s4: etching the edge of the original N+ doped region (401) into the ion implantation region (7) along the circumferential direction of the original N+ doped region (401) to form a polygonal annular groove, and forming an N-type drift layer (2), a P-doped region (3), an N+ doped region (4) and an original shielding layer (601);
s5: preparing an electrode structure on the product prepared in the step S4, and forming a shielding layer (6); the shielding layer (6) is distributed at each corner of the polygonal annular groove and extends to the upper surface of the N+ doped region (4) and the N-type drift layer (2).
7. The method for manufacturing a SiC UMOSFET with a discontinuous p+ shield layer of claim 6, wherein step S5 comprises:
s501: oxidizing the surface of the polygonal annular groove to form a gate oxide layer (8) and form the shielding layer (6);
s502: preparing a gate electrode (9) on the gate oxide layer (8);
s503: depositing source metal on the surfaces of the N+ doped region (4) and the shielding layer (6) positioned on the upper surface of the N+ doped region (4) to form a source electrode (10);
s504: and preparing a drain electrode (11) on the lower surface of the substrate layer (1).
8. The method for fabricating a SiC UMOSFET with a discontinuous p+ shield layer of claim 6, wherein step S3 comprises:
s301: forming a protective layer on the upper surface of the original N+ doped region (401);
s302: forming an opening at a corner on the protective layer;
s303: ion implantation is carried out on the open hole area to form a plurality of ion implantation areas (7) distributed at corner positions of the original N+ doped area (401); the ion implantation region (7) penetrates the original N+ doped region (401) and the original P-doped region (301) and extends into the original N-type drift layer (201);
s304: and removing the protective layer.
9. The method of manufacturing a SiC UMOSFET with a discontinuous p+ shield of claim 6 wherein the doping type of the shield (6) is p+ type doping.
10. The method for manufacturing a SiC UMOSFET with a discontinuous p+ shield layer of claim 7, wherein step S502 comprises: and filling PolySi on the gate oxide layer (8) to form the gate electrode (9).
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