WO2018033034A1

WO2018033034A1 - Semiconductor device with hybrid channel configuration

Info

Publication number: WO2018033034A1
Application number: PCT/CN2017/097326
Authority: WO
Inventors: Jing Chen; Jin Wei
Original assignee: The Hong Kong University Of Science And Technology
Priority date: 2016-08-17
Filing date: 2017-08-14
Publication date: 2018-02-22

Abstract

A semiconductor device (100) as described herein includes a substrate (111), a drift layer (112) formed onto the substrate (111), a trench formed into the drift layer (112) at a first surface of the drift layer (112) opposite the substrate (111), wherein the trench extends into the drift layer (112) to a trench depth and defines respective sidewalls of a mesa region orthogonal to the first surface of the drift layer (112), respective planar body regions (113) positioned in the drift layer (112) at the trench surface, respective planar source regions (114) positioned in the drift layer (112) at the trench surface and encapsulated by the respective planar body regions (113), respective mesa body regions (103) positioned in the mesa structure at the first surface of the drift layer (112), and respective mesa source regions (104) positioned in the mesa structure at the first surface of the drift layer (112) and encapsulated by the respective mesa body regions (103).

Description

SEMICONDUCTOR DEVICE WITH HYBRID CHANNEL CONFIGURATION

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of priority to U.S. Provisional Patent Application No. 62/494,680, filed August 17, 2016, and entitled “Semiconductor Device with Trench/Planar Channel Configuration, ” the entirety of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to semiconductor devices, and techniques for fabricating the same.

BACKGROUND

Power MOSFETs (metal-oxide-semiconductor field effect transistors) are presently popular as power switching devices for a variety of reasons. For instance, power MOSFETs can be simple to drive since they are voltage control devices. Further, a power MOSFET is a majority carrier device, which enables it to operate at a significantly higher frequency as compared to bipolar devices such as power bipolar junction transistors, insulated-gate bipolar transistors, and thyristors.

With regard to power MOSFETs, and other semiconductor devices in general, it is desirable to implement fabrication techniques for semiconductor devices that result in improved performance and efficiency of the fabricated devices.

SUMMARY

The following summary is a general overview of various embodiments disclosed herein and is not intended to be exhaustive or limiting upon the disclosed embodiments. Embodiments are better understood upon consideration of the detailed description below in conjunction with the accompanying drawings and claims.

In the disclosure, a novel MOSFET structure is provided. The disclosed MOSFET structure features planar channels and trench channels. The planar channels of the disclosed MOSFET are located at the surface of the bottom body regions, while the bottom body regions are located at the trenched regions. Mesa regions are formed between the trenched regions. The trench channels of the disclosed MOSFET are located at the sidewall of the top body regions, while the top body regions are located in a mesa. Various embodiments herein can provide reduced channel resistance while also protecting the gate oxide from high electric fields. Additionally, various embodiments herein can reduces the reverse transfer capacitance of the associated device.

In one embodiment, a semiconductor device is described herein. The semiconductor device includes a substrate doped to a first doping type, a drift layer doped to the first doping type and formed onto the substrate, and a trench formed into the drift layer at a first surface of the drift layer opposite the substrate. The trench extends into the drift layer to a trench depth, and the trench defines a trench surface substantially parallel to the first surface of the drift layer and respective sidewalls of a mesa region orthogonal to the first surface of the drift layer. The semiconductor device further includes respective planar body regions doped to a second doping type that is opposite the first doping type and positioned in the drift layer at the trench surface, respective planar source regions doped to the first doping type, positioned in the drift layer at the trench surface, and encapsulated by the respective planar body regions, respective mesa body regions doped to the second doping type and positioned in the mesa structure at the first surface of the drift layer, and respective mesa source regions doped to the first doping type, positioned in the mesa structure at the first surface of the drift layer, and encapsulated by the respective mesa body regions.

In another embodiment, a method is described herein. The method includes growing a drift layer on a semiconductor substrate, forming respective first body regions at a first surface of the drift layer opposite the semiconductor substrate, forming respective first source regions at the first surface of the drift layer that are encapsulated by the respective first body regions, etching one or more regions at the first surface of the drift layer, resulting in a trench in the drift layer having a trench surface and defining a mesa that includes the respective first body regions and first source regions, forming respective second body regions at the trench surface of the drift layer, and forming respective second source regions at the trench surface of the drift layer that are encapsulated by the respective second body regions.

In a further embodiment, a semiconductor device is described herein. The semiconductor device includes a low resistivity semiconductor substrate having a first doping type, a drift layer on the substrate having a second doping type that is opposite to the first doping type, and a trench formed into the drift layer at a first surface of the drift layer opposite the substrate. The trench extends into the drift layer and defines a trench surface substantially parallel to the first surface of the drift layer and respective sidewalls of a mesa orthogonal to the first surface of the drift layer. The semiconductor device further includes respective first body regions having the first doping type that are positioned in the drift layer at the trench surface, respective first source regions having the second doping type that are positioned in the drift layer at the trench surface and encapsulated by the respective first body regions, respective second body regions having the first doping type that are positioned in the mesa, respective second source regions having the second doping type that are located in the mesa and encapsulated by the respective second body regions, and respective drain regions having the second doping type that are located at the first surface of the drift layer.

DESCRIPTION OF DRAWINGS

Various non-limiting embodiments of the subject disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout unless otherwise specified.

FIG. 1 is a schematic diagram illustrating a semiconductor device with a hybrid trench/planar channel configuration in accordance with various aspects described herein.

FIGS. 2-12 are diagrams illustrating respective stages of a process of fabricating a semiconductor device, e.g.， the semiconductor device of FIG. 1, in accordance with various aspects described herein.

FIG. 13 is a diagram illustrating an alternative structure that can be utilized for the semiconductor device of FIG. 1.

FIG. 14 is a schematic diagram illustrating another semiconductor device with a hybrid trench/planar channel configuration in accordance with various aspects described herein.

FIG. 15 is a schematic diagram illustrating an alternate configuration that can be employed by the semiconductor device of FIG. 14.

FIG. 16 is a diagram illustrating simulated electrical characteristics of the semiconductor device of FIG. 1 in comparison to existing MOSFET implementations.

FIG. 17 is a diagram illustrating simulated on-resistance of the semiconductor device of FIG. 1 in comparison to existing MOSFET implementations.

FIG. 18 is a diagram illustrating simulated off-state electric field strength in the gate insulator of the semiconductor device of FIG. 1 in comparison to existing MOSFET implementations.

FIG. 19 is a diagram illustrating simulated reverse transfer capacitance of the semiconductor device of FIG. 1 in comparison to existing MOSFET implementations.

FIG. 20 is a diagram illustrating simulated gate charge characteristics of the semiconductor device of FIG. 1 in comparison to existing MOSFET implementations.

FIGS. 21-22 are flow diagrams of respective processes for fabricating a semiconductor device in accordance with various aspects described herein.

DETAILED DESCRIPTION

Various specific details of the disclosed embodiments are provided in the description below. One skilled in the art will recognize, however, that the techniques described herein can in some cases be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. Additionally, it should be appreciated that elements in the drawings provided herein are not necessarily drawn to scale, and that some areas or elements may be expanded to help improve understanding of various embodiments described herein.

Semiconductor devices such as power MOSFETs are widely used in power switching applications due to their desirable properties for such applications. Two MOSFET architectures used in power-related applications include planar MOSFET (P-MOS) and trench MOSFET (T-MOS) . The P-MOS architecture, in comparison to T-MOS, exhibits a lower C_rss (feedback capacitance) and Q_GD (gate-to-drain charge) . If a split-gate structure is adopted for a P-MOS device, C_rss and Q_GD could be further reduced at a price of a stronger electric field at the gate corners. A disadvantage of P-MOS, however, is a larger channel resistance as compared to the T-MOS due to P-MOS having a smaller channel density. This is a particular disadvantage in the case of silicon carbide (SiC) -based MOSFETs, since the channel mobility of SiC is very low (e.g.， in the range of 10～20 cm²/V-s) . Therefore, it is desirable to implement techniques to reduce the channel resistance of SiC P-MOS.

The T-MOS architecture, in comparison to P-MOS, enables a more compact cell design with increased channel density (defined as channel width per unit area) . As a result, R_ON (overall on-resistance) of T-MOS can be lowered due to a corresponding reduction of channel resistance. A disadvantage of T-MOS, however, is its large reverse transfer capacitance (C_rss) , which could result in degraded switching performance and unfavorable performance in suppressing false turn-on. Another disadvantage of T-MOS is increased off-state electric field in the gate oxide, which can degrade long-term device reliability, especially in the case of devices such as SiC-based trench MOSFETs having a critical breakdown field that is higher than that of silicon. Implementation of a p-type shield layer under the gate trench can be effective to suppress the high oxide field in T-MOS, but a poorly grounded shield layer can result in degraded switching performance.

Various embodiments herein provide for a hybrid trench/planar MOSFET (TP-MOS) , which features a trench channel and a planar channel in one half-cell. The gate terminal in the trench controls the current flow in both the vertical channel along the trench sidewall and the lateral channel at the trench bottom. Therefore, channel density for the TP-MOS architecture is increased compared to that of P-MOS, resulting in a low R_ON. Further, the C_rss and Q_GD of TP-MOS are lower than that of either P-MOS or T-MOS since the coupling between the gate and the drain is suppressed by the collective shielding effects of the top p-base and the bottom p-base. When a TP-MOS device as described herein is implemented on wide bandgap semiconductors, such as SiC, the p-bases for the planar channel also serve as a protection for the trench gate, resulting in a low oxide field in the OFF-state. As will be described below, the various TP-MOS structures described herein exhibit these and/or other advantages over traditional SiC MOSFETs, silicon MOSFETs, or the like.

Turning now to FIG. 1, a cross-section of an example TP-MOS device 100 in accordance with various aspects described herein. The device 100 includes a substrate 111 doped to a first doping type (e.g.， n+-type doping) and a drift layer 112 doped to the first doping type and formed onto the substrate 111. The device also includes bottom body regions 113 for respective planar channels located at the surface of a trench formed into the drift layer 112 as well as bottom source regions 114 encapsulated by the bottom body regions 113. In an aspect, the bottom body regions 113 can be doped to a second doping type (e.g., p-type doping) that is opposite the first doping type, while the bottom source regions 114 can be doped to the first doping type (e.g.， n+) . The device 100 can further include top body regions 103 and top source regions 104 located in a mesa defined by the trench positioned on either side of the mesa. As with the bottom body regions 113 and bottom source regions 114, the top body regions 103 can be doped to the second doping type (e.g.， p) and the top source regions 104 can be doped to the first doping type (e.g., n+) .

The device 100 shown in FIG. 1 further includes a gate insulator 115 covering the respective sidewalls of the mesa and at least a portion of the trench surface. A gate electrode 121 is subsequently formed onto the gate insulator 115. The device 100 further includes a source electrode 122 that covers the

regions

103, 104, 113, 114, as well as a drain electrode 123 contacting the substrate 111. As shown by FIG. 1, the gate electrode 121 and the semiconductor structure of the device 100 are separated by the gate insulator 115, and the gate electrode 121 and source electrode 122 are separated by an additional insulator 116.

With a gate-to-source voltage higher than the threshold voltages of the planar channels and the trench channels, a planar channel is formed in the device 100 at the surface of the bottom body regions 113 between the bottom source regions 114 and the drift layer 112. Additionally, a trench channel is formed at the sidewall of the top body regions 103.

It can be appreciated that because the effective channel width of device 100 is increased, the channel resistance of device 100 is correspondingly reduced. In the off-state, the

body regions

103, 113 collectively screen high drain voltage, and as a consequence the electric field strength in the gate oxide can be reduced. Owing to the screening effect of the

body regions

103, 113, the reverse transfer capacitance of device 100 can also be reduced. Thus, in various aspects, device 100 combines the advantages of conventional T-MOS and P-MOS architectures.

Turning next to FIGS. 2-12, diagrams are provided that illustrate respective stages of manufacturing a semiconductor device, e.g.， device 100. For simplicity and clarity of illustration, FIGS. 2-12 illustrate a specific, non-limiting example manner of construction, and it should be appreciated that various device manufacturing techniques could use steps that differ from those illustrated in FIGS. 2-12, as well as add or omit steps as shown by FIGS. 2-12, without departing from the present disclosure and the claimed subject matter. Further, descriptions and/or details of well-known features or techniques may be omitted to avoid unnecessarily obscuring the disclosure. Additionally, to the extent that the following description uses relative terms, such as “above, ” “on top of, ” “under, ” or the like, it should be appreciated that these terms relate only to the arrangement of the various device structures as shown in FIGS. 2-12 for purposes of clarity, and that these structures could be oriented in any suitable manner that substantially conforms to the shown relative structure placements. Further, the techniques provided by FIGS. 2-12 and the accompanying description are intended to include any modifications, combinations, and/or other variations that would be readily apparent to those of skill in the art.

With reference again to the drawings, diagram 200 in FIG. 2 illustrates a first stage of the fabrication process. Here, fabrication begins with substrate 111, e.g., an n+substrate. A drift layer 112, e.g.， an n-type drift layer, can be formed on top of the substrate 111. In an aspect, the thickness and/or doping concentration of the drift layer 112 can be determined based on the desired blocking voltage of the finished device.

Next, as shown by diagram 300 in FIG. 3, a top (mesa) body region 103 is initially formed onto and/or from drift layer 112 as a semiconductor layer, e.g.， a p-layer. The top body region 103 can be formed via techniques such as ion implantation, epitaxal growth, and/or any other suitable technique (s) .

As shown by diagram 400 in FIG. 4, top source regions 104 are then formed into the top body region 103, e.g.， as n+ regions or the like. Similar to the top body region 103, the top source regions 104 can be formed via techniques such as ion implantation, epitaxal growth, and/or any other suitable technique (s) .

In a subsequent stage as shown by diagram 500 in FIG. 5, a dielectric layer can be deposited onto a portion of the top body region 103 and top source regions 104 and patterned to serve as a hard mask 131 for the following process stages. In an aspect, the hard mask 131 can be composed of silicon oxide (SiO₂) and/or any other suitable material (s) .

As subsequently shown by diagram 600 in FIG. 6, a trench is formed in the device via dry etching of the semiconductor layers 112, 103, 104 based on the hard mask 131 applied at the previous stage. In an aspect, the depth of the trench formed as shown by FIG. 6 can be larger than the thickness of the top body region 103, e.g.， such that the trench extends beyond the bottom of the top body region 103.

As shown by diagram 700 in FIG. 7, the bottom (planar) body regions 113 and bottom source regions 114 are formed into the drift layer 112. In an aspect, the bottom body regions 113 and bottom source regions 114 can be formed via ion implantation, e.g.， to form the bottom body regions 113 as p-regions and the bottom source regions 114 as n+ regions. As further shown in FIG. 7, the bottom body regions 113 can be positioned at the bottom of the trench created as shown by FIG. 6 and constrained by the sidewalls of the resulting mesa.

Following formation of the bottom body regions 113 and bottom source regions 114 as shown by FIG. 7, the hard mask 131 can be removed as shown by diagram 800 in FIG. 8. Removal of the hard mask 131 can be performed via wet etching, dry etching, and/or any other suitable technique (s) . Additionally, the device is annealed subsequent to removal of the hard mask 131, e.g.， via thermal annealing, to activate the dopants introduced into the device in the preceding stages.

As shown next by diagram 900 in FIG. 9, an insulator 115 is formed onto the top surface of the semiconductor structure via thermal oxidation of the semiconductor, deposition, and/or other technique (s) . Following formation of the insulator 115, a polysilicon layer 121 is deposited onto the insulator 115.

The polysilicon layer 121 formed as shown by FIG. 9 is then etched, e.g., via dry etching, as shown by diagram 1000 in FIG. 10. In addition to the polysilicon layer 121, the insulator 115 applied as shown by FIG. 9 is also etched with and/or after etching of the polysilicon layer 121. As shown by FIG. 10, the etch time for the polysilicon layer 121 and insulator 115 is controlled such that a portion of the polysilicon layer 121 and associated insulator 115 remain at the sidewall of the trench.

Following the etching shown in FIG. 10, another insulator 116 is deposited and patterned, as shown by diagram 1100 in FIG. 11. Subsequently, as shown by diagram 1200 in FIG. 12, a source contact 122 and drain contact 123 are formed onto respective surfaces of the device and annealed (e.g.， via thermal annealing) .

Turning next to FIG. 13, a device 1300 is illustrated that exhibits an alternate structure to that employed by device 100, etc. Here, the components of device 1300 are similar to those described above with respect to device 100, with the exception that the bottom body regions 113 are not aligned with the trench edge. Stated another way, the bottom body regions 113 are formed such that the interior edges of the respective bottom body regions 113 are positioned at a nonzero distance from the sidewalls of the mesa.

With reference to FIG. 14, another embodiment of a semiconductor device 1400 that can be manufactured as described herein is illustrated. The device 1400 includes a low resistivity semiconductor substrate 217 having a first doping type, e.g.， such that the substrate 217 is a p-region. The device 1400 further includes a drift layer 212 on the substrate having a second doping type that is opposite the first doping type, e.g.， such that the drift layer 212 is an n+ region. As further shown by FIG. 14, a trench is formed into the drift layer 212 at a first surface of the drift layer 212 opposite the substrate 217. The trench extends into the drift layer 212 and can define a trench surface substantially parallel to the first surface of the drift layer 212 and respective sidewalls of a mesa orthogonal to the first surface of the drift layer 212.

Additionally, device 1400 includes respective first body regions 213 having the first doping type (e.g.， p-type doping) and positioned in the drift layer 212 at the trench surface, as well as first source regions 214 having the second doping type (e.g.， n+-type doping) and encapsulated by respective first body regions 213. The device 1400 further includes respective second body regions 203 having the first doping type (e.g.， p-type doping) positioned in the mesa and second source regions 204 having the second doping type (e.g., n+-type doping) and encapsulated by respective second body regions 203. The device 1400 additionally includes drain regions 211 having the second doping type (e.g.， n+-type doping) and located at the first surface of the drift layer 212.

As additionally shown by FIG. 14, the device 1400 includes a link region or p-sink layer 218 having the first doping type (e.g.， p-type doping) and connecting the respective first body regions 213 and the substrate 217. Similar to device 100, device 1400 also includes a gate electrode 221, a source electrode 222, and a drain electrode 223. In an aspect, the source electrode 222 contacts the respective first body regions 213, first source regions 214, second body regions 203, and second source regions 204 and is electrically connected to the substrate 217 via the p-sink layer 218. The gate electrode 221 is separated from its surrounding semiconductor features via a gate insulator 215. Additionally, the gate electrode 221 and source electrode 222 are separated by a second insulator 216.

With a gate-to-source voltage that is higher than the threshold voltages of the planar channels and the trench channels of device 1400, a planar channel is formed at the surface of the first body regions 213 between the corresponding first source regions 214 and the drift region 212. Similarly, a trench channel is formed at the sidewall of the second body regions 203.

An alternate embodiment to device 1400 is shown by device 1500 in FIG. 15. Here, the features of device 1500 are substantially similar to the features of device 1400 as described above, with the addition of a body extension region 205 located in the mesa adjacent to the second body regions 203.

In an aspect, spacer-gate, side-gate, and/or other technology could be utilized to form the gate of the devices described above, e.g.， such that the gate leans against one side of the mesa. Additionally, in view of the anisotropic oxidation rates for SiC, a deposited dielectric can be used as the main body of the gate dielectric for the TP-MOS structure. Alternatively, an oxide converted from a deposited polysilicon can be used.

With respect to FIGS. 16-20 and the associated description, results of various simulations and/or experiments associated with the device structures shown above are provided. The devices used for simulation were based on a SiC structure； however, it should be appreciated that the various embodiments described herein could also be implemented on other semiconductors, such as silicon, gallium nitride, diamond, etc. The devices utilized for the simulation are designed for a 1200V voltage rating. The thickness of the drift region (e.g., from the gate bottom to the backside n+ region) is 11 μm, and the doping concentration of the drift region is 8×10¹⁵ cm^-2. The doping concentrations of the JFET (junction gate FET) regions in the utilized P-MOS and TP-MOS structures are 2×10¹⁶ cm^-2. The devices are associated with a channel length of 0.5 μm and an electron mobility of 20 cm²/V-s. In the P-MOS and TP-MOS structures, the width of the JFET region is W_JFET ＝ 1.8 μm, and the cell size is W_cell ＝ 5.6 μm. For the T-MOS structure, the cell size is W_cell ＝ 3 μm. The gate oxide is 50 nm for both the sidewall and the bottom.

Simulated current-voltage (I-V) characteristics of an example SiC MOSFET as described herein is shown by diagram 1600 in FIG. 16 in comparison to similar characteristics for T-MOS and P-MOS structures. As shown by diagram 1600, the T-MOS and TP-MOS structures exhibit a lower R_ON than the P-MOS because of their higher channel densities. The high channel density in the T-MOS results in an increased saturation current compared to P-MOS. While the TP-MOS structure has similar channel density as that of T-MOS, the TP-MOS structure shows a less appreciable increase of saturation current owing to the presence of the JFET region, which can in turn result in improved short-circuit capability. The breakdown voltage of the T-MOS structure is slightly higher than that of P-MOS and TP-MOS since no JFET doping is implemented in the T-MOS and its effective drift region thickness is larger. The breakdown voltage of the P-MOS structure is slightly higher than that of TP-MOS because the MOS structure above the JFET region serves as a field plate

Simulated on-resistance (R_ON) characteristics of an example SiC MOSFET as described herein is shown by diagram 1700 in FIG. 17 in comparison to similar characteristics for T-MOS and P-MOS structures. Since the TP-MOS structure contains two channel types in a single half-cell, for convenience, a 0.3-μm length (e.g.， half of the distance between two channels in the TP-MOS structure) outside of the channel is counted in the calculation of channel resistance for each of the devices shown in diagram 1700. The R_ON of the P-MOS structure is 2.90 mΩ·cm², which is dominated by channel resistance due to low channel mobility. In contrast, the T-MOS and TP-MOS structures exhibit lower R_ON characteristics, namely 2.05 mΩ·cm² and 2.18 mΩ·cm², respectively. This reduction in R_ON stems from lower channel resistance as a result of an increased number of channels in a given area.

Diagram 1800 in FIG. 18 illustrates OFF-state (V_DS ＝ 1200 V) electric field distributions of an example SiC MOSFET as described herein in comparison to similar characteristics for T-MOS and P-MOS structures. As shown by diagram 1800, the T-MOS structure suffers from a high E_ox-m of 9.20 MV/cm located at the trench corner as well as an oxide field at the trench bottom of 5.43 MV/cm, both of which are beyond a conventionally acceptable level of 3 MV/cm. It is noted that trench corner profile is process-dependent. For instance, a rounded corner with a large radius of curvature is expected to achieve a lower local oxide field. However, this field can be no less than that at the trench bottom. With the shielding effect provided by the p-bases in the P-MOS structure, the E_ox-m is lowered to 2.48 MV/cm, located at the middle of the MOS-structure with the farthest distance to the p-bases. In contrast to both T-MOS and P-MOS, the TP-MOS structure features an E_ox-m (0.99 MV/cm) that is lower than that of P-MOS because the vulnerable portion of the MOS structure above the JFET region is removed.

Diagram 1900 in FIG. 19 illustrates simulated feedback capacitance (C_rss) characteristics of an example SiC MOSFET in comparison to similar characteristics for T-MOS and P-MOS structures. As shown by diagram 1900, the T-MOS structure exhibits a larger C_rss between the gate and the drain due to the fact that the gate electrode is not completely surrounded by the p-base. The P-MOS architecture utilizes p-bases to shield the gate electrode, resulting in a lower C_rss. However, the middle portion of the gate electrode in the P-MOS structure is still not fully screened by the p-bases, and this is a significant source of C_rss in the P-MOS structure. The TP-MOS structure, in contrast, eliminates the MOS gate above the JFET region and features a gate screened collectively by the top p-base and the bottom p-base. As a result, coupling between the gate and the drain is weak in the TP-MOS structure, resulting in the lowest C_rss among the three devices (i.e., P-MOS, T-MOS, and TP-MOS) .

In diagram 2000 shown by FIG. 20, the gate charges of the three MOSFET structures (i.e., P-MOS, T-MOS, and TP-MOS) are simulated. As shown in diagram 2000, Q_G and Q_GD for the P-MOS structure are 692 nC/cm² and 237 nC/cm², respectively. The T-MOS structure exhibits a larger Q_G of 2262 nC/cm² and a larger Q_GD of 1274 nC/cm² due to its increased channel density and unscreened gate trench. The Q_G of the TP-MOS structure is 695 nC/cm², which is similar to that of P-MOS. The Q_GD of the TP-MOS structure is 145 nC/cm², which is the lowest among the three devices. In terms of overall performance, the TP-MOS structure exhibits the best performance of the three structures in terms of Q_G×R_ON and Q_G×R_ON.

In an aspect, TP-MOS device structures as described herein exhibit various advantages. These include, but are not limited to, a lower on-resistance than conventional P-MOS, a lower electric field in the gate oxide than conventional T-MOS and P-MOS, a lower C_rss than conventional T-MOS and P-MOS, and lower Q_GD than both P-MOS and T-MOS.

Turning next to FIGS. 21-22, flow diagrams of respective methods of manufacturing a semiconductor device are illustrated. While, for purposes of simplicity of explanation, the methods are shown and described as series of acts, it is to be understood and appreciated that this disclosure is not limited by the order of acts, as some acts may occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that methods can alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement methods in accordance with certain aspects of this disclosure.

With reference first to FIG. 21, presented is a flow diagram of a process 2100 for fabricating a semiconductor device, e.g.， any of the

semiconductor devices

100, 1300, 1400, and/or 1500, in accordance with various aspects described herein. Process 2100 begins at 2102 by growing a drift layer on a semiconductor substrate. At 2104, respective first body regions are formed at a first surface of the drift layer opposite the semiconductor substrate. The first body regions formed at 2104 can be generated using any suitable technique (s) , such as epitaxal growth, ion implantation, or the like.

At 2106, first source regions are formed at the first surface of the drift layer. The first source regions formed at 2106 are positioned such that they are encapsulated (e.g., fully enclosed by) the first body regions formed at 2104. In an aspect, the first source regions can be formed at 2106 using ion implantation and/or any other suitable technique (s) .

At 2108, one or more regions at the first surface of the drift layer are etched, resulting in a trench being formed in the drift layer. The trench, in turn, defines a mesa that includes the first body regions formed at 2104 and the first source regions formed at 2106.

At 2110, second body regions are formed at the trench surface of the drift layer as created at 2108. In an aspect, the second body regions can be formed using ion implantation and/or any other suitable technique (s) .

At 2112, second source regions are formed at the trench surface of the drift layer. The second source regions formed at 2112 are positioned such that they are encapsulated (e.g.， fully enclosed by) the second body regions formed at 2110. In an aspect, the second source regions can be formed using ion implantation and/or any other suitable technique (s) .

Turning next to FIG. 22, a flow diagram of an additional process 2200 for fabricating a semiconductor device is presented. While process 2200 is illustrated as a continuation of process 2100, it should be appreciated that process 2100 could be performed with or without process 2200 and/or with supplemental processes that differ from that illustrated by FIG. 22. Similarly, process 2200 could be performed as an extension of a process that differs from process 2100 as shown by FIG. 21.

At 2202, a first thermal annealing is performed on a semiconductor device, e.g., a semiconductor device resulting from process 2100. In an aspect, the thermal annealing performed at 2202 activates dopants present in the semiconductor device at regions which can include, but are not limited to, the semiconductor substrate, the respective first body regions, the respective first source regions, the respective second body regions, and/or the respective second source regions.

At 2204, a gate insulator is formed on the mesa and the trench surface of the drift layer of the semiconductor device. In an aspect, the gate insulator can be formed at 2204 using techniques such as thermal oxidation, deposition, and/or other suitable technique (s) .

At 2206, a polysilicon layer is deposited onto the gate insulator formed at 2204. At 2208, the polysilicon layer deposited at 2206 is etched, leaving respective remaining polysilicon regions covering at least a portion of respective sidewalls of the mesa and at least a portion of the trench surface. At 2210, a mesa sidewall insulator is deposited onto the remaining polysilicon regions resulting from the etching at 2208.

At 2212, ohmic contacts are formed to the first source regions, first body regions, second source regions, second body regions, and substrate of the semiconductor device. In an aspect, the regions to which the ohmic contacts are formed at 2212 can be regions resulting from the respectively corresponding acts of process 2100, and/or other suitable acts or processing steps. At 2214, the process 2200 concludes by performing a second thermal annealing on the semiconductor device.

The above description includes non-limiting examples of the various embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the disclosed subject matter, and one skilled in the art may recognize that further combinations and permutations of the various embodiments are possible. The disclosed subject matter is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

With regard to the various functions performed by the above described components, devices, circuits, systems, etc., the terms (including a reference to a “means” ) used to describe such components are intended to also include, unless otherwise indicated, any structure (s) which performs the specified function of the described component (e.g., a functional equivalent) , even if not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosed subject matter may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

The terms “exemplary” and/or “demonstrative” as used herein are intended to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and/or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent structures and techniques known to one skilled in the art. Furthermore, to the extent that the terms “includes, ” “has, ” “contains, ” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive -in a manner similar to the term “comprising” as an open transition word -without precluding any additional or other elements.

The term “or” as used herein is intended to mean an inclusive “or” rather than an exclusive “or. ” For example, the phrase “A or B” is intended to include instances of A, B, and both A and B. Additionally, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless either otherwise specified or clear from the context to be directed to a singular form.

The term “set” as employed herein excludes the empty set, i.e., the set with no elements therein. Thus, a “set” in the subject disclosure includes one or more elements or entities. Likewise, the term “group” as utilized herein refers to a collection of one or more entities.

The description of illustrated embodiments of the subject disclosure as provided herein, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as one skilled in the art can recognize. In this regard, while the subject matter has been described herein in connection with various embodiments and corresponding drawings, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below.

Claims

A semiconductor device, comprising:

a substrate doped to a first doping type；

a drift layer doped to the first doping type and formed onto the substrate；

a trench formed into the drift layer at a first surface of the drift layer opposite the substrate, wherein the trench extends into the drift layer to a trench depth, and wherein the trench defines a trench surface substantially parallel to the first surface of the drift layer and respective sidewalls of a mesa region orthogonal to the first surface of the drift layer；

respective planar body regions doped to a second doping type that is opposite the first doping type and positioned in the drift layer at the trench surface；

respective planar source regions doped to the first doping type, positioned in the drift layer at the trench surface, and encapsulated by the respective planar body regions；

respective mesa body regions doped to the second doping type and positioned in the mesa structure at the first surface of the drift layer； and

respective mesa source regions doped to the first doping type, positioned in the mesa structure at the first surface of the drift layer, and encapsulated by the respective mesa body regions.
The semiconductor device of claim 1, further comprising:

a gate insulator covering the respective sidewalls of the mesa region and at least a portion of the trench surface； and

a gate electrode formed onto the gate insulator.
The semiconductor device of claim 1, further comprising a source electrode contacting the respective planar source regions, the respective planar body regions, the respective mesa source regions, and the respective mesa body regions.
The semiconductor device of claim 1, further comprising a drain electrode contacting the substrate.
The semiconductor device of claim 1, wherein interior edges of the respective planar body regions are positioned at a nonzero distance from the sidewalls of the mesa.
A method, comprising:

growing a drift layer on a semiconductor substrate；

forming respective first body regions at a first surface of the drift layer opposite the semiconductor substrate；

forming respective first source regions at the first surface of the drift layer, wherein the respective first source regions are encapsulated by the respective first body regions；

etching one or more regions at the first surface of the drift layer, resulting in a trench in the drift layer having a trench surface and defining a mesa comprising the respective first body regions and first source regions；

forming respective second body regions at the trench surface of the drift layer； and

forming respective second source regions at the trench surface of the drift layer, wherein the respective second source regions are encapsulated by the respective second body regions.
The method of claim 6, wherein the forming the respective first body regions comprises forming the respective first body regions via epitaxal growth or ion implantation.
The method of claim 7, wherein the forming the respective first source regions comprises forming the respective first source regions via ion implantation.
The method of claim 6, wherein the forming the respective second body regions comprises forming the respective first body regions via ion implantation.
The method of claim 9, wherein the forming the respective second source regions comprises forming the respective second source regions via ion implantation.
The method of claim 6, further comprising performing a first thermal annealing on the semiconductor device, thereby activating dopants present in a semiconductor device that comprises the semiconductor substrate, the respective first body regions, the respective first source regions, the respective second body regions, and the respective second source regions.
The method of claim 11, further comprising:

forming a gate insulator on the mesa and the trench surface；

depositing a polysilicon layer on the gate insulator； and

etching the polysilicon layer, leaving respective remaining polysilicon regions covering at least a portion of respective sidewalls of the mesa and at least a portion of the trench surface.
The method of claim 12, further comprising depositing a mesa sidewall insulator onto the respective remaining polysilicon regions.
The method of claim 13, further comprising forming respective ohmic contacts to the first source regions, the first body regions, the second source regions, the second body regions, and the substrate.
The method of claim 14, further comprising performing a second thermal annealing on the semiconductor device.
The method of claim 12, wherein the forming the gate insulator comprises forming the gate insulator via thermal oxidation or deposition.
A semiconductor device, comprising:

a low resistivity semiconductor substrate having a first doping type；

a drift layer on the substrate having a second doping type that is opposite to the first doping type；

a trench formed into the drift layer at a first surface of the drift layer opposite the substrate, wherein the trench extends into the drift layer and defines a trench surface substantially parallel to the first surface of the drift layer and respective sidewalls of a mesa orthogonal to the first surface of the drift layer；

respective first body regions having the first doping type, wherein the respective first body regions are positioned in the drift layer at the trench surface；

respective first source regions having the second doping type, wherein the respective first source regions are positioned in the drift layer at the trench surface and encapsulated by the respective first body regions；

respective second body regions having the first doping type, wherein the respective second body regions are positioned in the mesa；

respective second source regions having the second doping type, wherein the respective second source regions are located in the mesa and encapsulated by the respective second body regions； and

respective drain regions having the second doping type, wherein the respective drain regions are located at the first surface of the drift layer.
The semiconductor device of claim 17, further comprising:

a gate insulator covering a sidewall of the mesa and at least a portion of the trench surface；

a gate electrode formed onto the gate insulator；

a source electrode contacting the respective first body regions, the respective first source regions, the respective second body regions, and the respective second source regions；

a drain electrode contacting the respective drain regions； and

a link region having the first doping type and connecting the respective first body regions and the substrate.
The semiconductor device of claim 17, wherein interior edges of the respective first body regions are positioned at a nonzero distance from the sidewalls of the mesa.
The semiconductor device of claim 17, further comprising a body extension region in the mesa adjacent to the respective second body regions.