CN105206668A - Vertical MOS power device and formation method thereof - Google Patents
Vertical MOS power device and formation method thereof Download PDFInfo
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- CN105206668A CN105206668A CN201410305139.7A CN201410305139A CN105206668A CN 105206668 A CN105206668 A CN 105206668A CN 201410305139 A CN201410305139 A CN 201410305139A CN 105206668 A CN105206668 A CN 105206668A
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Abstract
The invention provides a vertical MOS power device. The vertical MOS power device can be a plane type or a groove type. In the vertical MOS power device, the entire or part of a grid electrode which generates a Miller capacitance is eliminated, the Miller capacitance is reduced distinctly, so that the feedback effect of voltage changes of a second electrode on the grid electrode voltage is eliminated or reduced distinctly, and therefore a Miller platform or an oscillation phenomenon in the switching process is avoided or reduced, the switching time of a device is shortened, the switch speed of the device is improved, the switch consumption is reduced, the power device is made safer and more reliable. The vertical MOS power device has advantages of being simple in structure, being low in cost and the like. The invention also provides a formation method of the vertical MOS power device.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to vertical MOS power device and forming method thereof.
Background technology
Vertical MOS power device grids adopts voltage driven, and have switching speed fast, the advantages such as drive circuit is simple, are widely used in low-pressure field and mesohigh field.Common MOS type power device is mainly divided into plane and groove-shaped two kinds according to its grid structure shape is different with channel direction.Fig. 1 is the schematic diagram of traditional planar vertical MOS power device.Wherein 101 is Withstand voltage layer, and 102 is P type trap zone, and 103 is N-shaped source region, and 104 is grid oxic horizon, and 105 is grid, and 106 is insulating dielectric layer, and 107 is negative electrode, and anode does not draw below Withstand voltage layer 101.Wherein the P type trap zone 102 surface part relative with grid 105 is channel region.Fig. 2 is the schematic diagram of traditional trench vertical MOS power device.Wherein 201 is Withstand voltage layer, and 202 is P type trap zone, and 203 is N-shaped source region, and 204 is grid oxic horizon, and 205 is grid, and 206 is insulating dielectric layer, and 207 is negative electrode, and anode does not draw below Withstand voltage layer 201, and 208 is floating P type trap zone.The part that wherein P type trap zone 202 side is relative with grid 205 is channel region.Turning on and off of vertical MOS power device shown in Fig. 1 and Fig. 2 is realized by the voltage of control gate.When grid voltage is higher than threshold voltage, then form conducting channel on P type trap zone surface, electric current can from anode through Withstand voltage layer, and conducting channel flows to source region and finally reaches negative electrode, the voltage drop on anode and Withstand voltage layer, break-over of device.Otherwise turn off then, be grid voltage lower than threshold voltage, the surface conduction channel of P type trap zone disappears, and current path is truncated, the voltage rise of Withstand voltage layer and anode, and device ends.
In traditional vertical MOS power device shown in Fig. 1 and Fig. 2, grid is except relative with P type trap zone, some area is relative with Withstand voltage layer or Withstand voltage layer surface, grid-oxide layer-semicoductor capacitor that this part is formed defines miller capacitance together with connecting with the depletion-layer capacitance in Withstand voltage layer body.This miller capacitance needs to carry out discharge and recharge in devices switch process, a part for anode voltage can be fed back to grid.This causes in opening process, grid voltage needs one period of charging interval of maintenance could continue to rise after reaching Miller platform, in turn off process, grid voltage also needs maintenance a period of time could continue to decline after dropping to Miller platform, reduces the switching loss that switching speed considerably increases device simultaneously.And because the change of anode voltage is often very large, its feedback also likely causes the violent waveform of grid voltage, forms vibration, causes device irregular working even to be burnt.
Summary of the invention
The present invention is intended to solve one of technical problem in correlation technique at least to a certain extent.For this reason, the object of the invention is to propose a kind of miller capacitance is little, switching speed is fast vertical MOS power device and forming method thereof.
The vertical MOS power device of embodiment according to a first aspect of the present invention, described vertical MOS power device is planar vertical MOS power device, can comprise: Withstand voltage layer; Multiple first doping type well region, described multiple first doping type well region is positioned at the top of described Withstand voltage layer; Multiple second doping type source region, described multiple second doping type source region is arranged in described multiple first doping type well region; Planar gate oxygen layer, described planar gate oxygen layer is positioned on described Withstand voltage layer, and the two ends of described planar gate oxygen layer contact respectively with adjacent two described second doping type source regions; Planar gate layer, described planar gate layer is positioned on described planar gate oxygen layer, and wherein, described planar gate layer does not cover or part covers correspondence position above described Withstand voltage layer; Insulating medium layer, two described second doping type source regions that described insulating medium layer covers described planar gate oxygen layer, described planar gate layer and contacts with described planar gate oxygen layer; First electrode, described first electrode is positioned on described insulating medium layer; And second electrode, described second electrode is positioned under described Withstand voltage layer.
The vertical MOS power device of embodiment according to a second aspect of the present invention, described vertical MOS power device is trench vertical MOS power device, can comprise: Withstand voltage layer; First doping type well region, described first doping type well region is positioned at the top of described Withstand voltage layer; Second doping type source region, described second doping type source region is arranged in the first doping type well region; Floating well region, described floating well region is positioned at the top of described Withstand voltage layer and is positioned near described first doping type well region, and described floating well region is identical with described first doping type well region doping type; Trench gate oxygen layer, described trench gate oxygen layer is positioned at the top of described Withstand voltage layer, the first side wall of described trench gate oxygen layer and described first doping type well region and described second doping type source contact, the second sidewall of described trench gate oxygen layer contacts with described floating well region; Trench-gate layer, it is inner that described trench-gate layer is full of described trench gate oxygen layer, and wherein, described trench-gate layer and described trench gate oxygen layer do not cover or partly cover the upper surface of described floating well region; Insulating medium layer, described insulating medium layer covers described planar gate oxygen layer, described planar gate layer, described floating well region and described second doping type source region; First electrode, described first electrode is positioned on described insulating medium layer; And second electrode, described second electrode is positioned under described Withstand voltage layer.
In vertical MOS power device according to the above embodiment of the present invention, by eliminating grid that is whole or part formation miller capacitance, miller capacitance obviously reduces, thus eliminate or obviously reduce the feedback effect of the second electrode voltage change to grid voltage, thus the Miller platform avoided or reduce in switching process and oscillatory occurences, shorten device switching time, improve devices switch speed, reduce switching loss, make power device more safe and reliable.In addition, the vertical MOS power device of this embodiment also has that structure is simple, low cost and other advantages.
The formation method of the vertical MOS power device of embodiment according to a third aspect of the present invention, described vertical MOS power device is planar vertical MOS power device, can comprise the following steps: provide Withstand voltage layer; On described Withstand voltage layer, form planar gate oxygen layer, described planar gate oxygen layer comprises the first area being positioned at two ends and the second area being positioned at centre; Planar gate layer is formed on the first area of described planar gate oxygen layer; First doping type well region and the second doping type source region are formed on the top of the described Withstand voltage layer under the first area of described planar gate oxygen layer, wherein said second doping type source region is arranged in the first doping type well region, and the two ends of described planar gate oxygen layer contact respectively with two described second doping type source regions; Form insulating medium layer, two described second doping type source regions that described insulating medium layer covers described planar gate oxygen layer, described planar gate layer and contacts with described planar gate oxygen layer; And form the first electrode and the second electrode, wherein, described first electrode is positioned on described insulating medium layer, and described second electrode is positioned under described Withstand voltage layer.
The formation method of the vertical MOS power device of embodiment according to a fourth aspect of the present invention, described vertical MOS power device is trench vertical MOS power device, can comprise the following steps: provide Withstand voltage layer; Form groove at described Withstand voltage layer top, then form trench gate oxygen layer at the inwall of described groove; On described trench gate oxygen layer, form trench-gate layer, described trench-gate layer and described trench gate oxygen layer do not cover or part covers the upper surface presetting floating well region region; First doping type well region, the second doping type source region and floating well region are formed on the top of the described Withstand voltage layer near described trench-gate layer, wherein, described second doping type source region is arranged in the first doping type well region, described first doping type well region contacts with the first side wall of described trench gate oxygen layer with described second doping type source region, the second sidewall contact of described floating well region and described trench gate oxygen layer; Form insulating medium layer, described insulating medium layer covers described trench gate oxygen layer, trench-gate layer, the second doping type source region and floating well region; And form the first electrode and the second electrode, wherein, described first electrode is positioned on described insulating medium layer, and described second electrode is positioned under described Withstand voltage layer.
In vertical MOS power device formation method according to the above embodiment of the present invention, by eliminating grid that is whole or part formation miller capacitance, miller capacitance obviously reduces, thus eliminate or obviously reduce the feedback effect of the second electrode voltage change to grid voltage, thus the Miller platform avoided or reduce in switching process and oscillatory occurences, shorten device switching time, improve devices switch speed, reduce switching loss, make power device more safe and reliable.In addition, the vertical MOS power device formation method of this embodiment also has that technique is simple, low cost and other advantages.
Accompanying drawing explanation
Fig. 1 is the structural representation of traditional planar vertical MOS power device.
Fig. 2 is the structural representation of traditional trench vertical MOS power device.
Fig. 3 is the structural representation of the planar vertical MOS power device of the embodiment of the present invention.
Fig. 4 is the structural representation of the trench vertical MOS power device of the embodiment of the present invention.
Fig. 5 is the flow chart of the planar vertical MOS power device formation method of the embodiment of the present invention.
Fig. 6 is the flow chart of the trench vertical MOS power device formation method of the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
First aspect present invention proposes a kind of planar vertical MOS power device.Fig. 3 is the structural representation of the planar vertical MOS power device of the embodiment of the present invention.
As shown in Figure 3, the planar vertical MOS power device of this embodiment can comprise: Withstand voltage layer 301, multiple first doping type well region 302, multiple second doping type source region 303, planar gate oxygen layer 304, planar gate layer 305, insulating medium layer 306, first electrode 307 and the second electrode (not shown in FIG.), multiple first doping type well regions 302 are positioned at the top of Withstand voltage layer 301.Multiple first doping type well region 302 is contrary with the doping type of Withstand voltage layer 301.It is contrary with the first doping type that multiple second doping type source region 303 is arranged in multiple first doping type well region 302, second doping type, and namely multiple second doping type source region 303 is identical with the doping type of Withstand voltage layer 301.Planar gate oxygen layer 304 is positioned on Withstand voltage layer 301, and the two ends of planar gate oxygen layer 304 contact respectively with adjacent two the second doping type source regions 303.Planar gate layer 305 is positioned on planar gate oxygen layer 304, and wherein, planar gate layer 305 does not cover or part covers correspondence position above Withstand voltage layer 301.As shown in Figure 3, planar gate layer 305 is only left the part above planar channeling, and the grid material be equivalent to above Withstand voltage layer 301 is eliminated completely or partially.Insulating medium layer 306 overlay planes grid oxide layer 304, planar gate layer 305 and two the second doping type source regions 303 contacted with planar gate oxygen layer 304.First electrode 307 is positioned on insulating medium layer 306.Second electrode is usually located under Withstand voltage layer 301, and the first electrode 307 is contrary with the second polarity of electrode.Those skilled in the art can determine the polarity of the first electrode and the second electrode according to actual conditions, such as, when Withstand voltage layer 301 is N-type, the first doping type well region 302 is P trap, the second doping type source region 303 is N district, the first electrode 307 should be negative electrode, and the second electrode is anode.This is the known knowledge of those skilled in the art, and the present invention does not repeat.
In the planar vertical MOS power device of above-described embodiment, by eliminating grid that is whole or part formation miller capacitance, miller capacitance obviously reduces, thus eliminate or obviously reduce the feedback effect of the second electrode voltage change to grid voltage, thus the Miller platform avoided or reduce in switching process and oscillatory occurences, shorten device switching time, improve devices switch speed, reduce switching loss, make power device more safe and reliable.This device also has that structure is simple, low cost and other advantages.
Second aspect present invention proposes a kind of trench vertical MOS power device.Fig. 4 is the structural representation of the trench vertical MOS power device of the embodiment of the present invention.
As shown in Figure 4, the trench vertical MOS power device of this embodiment can comprise: Withstand voltage layer 401, first doping type well region 402, second doping type source region 403, floating well region 408, trench gate oxygen layer 404, trench-gate layer 405, insulating matter layer 406, first electrode 407 and the second electrode (not shown in FIG.), first doping type well region 402 is positioned at the top of Withstand voltage layer 401, and the first doping type well region 402 is contrary with the doping type of Withstand voltage layer 401.It is contrary with the first doping type that second doping type source region 403 is arranged in the first doping type well region 402, second doping type, and namely the second doping type source region 403 is identical with the doping type of Withstand voltage layer 401.Floating well region 408 is positioned at the top of Withstand voltage layer 401 and is positioned near the first doping type well region 402, and floating well region 408 is identical with the first doping type well region 402 doping type.Trench gate oxygen layer 404 is positioned at the top of Withstand voltage layer 401, and the first side wall of trench gate oxygen layer 404 contacts with the second doping type source region 403 with the first doping type well region 402, and the second sidewall of trench gate oxygen layer 404 contacts with floating well region 408.It is inner that trench-gate layer 405 is full of trench gate oxygen layer 404, and the top of trench-gate layer 404 is higher than the top of the first doping type well region 402 with floating well region 408.Wherein, trench-gate layer 405 and trench gate oxygen layer 404 do not cover or partly cover the upper surface of floating well region 408.Insulating medium layer 406, insulating medium layer 406 overlay planes grid oxide layer 404, planar gate layer 405, floating well region 408 and the second doping type source region 403.First electrode 407 is positioned on insulating medium layer 406.Second electrode is positioned under Withstand voltage layer 401, and the first electrode 407 is contrary with the second polarity of electrode.Those skilled in the art can determine the polarity of the first electrode 407 and the second electrode according to actual conditions, such as, when Withstand voltage layer 401 is N-type, the first doping type well region 402 is P trap, the second doping type source region 403 is N district, floating well region 408 is floating P trap, first electrode 407 should be negative electrode, and the second electrode is anode.This is the known knowledge of those skilled in the art, and the present invention does not repeat.
In the trench vertical MOS power device of above-described embodiment, by eliminating grid that is whole or part formation miller capacitance, miller capacitance obviously reduces, thus eliminate or obviously reduce the feedback effect of the second electrode voltage change to grid voltage, thus the Miller platform avoided or reduce in switching process and oscillatory occurences, shorten device switching time, improve devices switch speed, reduce switching loss, make power device more safe and reliable.This device also has that structure is simple, low cost and other advantages.
Third aspect present invention proposes a kind of planar vertical MOS power device formation method.Fig. 5 is the flow chart of the planar vertical MOS power device formation method of the embodiment of the present invention.
As shown in Figure 5, the planar vertical MOS power device formation method of this embodiment can comprise the following steps:
S51. Withstand voltage layer is provided.
S52. on Withstand voltage layer, planar gate oxygen layer is formed.This planar gate oxygen layer comprises the first area being positioned at two ends and the second area being positioned at centre.
S53. on the first area of planar gate oxygen layer, planar gate layer is formed.
First doping type well region and the second doping type source region are formed on the top of the Withstand voltage layer S54. under the first area of planar gate oxygen layer, wherein the second doping type source region is arranged in the first doping type well region, and the two ends of planar gate oxygen layer contact respectively with two the second doping type source regions.Wherein, the first doping type well region is contrary with the doping type of Withstand voltage layer, and the second doping type source region is identical with the doping type of Withstand voltage layer.Such as, Withstand voltage layer is N-type, and the first doping type well region is P trap, and the second doping type source region is N district.Wherein, the first doping type well region and the second doping type source region can be formed by the technique such as photoetching and injection.
So far, the top at planar gate oxygen layer two ends has planar gate layer, and below has the second doping type source region, and the top in planar gate oxygen layer stage casing is without planar gate layer, and below is Withstand voltage layer.
S55. insulating medium layer is formed, insulating medium layer overlay planes grid oxide layer, planar gate layer and two the second doping type source regions contacted with planar gate oxygen layer.
S56. the first electrode and the second electrode is formed.Wherein, the first electrode is positioned on insulating medium layer, and the second electrode is positioned under Withstand voltage layer, and the first electrode is contrary with the second polarity of electrode.Such as, the first electrode is negative electrode, and the second electrode is anode.
In the planar vertical MOS power device formation method of above-described embodiment, by eliminating grid that is whole or part formation miller capacitance, miller capacitance obviously reduces, thus eliminate or obviously reduce the feedback effect of the second electrode voltage change to grid voltage, thus the Miller platform avoided or reduce in switching process and oscillatory occurences, shorten device switching time, improve devices switch speed, reduce switching loss, make power device more safe and reliable.This formation method also has that technique is simple, low cost and other advantages.
Fourth aspect present invention proposes a kind of trench vertical MOS power device formation method.Fig. 6 is the flow chart of the trench vertical MOS power device formation method of the embodiment of the present invention.
As shown in Figure 6, the trench vertical MOS power device formation method of this embodiment can comprise the following steps:
S61. Withstand voltage layer is provided.
S62. form groove at Withstand voltage layer top, then form trench gate oxygen layer at the inwall of groove.
S63. on trench gate oxygen layer, form trench-gate layer, trench-gate layer and trench gate oxygen layer do not cover or part covers the upper surface presetting floating well region region.
First doping type well region, the second doping type source region and floating well region are formed on the top of the Withstand voltage layer S64. near trench-gate layer, wherein, second doping type source region is arranged in the first doping type well region, first doping type well region contacts with the first side wall of trench gate oxygen layer with the second doping type source region, the second sidewall contact of floating well region and trench gate oxygen layer.First doping type well region is contrary with the doping type of Withstand voltage layer with floating well region, and the second doping type source region is identical with the doping type of Withstand voltage layer.Such as, Withstand voltage layer is N-type, and the first doping type well region is P trap, and the second doping type source region is N district, and floating well region is floating P trap.Wherein, the first doping type well region and the second doping type source region can be formed by the technique such as photoetching and injection.
S65. insulating medium layer is formed, insulating medium layer covering groove grid oxide layer, trench-gate layer, the second doping type source region and floating well region.
S66. the first electrode and the second electrode is formed.Wherein, the first electrode is positioned on insulating medium layer, and the second electrode is positioned under Withstand voltage layer.Such as, the first electrode is negative electrode, and the second electrode is anode.
In the trench vertical MOS power device formation method of above-described embodiment, by eliminating grid that is whole or part formation miller capacitance, miller capacitance obviously reduces, thus eliminate or obviously reduce the feedback effect of the second electrode voltage change to grid voltage, thus the Miller platform avoided or reduce in switching process and oscillatory occurences, shorten device switching time, improve devices switch speed, reduce switching loss, make power device more safe and reliable.This formation method also has that technique is simple, low cost and other advantages.
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", " counterclockwise ", " axis ", " radial direction ", orientation or the position relationship of the instruction such as " circumference " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise at least one this feature.In describing the invention, the implication of " multiple " is at least two, such as two, three etc., unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or integral; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals or the interaction relationship of two elements, unless otherwise clear and definite restriction.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature " on " or D score can be that the first and second features directly contact, or the first and second features are by intermediary indirect contact.And, fisrt feature second feature " on ", " top " and " above " but fisrt feature directly over second feature or oblique upper, or only represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " below " and " below " can be fisrt feature immediately below second feature or tiltedly below, or only represent that fisrt feature level height is less than second feature.
Describe and can be understood in flow chart or in this any process otherwise described or method, represent and comprise one or more for realizing the module of the code of the executable instruction of the step of specific logical function or process, fragment or part, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can not according to order that is shown or that discuss, comprise according to involved function by the mode while of basic or by contrary order, carry out n-back test, this should understand by embodiments of the invention person of ordinary skill in the field.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not must for be identical embodiment or example.And the specific features of description, structure, material or feature can combine in one or more embodiment in office or example in an appropriate manner.In addition, when not conflicting, the feature of the different embodiment described in this specification or example and different embodiment or example can carry out combining and combining by those skilled in the art.
Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, revises, replace and modification.
Claims (10)
1. a vertical MOS power device, is characterized in that, described vertical MOS power device is planar vertical MOS power device, comprising:
Withstand voltage layer;
Multiple first doping type well region, described multiple first doping type well region is positioned at the top of described Withstand voltage layer;
Multiple second doping type source region, described multiple second doping type source region is arranged in described multiple first doping type well region;
Planar gate oxygen layer, described planar gate oxygen layer is positioned on described Withstand voltage layer, and the two ends of described planar gate oxygen layer contact respectively with adjacent two described second doping type source regions;
Planar gate layer, described planar gate layer is positioned on described planar gate oxygen layer, and wherein, described planar gate layer does not cover or part covers correspondence position above described Withstand voltage layer;
Insulating medium layer, two described second doping type source regions that described insulating medium layer covers described planar gate oxygen layer, described planar gate layer and contacts with described planar gate oxygen layer;
First electrode, described first electrode is positioned on described insulating medium layer; And
Second electrode, described second electrode is positioned under described Withstand voltage layer.
2. vertical MOS power device according to claim 1, it is characterized in that, described multiple first doping type well region is contrary with the doping type of described Withstand voltage layer, described second doping type source region is identical with the doping type of described Withstand voltage layer, further, described first electrode is contrary with described second polarity of electrode.
3. a vertical MOS power device, is characterized in that, described vertical MOS power device is trench vertical MOS power device, comprising:
Withstand voltage layer;
First doping type well region, described first doping type well region is positioned at the top of described Withstand voltage layer;
Second doping type source region, described second doping type source region is arranged in the first doping type well region;
Floating well region, described floating well region is positioned at the top of described Withstand voltage layer and is positioned near described first doping type well region, and described floating well region is identical with described first doping type well region doping type;
Trench gate oxygen layer, described trench gate oxygen layer is positioned at the top of described Withstand voltage layer, the first side wall of described trench gate oxygen layer and described first doping type well region and described second doping type source contact, the second sidewall of described trench gate oxygen layer contacts with described floating well region;
Trench-gate layer, it is inner that described trench-gate layer is full of described trench gate oxygen layer, and wherein, described trench-gate layer and described trench gate oxygen layer do not cover or partly cover the upper surface of described floating well region;
Insulating medium layer, described insulating medium layer covers described planar gate oxygen layer, described planar gate layer, described floating well region and described second doping type source region;
First electrode, described first electrode is positioned on described insulating medium layer; And
Second electrode, described second electrode is positioned under described Withstand voltage layer.
4. vertical MOS power device according to claim 3, it is characterized in that, described multiple first doping type well region is contrary with the doping type of described Withstand voltage layer, described second doping type source region is identical with the doping type of described Withstand voltage layer, further, described first electrode is contrary with described second polarity of electrode.
5. a formation method for vertical MOS power device, is characterized in that, described vertical MOS power device is planar vertical MOS power device, comprises the following steps:
Withstand voltage layer is provided;
On described Withstand voltage layer, form planar gate oxygen layer, described planar gate oxygen layer comprises the first area being positioned at two ends and the second area being positioned at centre;
Planar gate layer is formed on the first area of described planar gate oxygen layer;
First doping type well region and the second doping type source region are formed on the top of the described Withstand voltage layer under the first area of described planar gate oxygen layer, wherein said second doping type source region is arranged in the first doping type well region, and the two ends of described planar gate oxygen layer contact respectively with two described second doping type source regions;
Form insulating medium layer, two described second doping type source regions that described insulating medium layer covers described planar gate oxygen layer, described planar gate layer and contacts with described planar gate oxygen layer; And
Form the first electrode and the second electrode, wherein, described first electrode is positioned on described insulating medium layer, and described second electrode is positioned under described Withstand voltage layer.
6. the formation method of vertical MOS power device according to claim 5, it is characterized in that, described multiple first doping type well region is contrary with the doping type of described Withstand voltage layer, described second doping type source region is identical with the doping type of described Withstand voltage layer, further, described first electrode is contrary with described second polarity of electrode.
7. the formation method of vertical MOS power device according to claim 5, it is characterized in that, by photoetching and injection technology, described first doping type well region and the second doping type source region are formed on the top of the described Withstand voltage layer under the first area of described planar gate oxygen layer.
8. a formation method for vertical MOS power device, is characterized in that, described vertical MOS power device is trench vertical MOS power device, comprises the following steps:
Withstand voltage layer is provided;
Form groove at described Withstand voltage layer top, then form trench gate oxygen layer at the inwall of described groove;
On described trench gate oxygen layer, form trench-gate layer, described trench-gate layer and described trench gate oxygen layer do not cover or part covers the upper surface presetting floating well region region;
First doping type well region, the second doping type source region and floating well region are formed on the top of the described Withstand voltage layer near described trench-gate layer, wherein, described second doping type source region is arranged in the first doping type well region, described first doping type well region contacts with the first side wall of described trench gate oxygen layer with described second doping type source region, the second sidewall contact of described floating well region and described trench gate oxygen layer;
Form insulating medium layer, described insulating medium layer covers described trench gate oxygen layer, trench-gate layer, the second doping type source region and floating well region; And
Form the first electrode and the second electrode, wherein, described first electrode is positioned on described insulating medium layer, and described second electrode is positioned under described Withstand voltage layer.
9. the formation method of vertical MOS power device according to claim 8, it is characterized in that, described multiple first doping type well region is contrary with the doping type of described Withstand voltage layer, described second doping type source region is identical with the doping type of described Withstand voltage layer, further, described first electrode is contrary with described second polarity of electrode.
10. the formation method of vertical MOS power device according to claim 8, it is characterized in that, by photoetching and injection technology, described first doping type well region, the second doping type source region and floating well region are formed on the top of the described Withstand voltage layer near described trench-gate layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018033034A1 (en) * | 2016-08-17 | 2018-02-22 | The Hong Kong University Of Science And Technology | Semiconductor device with hybrid channel configuration |
| CN108627753A (en) * | 2018-05-11 | 2018-10-09 | 西安交通大学 | A kind of IGBT on-line condition monitorings method and measuring system based on Miller platform time delay |
| CN114122122A (en) * | 2020-08-26 | 2022-03-01 | 比亚迪半导体股份有限公司 | Groove type semiconductor device and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02216871A (en) * | 1989-02-17 | 1990-08-29 | Fuji Electric Co Ltd | Power mosfet |
| US20020016062A1 (en) * | 2000-07-28 | 2002-02-07 | Nec Corporation | Semiconductor device with improved UMOS-structure |
| CN102386099A (en) * | 2010-08-30 | 2012-03-21 | 英飞凌科技奥地利有限公司 | Method for forming a semiconductor device, and a semiconductor with an integrated poly-diode |
| CN103222038A (en) * | 2010-11-23 | 2013-07-24 | 密克罗奇普技术公司 | Vertical FET |
| CN204067369U (en) * | 2014-06-27 | 2014-12-31 | 宁波比亚迪半导体有限公司 | Vertical mos power device |
-
2014
- 2014-06-27 CN CN201410305139.7A patent/CN105206668A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02216871A (en) * | 1989-02-17 | 1990-08-29 | Fuji Electric Co Ltd | Power mosfet |
| US20020016062A1 (en) * | 2000-07-28 | 2002-02-07 | Nec Corporation | Semiconductor device with improved UMOS-structure |
| CN102386099A (en) * | 2010-08-30 | 2012-03-21 | 英飞凌科技奥地利有限公司 | Method for forming a semiconductor device, and a semiconductor with an integrated poly-diode |
| CN103222038A (en) * | 2010-11-23 | 2013-07-24 | 密克罗奇普技术公司 | Vertical FET |
| CN204067369U (en) * | 2014-06-27 | 2014-12-31 | 宁波比亚迪半导体有限公司 | Vertical mos power device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018033034A1 (en) * | 2016-08-17 | 2018-02-22 | The Hong Kong University Of Science And Technology | Semiconductor device with hybrid channel configuration |
| CN108627753A (en) * | 2018-05-11 | 2018-10-09 | 西安交通大学 | A kind of IGBT on-line condition monitorings method and measuring system based on Miller platform time delay |
| CN114122122A (en) * | 2020-08-26 | 2022-03-01 | 比亚迪半导体股份有限公司 | Groove type semiconductor device and manufacturing method thereof |
| CN114122122B (en) * | 2020-08-26 | 2023-09-12 | 比亚迪半导体股份有限公司 | Groove type semiconductor device and manufacturing method thereof |
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Application publication date: 20151230 |