CN114122122A - Groove type semiconductor device and manufacturing method thereof - Google Patents

Groove type semiconductor device and manufacturing method thereof Download PDF

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CN114122122A
CN114122122A CN202010870367.4A CN202010870367A CN114122122A CN 114122122 A CN114122122 A CN 114122122A CN 202010870367 A CN202010870367 A CN 202010870367A CN 114122122 A CN114122122 A CN 114122122A
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trench
source
gate oxide
oxide protection
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CN114122122B (en
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杨涛涛
吴海平
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BYD Semiconductor Co Ltd
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BYD Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention belongs to the field of electric elements, and particularly relates to a trench type semiconductor device and a manufacturing method thereof. The trench type semiconductor device comprises a semiconductor substrate, a drain electrode region, a gate electrode region, a source electrode region and an insulated gate dielectric layer; the semiconductor substrate is provided with a groove, the gate electrode region is positioned in the groove, and the insulated gate dielectric layer is positioned between the gate electrode region and the semiconductor substrate; a gate oxide protection region and a first source region are formed on one side of the groove, the outer wall of one side of the groove extends to the bottom of the groove, the gate oxide protection region extends to the bottom of the groove, a first channel communicated with the first source region and the semiconductor substrate is formed at the contact position of the gate oxide protection region and the bottom of the groove, and the first channel is formed at the contact position of the gate oxide protection region and the bottom of the groove, so that the channel density of the semiconductor device is increased, the conduction internal resistance of the semiconductor device is reduced, and the device performance is improved.

Description

Groove type semiconductor device and manufacturing method thereof
Technical Field
The invention belongs to the field of electric elements, and particularly relates to a trench type semiconductor device and a manufacturing method thereof.
Background
Silicon carbide (SiC) is a new generation wide bandgap semiconductor material, and has excellent material characteristics such as a critical breakdown electric field 10 times that of silicon, high saturation drift rate, high thermal conductivity and the like, so that the performance of a power electronic device based on the SiC material is far superior to that of a Si-based material, and the SiC material has a wide application prospect particularly in high voltage and high power. The trench gate SiC MOSFET has a lower on-resistance than a planar gate, and is a development direction of SiC MOSFETs in the future. A cross-sectional structure of a conventional trench gate SiC MOSFET is shown in fig. 1i, and mainly includes a substrate region 101, an epitaxial region 102, a well region 103, a source region 104, a gate oxide protection region 105, an insulated gate dielectric layer 107, a gate electrode region 108, an insulated dielectric isolation layer 109, a source electrode region 111, and a drain electrode region 112.
As shown in fig. 1a to 1i, the manufacturing method for forming the trench gate semiconductor device includes:
s1, as shown in fig. 1a, providing a substrate region 101 of a first conductivity type and an epitaxial region 102 of the first conductivity type;
s2, as shown in fig. 1b, forming a well region 103 of the second conductivity type and a source region 104 of the first conductivity type on the epitaxial region 102 of the first conductivity type by epitaxy or ion implantation;
s3, as shown in FIG. 1c, forming a gate oxide protection region 105 of the second conductive type by selective area high temperature ion implantation;
s4, as shown in fig. 1d, dry etching to form the trench 106;
s5, as shown in fig. 1e, forming an insulated gate dielectric layer 107 inside the trench 106 by high temperature thermal oxidation;
s6, as shown in fig. 1f, depositing polysilicon in the trench to form the gate electrode region 108;
s7, as shown in figure 1g, depositing an insulating medium above the gate electrode region, removing part of the insulating medium through photoetching, and forming a source contact hole 110 and an insulating medium isolating layer 109;
s8, as shown in figure 1h, depositing a source electrode region 111 above the insulating medium isolation layer 109;
s9, as shown in fig. 1i, a drain electrode region 112 is deposited on a side of the substrate region 101 remote from the epitaxial region 102.
In the existing manufacturing method, in order to protect the gate dielectric layer, the channel on one side of the trench is sacrificed, a P-type injection layer is formed on one side of the trench through high-temperature ion injection, the trench on the other side is the (11-20) surface of the SiC, and the channel of the SiC MOSFET is formed at the joint of the second conductive type well region.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the problems of low channel density and large on-resistance of the existing trench type semiconductor device, the trench type semiconductor device and the manufacturing method thereof are provided.
In order to solve the above technical problems, in one aspect, the present invention provides a trench type semiconductor device, including a semiconductor substrate, a drain electrode region, a gate electrode region, a source electrode region, and an insulated gate dielectric layer;
the semiconductor substrate is provided with a groove, the gate electrode region is positioned in the groove, and the insulated gate dielectric layer is positioned between the gate electrode region and the semiconductor substrate;
a gate oxide protection region and a first source region are formed on one side of the trench, the semiconductor substrate and the first source region are of a first conductivity type, the gate oxide protection region is of a second conductivity type, the first source region extends to the bottom of the trench along the outer wall of one side of the trench, the gate oxide protection region is located on the periphery of the first source region, extends to the bottom of the trench and is in contact with the bottom of the trench, and a first channel communicating the first source region with the semiconductor substrate is formed at the contact position of the gate oxide protection region and the bottom of the trench;
the source electrode region is electrically coupled to the first source region, and the drain electrode region is electrically coupled to the semiconductor substrate.
Optionally, the semiconductor substrate includes a substrate region and an epitaxial region disposed on the substrate region, the substrate region is disposed on the drain electrode region, and the trench is disposed on the epitaxial region.
Optionally, the trench semiconductor device further comprises an insulating dielectric isolation layer disposed between the gate electrode region and the source electrode region.
Optionally, the insulating gate dielectric layer is formed on the inner wall of the trench and extends outwards along the inner wall of the trench into the insulating dielectric isolation layer.
Optionally, a second source region and a well region are formed on the semiconductor substrate on the other side of the trench;
the well region is of a second conductivity type and is formed on the semiconductor substrate; the second source region is of a first conductivity type, the second source region and the semiconductor substrate are separated by the well region, and the source electrode region is electrically coupled with the second source region;
and the contact position of the well region and the outer wall of the groove forms a second channel which is communicated with the second source region and the semiconductor substrate.
In another aspect, the present invention provides a method for manufacturing a trench type semiconductor device, including the steps of:
s1, forming a well region of a second conductive type and a second source region of the first conductive type on the surface of the well region on the semiconductor substrate of the first conductive type;
s2, doping a gate oxide protection region of a second conduction type on the surface of the semiconductor substrate, wherein the gate oxide protection region and the well region are arranged on the surface of the semiconductor substrate side by side;
s3, doping in the range covered by the gate oxide protection region to form a first source region of the first conductivity type in the gate oxide protection region;
s4, forming a groove by etching at the interface position of the gate oxide protection region and the second source region, wherein the bottom of the groove does not exceed the coverage area of the gate oxide protection region, and the periphery of the groove extends to the coverage area of the first source region;
s5, forming an insulated gate dielectric layer in the groove;
s6, depositing polycrystalline silicon in the groove to form a gate electrode region;
s7, forming a source electrode region on the surfaces of the second source region and the first source region;
and S8, forming a drain electrode region on the surface of the semiconductor substrate.
Optionally, before forming the source electrode region, an insulating medium is deposited over the gate electrode region, and a portion of the insulating medium is removed by photolithography etching to form a source contact hole and an insulating medium isolation layer, where the source contact hole is located on both sides of the insulating medium isolation layer.
Optionally, in step S5, the insulated gate dielectric layer is formed on the inner wall of the trench and extends outwards along the inner wall of the trench into the insulated dielectric isolation layer;
the insulated gate dielectric layer is made of silicon dioxide and has the thickness of 0.01-0.5 mu m.
Optionally, the insulating medium isolation layer is silicon dioxide or silicon nitride, and the thickness is 0.1-3 um.
Optionally, in step S1, the well region is located between the semiconductor substrate and the second source region;
the doping concentration of the well region is 1016～1018cm-3The thickness is 0.5 to 10 μm; the doping concentration of the second source region is 1018～1021cm-3The thickness is 0.2 to 5 μm.
Optionally, the first source region extends to the bottom of the trench along an outer wall of one side of the trench, the gate oxide protection region is located at the periphery of the first source region, and the gate oxide protection region extends to the bottom of the trench and contacts the bottom of the trench;
the thickness of the gate oxide protection region is 2.5-5 mu m, the thickness of the first source region is 1-2 mu m, a first channel communicated with the first source region and the semiconductor substrate is formed at the bottom of the groove by the gate oxide protection region, and the length of the first channel is 0.5-0.8 mu m.
Optionally, the doping concentration of the gate oxide protection region near the bottom region of the trench is 1017～1019cm-3The region near the source electrode region has a doping concentration of1019～1020cm-3The doping concentration of the first source region is 1018～1021cm-3。
Optionally, in step S4, the etching depth of the trench is 1 to 2 μm.
Optionally, in step S6, the polysilicon is heavily doped with a doping concentration of 1016～1021cm-3The sheet resistance of the polysilicon is less than 100 omega/□.
Optionally, the source electrode region is made of nickel-titanium-aluminum alloy and has a thickness of 1-10 μm, and the drain electrode region is made of titanium-nickel-silver alloy and has a thickness of 1-10 μm.
In the embodiment of the invention, the gate oxide protection region is located at the periphery of the first source region, the first source region with a different conductivity type from that of the gate oxide protection region is formed in the region of the gate oxide protection region, the gate oxide protection region is of the second conductivity type, the first source region is of the first conductivity type, the first source region extends to the bottom of the trench along the outer wall of one side of the trench, the first channel is formed at the position where the gate oxide protection region is in contact with the bottom of the trench, and on the basis that the gate oxide protection region can reduce the electric field intensity of a gate oxide layer and improve the reliability of a semiconductor device, the channel density of the semiconductor device is increased, the on-state internal resistance of the semiconductor device is reduced, and the device performance is improved.
Drawings
FIGS. 1a-1i are cross-sectional views of steps in a method of fabricating a trench-type semiconductor device provided in the prior art;
fig. 2a-2j are cross-sectional views of steps in a method of fabricating a trench-type semiconductor device according to an embodiment of the present invention.
The reference numerals in the specification are as follows:
101. a substrate region; 102. an epitaxial region; 103. a well region; 104. a source region; 105. a gate oxide protection region; 106. a trench; 107. an insulated gate dielectric layer; 108. a gate electrode region; 109. an insulating dielectric isolation layer; 110. a source contact hole; 111. a source electrode region; 112. a drain electrode region;
201. a substrate region; 202. an epitaxial region; 203. a well region; 204. a second source region; 205. a gate oxide protection region; 206. a first source region; 207. a trench; 208. an insulated gate dielectric layer; 209. a gate electrode region; 210. an insulating dielectric isolation layer; 211. a source contact hole; 212. a source electrode region; 213. a drain electrode region; 214. a second channel; 215. a first channel.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 2a to 2j, a trench type semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, a drain electrode region 213, a gate electrode region 209, a source electrode region 212, and an insulated gate dielectric layer 208, wherein the semiconductor substrate is formed with a trench 207, the gate electrode region 209 is located in the trench 207, the insulated gate dielectric layer 208 is located between the gate electrode region 209 and the semiconductor substrate, a gate oxide protection region 205 and a first source region 206 are formed on one side of the trench 207, the semiconductor substrate and the first source region 206 are of a first conductivity type, the gate oxide protection region 205 is of a second conductivity type, the first conductivity type is N-type, the second conductivity type is P-type or the first conductivity type is P-type, and the second conductivity type is N-type. The first source region 206 extends from the outer wall of one side of the trench 207 to the bottom of the trench 207, the gate oxide protection region 205 is located at the periphery of the first source region 206, the gate oxide protection region 205 extends to the bottom of the trench 207, a first trench 215 communicating the first source region 206 with the semiconductor substrate is formed at a position where the gate oxide protection region 205 contacts the bottom of the trench 207, the source electrode region 212 is electrically coupled with the first source region 206, and the drain electrode region 213 is electrically coupled with the semiconductor substrate.
In the prior art, the trench including the SiC (11-20) surface is etched by controlling an angle, and a relatively low on-resistance can be obtained by utilizing a relatively high channel mobility of the SiC (11-20) surface, so as to protect an insulated gate dielectric layer formed by high-temperature thermal oxidation and improve the reliability of a semiconductor device, the gate oxide protection region is formed on the semiconductor substrate by high-temperature ion implantation, and the gate oxide protection region is located on one side of the trench and extends to the bottom of the trench, so that the insulated gate dielectric layer can be effectively protected, but the channel on one side of the trench is sacrificed, the channel density of the semiconductor device is reduced, and the performance of the semiconductor device is reduced.
In the present invention, the gate oxide protection region 205 is located at the periphery of the first source region 206, the first source region 206 with a conductivity type different from that of the gate oxide protection region 205 is formed in the region of the gate oxide protection region 205, the gate oxide protection region 205 is of the second conductivity type, the first source region 206 is of the first conductivity type, the first source region 206 extends to the bottom of the trench 207 along the outer wall of one side of the trench 207, and the first channel 215 is formed at the position where the gate oxide protection region 205 contacts the bottom of the trench 207, so that the channel density of the semiconductor device is increased, the on-resistance of the semiconductor device is reduced, and the device performance is improved.
The first channel 215 communicates the first source region 206 with the semiconductor substrate, such that electrons in the first source region 206 can enter the semiconductor substrate through the first channel 215 to reach the drain electrode region 213 electrically coupled to the semiconductor substrate.
In one embodiment, the semiconductor substrate comprises a substrate region 201 and an epitaxial region 202 disposed on the substrate region 201, the substrate region 201 and the epitaxial region 202 are both of a first conductivity type, the substrate region 201 is disposed on the drain electrode region 213, the trench 207 is disposed on the epitaxial region 202, and the gate oxide protection region 205 is formed by high temperature ion implantation on the epitaxial region 202.
In an embodiment, the trench type semiconductor device further comprises an insulating dielectric isolation layer 210, the insulating dielectric isolation layer 210 is disposed between the gate electrode region 209 and the source electrode region 212 to realize electrical insulation between the gate electrode region 209 and the source electrode region 212, an active electrode contact hole 211 is formed at two sides of the insulating dielectric isolation layer 210, and the source electrode region 212 is electrically coupled with the first source region 206 via the source contact hole 211.
In one embodiment, the insulated gate dielectric layer 208 is formed on the inner wall of the trench 207 and extends horizontally outward along the inner wall of the trench 207 into the insulated dielectric isolation layer 210. The insulated gate dielectric layer 208 has an insulating function, and realizes electrical insulation between the gate electrode region 209 in the trench 207 and the gate oxide protection region 205 and the first source region 206 on one side of the trench 207.
In an embodiment, a second source region 204 and a well region 203 are formed on the other side of the trench 207, and the well region 203 is of a second conductivity type and is formed on the epitaxial region 202 of the semiconductor substrate; the second source region 204 is of a first conductivity type, the first conductivity type is N-type, the second conductivity type is P-type or the first conductivity type is P-type, the second conductivity type is N-type. The second source region 204 and the epitaxial region 202 of the semiconductor substrate are separated by the well region 203, the source electrode region 212 is electrically coupled to the second source region 204, a contact position of the well region 203 with an outer wall of the trench 207 forms a second channel 214 communicating the second source region 204 with the semiconductor substrate, and the second channel 214 communicates the second source region 204 and the epitaxial region 202, so that electrons in the second source region 204 flow to the semiconductor substrate.
The trench 207 includes a SiC (11-20) plane, the second channel 214 is a SiC (11-20) plane as a channel of the semiconductor device, and the bottom of the trench 207 does not have a (11-20) plane, so that the second channel 214 has higher channel mobility than the first channel 215 at the bottom of the trench 207, the second channel 214 serves as a main channel of the semiconductor device, and the first channel 215 serves as an auxiliary channel to increase channel density of the semiconductor device on the basis that the gate oxide protection region 205 can reduce electric field intensity of a gate oxide layer.
An embodiment of the present invention further provides a method for manufacturing a trench type semiconductor device, including the steps of:
s1, forming a well region 203 of a second conductivity type and a second source region 204 of the first conductivity type on the surface of the well region 203 on the semiconductor substrate of the first conductivity type;
s2, doping a gate oxide protection region 205 of a second conductivity type on the surface of the semiconductor substrate, wherein the gate oxide protection region 205 and the well region 203 are arranged on the surface of the semiconductor substrate side by side;
s3, doping the inside of the area covered by the gate oxide protection region 205 to form a first source region 206 of the first conductivity type inside the gate oxide protection region 205;
s4, forming a trench 207 at the intersection of the gate oxide protection region 205 and the second source region 204 by etching, wherein the bottom of the trench 207 does not exceed the coverage area of the gate oxide protection region 205, and the periphery of the trench 207 extends to the coverage area of the first source region 206;
s5, forming an insulated gate dielectric layer 208 in the groove 207;
s6, depositing polysilicon in the trench 207 to form a gate electrode region 209;
s7, forming source electrode regions 212 on the surfaces of the second source region 204 and the first source region 206;
and S8, forming a drain electrode region 213 on the surface of the semiconductor substrate.
In this embodiment, after the first source region 206 is formed by high-temperature ion implantation in a selected region in the gate oxide protection region 205, etching is performed at the boundary position between the gate oxide protection region 205 and the second source region 204, the trench 207 including SiC (11-20) surfaces is etched by controlling a certain angle, one side of the trench 207 is the gate oxide protection region 205 and the first source region 206, both the gate oxide protection region 205 and the first source region 206 extend to the bottom of the trench 207, and the first trench 215 is formed at a position where the gate oxide protection region 205 contacts the bottom of the trench 207. The well region 203 and the second source region 204 are disposed on the other side of the trench 207, and the second trench 214 is formed at a contact position between the well region 203 and the outer wall of the trench 207, so that after the first source region 206 is formed in the gate oxide protection region 205, the insulating gate dielectric layer 208 formed by high-temperature thermal oxidation is protected, the reliability of the semiconductor device is improved, the channel density of the semiconductor device can be increased, and the on-resistance of the semiconductor device is reduced.
In an embodiment, an insulating dielectric isolation layer 210 is provided between the gate electrode region 209 and the source electrode region 212, enabling electrical isolation between the gate electrode region 209 and the source electrode region 212. Specifically, before the source electrode region 212 is formed, an insulating medium is deposited above the gate electrode region 209, and part of the insulating medium is removed by photoetching to form a source contact hole 211 and an insulating medium isolation layer 210, wherein the source contact hole 211 is positioned at two sides of the insulating medium isolation layer 210.
In an embodiment, as shown in fig. 2a, the semiconductor substrate includes a substrate region 201 and an epitaxial region 202 disposed on the substrate region 201, and an epitaxial parameter of the epitaxial region 202 is related to a withstand voltage requirement of the semiconductor device. Generally, the higher the withstand voltage requirement, the lower the epitaxial doping concentration and the thicker the epitaxial thickness, and the doping concentration of the epitaxial region 202 is 1015～1017cm-3The thickness is 10-100 μm, and preferably, the thickness of the epitaxial region 202 is 10-50 μm.
Epitaxy is known to mean the growth of a layer of single crystal material on a single crystal substrate region, which has the same lattice arrangement as the substrate region, and the epitaxial layer may be a homoepitaxial layer or a heteroepitaxial layer. There are many methods for implementing epitaxial growth, including molecular beam epitaxy, ultra-high vacuum chemical vapor deposition, atmospheric and reduced pressure epitaxy, etc., and conventional operations and methods in the art are used for implementing epitaxy, which are not described herein again.
In one embodiment, as shown in fig. 2b, the specific operation of step S1 is to form the well region 203 on the epitaxial region 202 of the semiconductor substrate by epitaxy or ion implantation, form the second source region 204 on the surface of the well region 203 by epitaxy or ion implantation, and position the well region 203 between the epitaxial region 202 and the second source region 204. The doping concentration of the well region 203 is 1016～1018cm-3Thickness of0.5-10 μm, preferably, the thickness of the well region 203 is 0.5-0.8 μm; the doping concentration of the second source region 204 is 1018～1021cm-3The thickness is 0.2 to 5 μm.
The basic principle of ion implantation is: the ion beam with a certain magnitude is incident into the epitaxial region 202, and a series of physical and chemical interactions between the ion beam and atoms or molecules in the epitaxial region 202 occur, so that the incident ions gradually lose energy and finally stay in the epitaxial region 202, and the surface composition, structure and performance of the epitaxial region 202 are changed, thereby optimizing the performance or obtaining some new excellent performance. Methods and operations for ion implantation are well known in the art and will not be described in detail herein.
In an embodiment, the specific operation of step S2 is to form a selection region by photo development on the basis of the semiconductor device obtained in step S1, form the gate oxide protection region 205 by multiple ion implantations, wherein the lower surface of the gate oxide protection region 205 extends into the extension region, the thickness of the gate oxide protection region 205 is 2.5 to 5 μm, and as shown in fig. 2c, the gate oxide protection region 205 and the well region 203 and the second source region 204 doped in step S1 are juxtaposed on the semiconductor substrate.
In an embodiment, the specific operation of step S3 is to form a selective area in the area covered by the gate oxide protection region 205 by photo development, form the first source region 206 in the selective area by ion implantation, as shown in fig. 2d, the area covered by the first source region 206 does not exceed the area covered by the gate oxide protection region 205, the thickness of the first source region 206 is 1-2 μm, and after doping the first source region 206, the gate oxide protection region 205 is located at the periphery of the first source region 206.
In an embodiment, the doping concentration in the gate oxide protection region 205 decreases from top to bottom, and the doping concentration of the region of the gate oxide protection region 205 near the bottom of the trench 207 (i.e. the lower region of the gate oxide protection region 205) is 1017～1019cm-3The region near the source electrode region 212 (i.e., the gate oxide)Upper region of protection region 205) has a doping concentration of 1019～1020cm-3The doping concentration of the first source region 206 is 1018～1021cm-3。
In an embodiment, the specific operation of step S4 is to form a selective region at the intersection of the gate oxide protection region 205 and the second source region 204 by photo development, and perform dry etching at a controlled angle to form the trench 207 including SiC (11-20) surface, as shown in fig. 2e, the bottom of the trench 207 does not exceed the coverage area of the gate oxide protection region 205, the first source region 206 extends from the outer wall of one side of the trench 207 to the bottom of the trench 207, the gate oxide protection region 205 is located at the outer periphery of the first source region 206, and the gate oxide protection region 205 extends to the bottom of the trench 207.
In an embodiment, the thickness of the gate oxide protection region 205 is 2.5 to 5 μm, the thickness of the first source region 206 is 1 to 2 μm, the gate oxide protection region 205 forms a first trench 215 communicating the first source region 206 and the semiconductor substrate at the bottom of the trench 207, and the length of the first trench 215 is 0.5 to 0.8 μm.
As shown in fig. 2e, a vertical line perpendicular to the bottom of the trench 207 is made, the angle between the vertical line and the side surface of the trench 207 is α, 0 < α < 15 °, and when 0 < α < 15 °, the trench 207 including SiC (11-20) surface can be obtained, and in SiC crystal, the SiC (11-20) surface has higher channel mobility and lower on-resistance can be obtained. Preferably 0 < α < 10 °, further preferably 2 < α < 8 °.
In one embodiment, the etching depth of the trench 207 is 1 to 2 μm.
In one embodiment, step S5 is specifically performed by performing a high temperature thermal oxidation on the semiconductor device after the trench 207 is etched, and forming the insulated gate dielectric layer 208 on the inner wall of the trench 207 by the high temperature thermal oxidation, and at the same time, the insulated gate dielectric layer 208 is also formed on the second source region 204 on one side outside the trench 207 and the first source region 206 on the other side outside the trench 207, as shown in fig. 2f, where the insulated gate dielectric layer 208 extends outward along the inner wall of the trench 207 to the edge of the semiconductor device.
In one embodiment, the insulated gate dielectric layer 208 is silicon dioxide and has a thickness of 0.01 to 0.5 μm.
In an embodiment, step S6 is specifically performed such that after the insulated gate dielectric layer 208 is formed in the trench 207, polysilicon needs to be deposited in the trench 207 and also formed on the surface of the insulated gate dielectric layer 208 outside the trench 207, and then a dry plasma etching process needs to be used to pattern the polysilicon to remove the polysilicon on the surface of the insulated gate dielectric layer 208, as shown in fig. 2g, the gate electrode region 209 is formed by the polysilicon remaining in the trench 207. The insulating gate dielectric layer 208 is located between the gate electrode region 209 and the semiconductor substrate for insulation.
In one embodiment, the polysilicon is typically heavily doped with a doping concentration of 1016～1021cm-3The sheet resistance of polysilicon is less than 100 Ω/□ (ohms per square).
In one embodiment, an insulating dielectric is deposited over the gate electrode region 209 after the gate electrode region 209 is formed and before the source electrode region 212 is formed, while an insulating dielectric is deposited on the insulating gate dielectric layer 208 at the surface of the semiconductor device. As shown in fig. 2h, after removing a portion of the insulating dielectric and the insulating gate dielectric layer 208 under the portion of the insulating dielectric by photolithography etching, a source contact hole 211 and an insulating dielectric isolation layer 210 are formed.
The source contact holes 211 are located on two sides of the insulating medium isolation layer 210, the source contact holes 211 are actually areas where insulating media are etched away, and the insulating medium isolation layer 210 is used for realizing electrical insulation between the gate electrode region 209 and the source electrode region 212 and avoiding short circuit of the gate electrode region 209 and the source electrode region 212.
In one embodiment, the insulating dielectric isolation layer 210 is silicon dioxide or silicon nitride, and has a thickness of 0.1-3 um.
In one embodiment, the source electrode region 212 is a nickel-titanium-aluminum alloy with a thickness of 1-10 μm, and the drain electrode region 213 is a titanium-nickel-silver alloy with a thickness of 1-10 μm.
In one embodiment, as shown in fig. 2i, step S7 is specifically performed by sputtering a nitinol target to obtain nitinol particles, and depositing the nitinol particles on the surfaces of the second source region 204 and the first source region 206 to form the source electrode region 212.
Step S8 is specifically performed by sputtering a titanium-nickel-silver alloy target material to obtain titanium-nickel-silver alloy particles, and as shown in fig. 2j, the titanium-nickel-silver alloy particles are deposited on the surface of the semiconductor substrate to form the drain region 213.
The present invention will be further illustrated by the following examples.
Example 1
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1015～1017cm-3The thickness is 10 to 100 μm;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1016～1018cm-3The thickness is 0.5 to 10 μm, and the doping concentration of the second N + source region is 1018～1021cm-3The thickness is 0.2 to 5 μm;
s3, forming a selective area by illumination development, forming a P-type gate oxide protection area 205 through multiple times of ion implantation, wherein the thickness is 2.5-5 mu m, and the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1017～1019cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1019～1020cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation, wherein the thickness is 1-2 μm, and the doping concentration is 1018～1021cm-3；
S5, forming a selection area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1-2 μm, and the length of a transverse first channel 215 at the bottom of the groove 207 is 0.5-0.8 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.01-0.5 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, removing a part of insulating medium and the insulating gate medium layer 208 below the part of insulating medium through photoetching, and forming a source contact hole 211 and an insulating medium isolating layer 210, wherein the thickness of the insulating medium isolating layer 210 is 0.1-3 um;
s9, depositing to form a source electrode area 212 with the thickness of 1-10 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 1-10 μm.
Example 2
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1015cm-3The thickness is 10 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1016cm-3The thickness is 0.5 μm, and the doping concentration of the second N + source region is 1018cm-3The thickness is 0.2 mu m;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 2.5 μm by multiple times of ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1017cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1019cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation with a thickness of 1 μm and a doping concentration of 1018cm-3；
S5, forming a selection area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.5 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.01 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 0.1 um;
s9, depositing to form a source electrode region 212 with the thickness of 1 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 1 μm.
Example 3
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1017cm-3The thickness is 100 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1018cm-3The thickness is 10 μm, and the doping concentration of the second N + source region is 1021cm-3A thickness of5μm；
S3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 5 μm by multiple times of ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1019cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1020cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation with a thickness of 2 μm and a doping concentration of 1021cm-3；
S5, forming a selection area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 2 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.8 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.5 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, removing a part of insulating medium and the insulating gate medium layer 208 below the part of insulating medium by photoetching, and forming a source contact hole 211 and an insulating medium isolating layer 210, wherein the thickness of the insulating medium isolating layer 210 is 3 um;
s9, depositing to form a source electrode region 212 with the thickness of 10 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 10 μm.
Example 4
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1016cm-3The thickness is 55 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 by epitaxy or ion implantationA second N + source region is formed on the surface of the P-type well region 203 by epitaxy or ion implantation, and the doping concentration of the P-type well region 203 is 1017cm-3The thickness is 5 μm, and the doping concentration of the second N + source region is 1019cm-3The thickness is 2.5 mu m;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 3.6 μm by multiple ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1018cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1019cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation with a thickness of 1.5 μm and a doping concentration of 1020cm-3；
S5, forming a selective area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1.5 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.6 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.3 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 1.5 um;
s9, depositing to form a source electrode region 212 with the thickness of 5 μm;
s10, depositing to form drain electrode region 213 with thickness of 5 μm.
Example 5
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N typeAnd an epitaxial region 202 of N-type, said epitaxial region 202 having a doping concentration of 1015cm-3The thickness is 60 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1017cm-3The thickness is 4 μm, and the doping concentration of the second N + source region is 1020cm-3The thickness is 4 mu m;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 4 μm by multiple times of ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1019cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1020cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation, wherein the thickness is 1.8 μm, and the doping concentration is 1019cm-3；
S5, forming a selective area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1.8 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.7 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.1 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 0.5 um;
s9, depositing to form a source electrode region 212 with the thickness of 8 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 6 μm.
Example 6
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1017cm-3The thickness is 20 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1018cm-3The thickness is 6 μm, and the doping concentration of the second N + source region is 1020cm-3The thickness is 3 mu m;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 4.5 μm by multiple ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1018cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1020cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation with a thickness of 1 μm and a doping concentration of 1021cm-3；
S5, forming a selection area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 2 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.8 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.05 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 2 um;
s9, depositing to form a source electrode region 212 with the thickness of 2 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 4 μm.
Example 7
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1016cm-3The thickness is 30 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1016cm-3The thickness is 8 μm, and the doping concentration of the second N + source region is 1021cm-3The thickness is 3.5 mu m;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 3 μm by multiple times of ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1017cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1019cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation, wherein the thickness is 1.6 μm, and the doping concentration is 1018cm-3；
S5, forming a selective area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1.3 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.5 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.4 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 1 um;
s9, depositing to form a source electrode region 212 with the thickness of 3 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 7 μm.
Example 8
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1015cm-3The thickness is 50 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1016cm-3The thickness is 2 μm, and the doping concentration of the second N + source region is 1019cm-3The thickness is 1 μm;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 2.5 μm by multiple times of ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1018cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1020cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation, wherein the thickness is 1.4 μm, and the doping concentration is 1020cm-3；
S5, forming a selective area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1.6 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.6 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.35 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 1.8 um;
s9, depositing to form a source electrode region 212 with the thickness of 9 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 3 μm.
Example 9
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1017cm-3The thickness is 80 μm;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1017cm-3The thickness is 3 μm, and the doping concentration of the second N + source region is 1018cm-3The thickness is 0.5 mu m;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 4.8 μm by multiple ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1019cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1019cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation with a thickness of 2 μm and a doping concentration of 1021cm-3；
S5, forming a selective area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1.4 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.8 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.45 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 1.6 um;
s9, depositing to form a source electrode region 212 with the thickness of 4 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 2 μm.
Example 10
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1016cm-3The thickness is 90 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1017cm-3The thickness is 9 μm, and the doping concentration of the second N + source region is 1019cm-3The thickness is 2 mu m;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 2.8 μm by multiple times of ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1017cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1019cm-3；
S4, selecting in the gate oxide protection region 205A region formed by ion implantation to have a thickness of 1.3 μm and a doping concentration of 1019cm-3；
S5, forming a selective area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1.3 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.7 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.5 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 1.2 um;
s9, depositing to form a source electrode region 212 with the thickness of 6 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 4 μm.
Example 11
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1016cm-3The thickness is 40 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1018cm-3The thickness is 1 μm, and the doping concentration of the second N + source region is 1020cm-3The thickness is 4.5 mu m;
s3, forming a selective area by illumination development, forming a P-type gate oxide protection area 205 with a thickness of 3.2 μm by multiple times of ion implantation, wherein the P-type gate oxide protection area 205 has a doping concentration of 1017cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1019cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation, wherein the thickness is 1.1 μm, and the doping concentration is 1018cm-3；
S5, forming a selective area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1.7 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.5 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.08 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 2.6 um;
s9, depositing to form a source electrode region 212 with the thickness of 7 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 2 μm.
Example 12
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1017cm-3The thickness is 70 mu m;
s2, forming a P-type well region 203 on the epitaxial region 202 through epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 through epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1018cm-3The thickness is 7 μm, and the second N + source region is dopedImpurity concentration of 1021cm-3The thickness is 1.5 mu m;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 3.4 μm by multiple ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1019cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1020cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation with a thickness of 1.2 μm and a doping concentration of 1020cm-3；
S5, forming a selective area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 1.9 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.6 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.2 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 2.8 um;
s9, depositing to form a source electrode region 212 with the thickness of 4 μm;
s10, forming a drain electrode region 213 by deposition, and the thickness is 8 μm.
Example 13
In this embodiment, the first conductive type is N-type, and the second conductive type is P-type.
S1, providing a substrate region 201 of N type and an epitaxial region 202 of N type, wherein the doping concentration of the epitaxial region 202 is 1015cm-3The thickness is 35 mu m;
s2, on the epitaxial region 202Forming a P-type well region 203 by epitaxy or ion implantation, forming a second N + source region on the surface of the well region 203 by epitaxy or ion implantation, wherein the doping concentration of the P-type well region 203 is 1016cm-3The thickness is 5.5 μm, and the doping concentration of the second N + source region is 1018cm-3The thickness is 5 mu m;
s3, forming a selective area by photo-development, forming a P-type gate oxide protection area 205 with a thickness of 2.6 μm by multiple times of ion implantation, wherein the doping concentration of the lower area of the P-type gate oxide protection area 205 is 1018cm-3The doping concentration of the upper region of the P-type gate oxide protection region 205 is 1020cm-3；
S4, selecting a region in the gate oxide protection region 205, and forming the first N + source region by ion implantation with a thickness of 1.5 μm and a doping concentration of 1019cm-3；
S5, forming a selection area at the junction position of the P-type gate oxide protection area 205 and the second N + source area through illumination development, controlling the angle to perform dry etching to form a groove 207, wherein the etching depth of the groove 207 is 2 μm, and the length of the transverse first channel 215 at the bottom of the groove 207 is 0.7 μm;
s6, forming an insulated gate dielectric layer 208 on the inner wall of the groove 207 through high-temperature thermal oxidation, wherein the thickness of the insulated gate dielectric layer is 0.25 mu m;
s7, depositing polycrystalline silicon, etching the polycrystalline silicon on the surface of the semiconductor device in a patterning mode, and forming a gate electrode region 209 by the polycrystalline silicon reserved in the groove 207;
s8, depositing an insulating medium, and forming a source contact hole 211 and an insulating medium isolating layer 210 after removing part of the insulating medium and the insulating gate medium layer 208 below the part of the insulating medium by photoetching, wherein the thickness of the insulating medium isolating layer 210 is 2.5 um;
s9, depositing to form a source electrode region 212 with the thickness of 8 μm;
s10, depositing to form a drain electrode region 213 with a thickness of 9 μm.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (15)

1. A trench type semiconductor device is characterized by comprising a semiconductor substrate, a drain electrode region, a gate electrode region, a source electrode region and an insulated gate dielectric layer;
the semiconductor substrate is provided with a groove, the gate electrode region is positioned in the groove, and the insulated gate dielectric layer is positioned between the gate electrode region and the semiconductor substrate;
a gate oxide protection region and a first source region are formed on one side of the trench, the semiconductor substrate and the first source region are of a first conductivity type, the gate oxide protection region is of a second conductivity type, the first source region extends to the bottom of the trench along the outer wall of one side of the trench, the gate oxide protection region is located on the periphery of the first source region, extends to the bottom of the trench and is in contact with the bottom of the trench, and a first channel communicating the first source region with the semiconductor substrate is formed at the contact position of the gate oxide protection region and the bottom of the trench;
the source electrode region is electrically coupled to the first source region, and the drain electrode region is electrically coupled to the semiconductor substrate.
2. The trench semiconductor device of claim 1 wherein the semiconductor substrate comprises a substrate region and an epitaxial region disposed on the substrate region, the substrate region being disposed on the drain region, the trench being disposed on the epitaxial region.
3. The trench semiconductor device of claim 1 further comprising an insulating dielectric isolation layer disposed between the gate electrode region and the source electrode region.
4. The trench semiconductor device of claim 3 wherein the insulating gate dielectric layer is formed on the inner walls of the trench and extends outwardly along the inner walls of the trench into the insulating dielectric isolation layer.
5. The trench semiconductor device of claim 1 wherein a second source region and well region are formed on the semiconductor substrate on the other side of the trench;
the well region is of a second conductivity type and is formed on the semiconductor substrate; the second source region is of a first conductivity type, the second source region and the semiconductor substrate are separated by the well region, and the source electrode region is electrically coupled with the second source region;
and the contact position of the well region and the outer wall of the groove forms a second channel which is communicated with the second source region and the semiconductor substrate.
6. The method for manufacturing a trench type semiconductor device according to any one of claims 1 to 5, comprising the steps of:
s1, forming a well region of a second conductive type and a second source region of the first conductive type on the surface of the well region on the semiconductor substrate of the first conductive type;
s2, doping a gate oxide protection region of a second conduction type on the surface of the semiconductor substrate, wherein the gate oxide protection region and the well region are arranged on the surface of the semiconductor substrate side by side;
s3, doping in the range covered by the gate oxide protection region to form a first source region of the first conductivity type in the gate oxide protection region;
s4, forming a groove by etching at the interface position of the gate oxide protection region and the second source region, wherein the bottom of the groove does not exceed the coverage area of the gate oxide protection region, and the periphery of the groove extends to the coverage area of the first source region;
s5, forming an insulated gate dielectric layer in the groove;
s6, depositing polycrystalline silicon in the groove to form a gate electrode region;
s7, forming a source electrode region on the surfaces of the second source region and the first source region;
and S8, forming a drain electrode region on the surface of the semiconductor substrate.
7. The method of claim 6, wherein prior to forming said source electrode region, an insulating dielectric is deposited over said gate electrode region, and a portion of said insulating dielectric is removed by photolithographic etching to form a source contact opening and an insulating dielectric spacer layer, said source contact opening being located on either side of said insulating dielectric spacer layer.
8. The method of manufacturing a trench semiconductor device according to claim 7, wherein in step S5, the insulating gate dielectric layer is formed on the inner wall of the trench and extends outwardly along the inner wall of the trench into the insulating dielectric isolation layer;
the insulated gate dielectric layer is made of silicon dioxide and has the thickness of 0.01-0.5 mu m.
9. The method of claim 7, wherein the insulating dielectric isolation layer is silicon dioxide or silicon nitride and has a thickness of 0.1-3 μm.
10. The method of manufacturing a trench semiconductor device according to claim 6, wherein in step S1, the well region is located between the semiconductor substrate and the second source region;
the doping concentration of the well region is 1016～1018cm-3The thickness is 0.5 to 10 μm; the doping concentration of the second source region is 1018～1021cm-3The thickness is 0.2 to 5 μm.
11. The method of manufacturing a trench semiconductor device according to claim 6, wherein the first source region extends to the bottom of the trench along an outer wall of one side of the trench, the gate oxide protection region is located at the periphery of the first source region, and the gate oxide protection region extends to and contacts the bottom of the trench;
the thickness of the gate oxide protection region is 2.5-5 mu m, the thickness of the first source region is 1-2 mu m, a first channel communicated with the first source region and the semiconductor substrate is formed at the bottom of the groove by the gate oxide protection region, and the length of the first channel is 0.5-0.8 mu m.
12. The method of claim 11 wherein said gate oxide protection region has a doping concentration of 10 in a region near the bottom of said trench17～1019cm-3The region close to the source electrode region has a doping concentration of 1019～1020cm-3The doping concentration of the first source region is 1018～1021cm-3。
13. The method for manufacturing a trench type semiconductor device according to claim 6, wherein in the step S4, the etching depth of the trench is 1 to 2 μm.
14. The method of manufacturing a trench semiconductor device according to claim 6 wherein in step S6, the polysilicon is heavily doped with a doping concentration of 1016～1021cm-3The sheet resistance of the polysilicon is less than 100 omega/□.
15. The method for manufacturing a trench semiconductor device according to claim 6, wherein the source electrode region is NiTi-Al alloy with a thickness of 1-10 μm, and the drain electrode region is Ti-Ni-Ag alloy with a thickness of 1-10 μm.
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US6198127B1 (en) * 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
US20130001592A1 (en) * 2011-06-29 2013-01-03 Toyota Jidosha Kabushiki Kaisha Silicon carbide semiconductor device
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