JP6539026B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same.

  Conventionally, as a diode having a groove structure, one having a second conductivity type region formed on the entire bottom of the groove is known (Patent Document 1). With this structure, the semiconductor device of Patent Document 1 can improve the withstand voltage at the time of reverse voltage application, and reverse the electric field concentrated at the corner of the groove by relaxing the depletion layer from the second conductivity type region. Leakage current can be suppressed.

Japanese Patent Application Publication No. 2007-128926

  However, in the structure of Patent Document 1, since the second conductivity type region is formed at the bottom of the groove, a depletion layer is formed in the low concentration first conductivity type semiconductor layer, and the impurity concentration of the first conductivity type semiconductor layer Is low, the depletion layer will expand. Therefore, when the forward current flows, there is a problem that the current path becomes narrow due to the spread of the depletion layer.

  The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device capable of suppressing the spread of a depletion layer and increasing a forward current, and a method of manufacturing the same.

A semiconductor device according to one aspect of the present invention includes a drift region of a first conductivity type, a groove formed from a main surface of the drift region toward a junction surface between the semiconductor substrate and the drift region, and at least the inside of the groove. And an electric field relaxation region of the second conductivity type formed to be in contact with the anode electrode so as to cover the bottom of the groove, and an electric field relaxation region and a drift region. And a depletion layer diffusion preventing region including a first conductivity type impurity having a concentration higher than that of the drift region.

  According to the present invention, the spread of the depletion layer can be suppressed and the forward current can be increased.

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 2A is a cross-sectional view showing the operation (during reverse voltage application) of the semiconductor device 100 according to the first embodiment of the present invention. FIG. 2B is a cross-sectional view showing the operation (at the time of forward voltage application) of the semiconductor device 100 according to the first embodiment of the present invention. FIG. 3A is a graph showing the relationship between the forward voltage and the forward current. FIG. 3B is a graph showing the relationship between the reverse voltage and the reverse current. FIG. 4A shows the distribution of the depletion layer 14 when a forward voltage of 3 V is applied when the depletion layer diffusion preventing region 6 is not formed. FIG. 4B is a view showing the distribution of the depletion layer 14 when the forward voltage 3 V is applied when the depletion layer diffusion preventing region 6 is formed. FIG. 5A is a process sectional view showing a method of manufacturing the semiconductor device 100 shown in FIG. 1 and a view showing a state in which the drift region 2 is formed on the semiconductor substrate 1. FIG. 5B is a cross-sectional view showing the method of manufacturing the semiconductor device 100 shown in FIG. 1, in which the insulating film mask 3 is formed on the main surface of the drift region 2. FIG. 5C is a cross-sectional view showing the method of manufacturing the semiconductor device 100 shown in FIG. 1, in which the groove 4 is formed on the main surface of the drift region 2. FIG. 5D is a cross-sectional view showing the method of manufacturing the semiconductor device 100 shown in FIG. 1, in which the corner of the groove 4 is formed round. FIG. 5E is a process sectional view showing a method of manufacturing the semiconductor device 100 shown in FIG. 1 and a view showing a state in which the depletion layer diffusion preventing region 6 and the electric field relaxation region 7 are formed inside the groove 4. FIG. 5F is a cross-sectional view showing the method of manufacturing the semiconductor device 100 shown in FIG. 1, in which the side surface of the groove 4 is etched. FIG. 5G is a process sectional view showing a method of manufacturing the semiconductor device 100 shown in FIG. 1, in which the anode electrode 9 is formed on the main surface of the drift region 2 and the cathode electrode 10 is formed on the back surface of the semiconductor substrate 1. FIG. FIG. 6 is a cross-sectional view showing a structure of a first modified example of the semiconductor device 100 according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing a structure of a second modified example of the semiconductor device 100 according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view showing the structure of a semiconductor device 200 according to the second embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same parts will be denoted by the same reference numerals and the description thereof will be omitted. In the following description, the symbols + and-indicate whether the introduced impurity density is high or low. In the present embodiment, the N type is described as the first conductivity type, and the P type is described as the second conductivity type. However, the P type may be the first conductivity type and the N type may be the second conductivity type.

First Embodiment
[Configuration of Semiconductor Device]
The configuration of the semiconductor device 100 according to the first embodiment of the present invention will be described with reference to FIG. On a main surface of a semiconductor substrate 1 which is an N-type high concentration (N + -type) silicon carbide substrate, a drift region 2 which is an N-type low-concentration (N--type) SiC layer is formed. A groove 4 is selectively formed from the main surface of the drift region 2 (the main surface opposite to the main surface in contact with the semiconductor substrate 1) toward the inside of the drift region 2. Also, the corner of the groove 4 is formed round.

  An anode electrode 9 is formed to fill the grooves 4 and to connect the adjacent grooves 4 to each other. The material of the anode electrode 9 is preferably a material in which P-type impurities are added to polycrystalline silicon which forms a heterojunction with the drift region 2 or a metal material which makes a Schottky junction with the drift region 2.

  A P-type electric field relaxation region 7 is formed to cover the bottom of the groove 4. In other words, the electric field relaxation region 7 is formed in contact with the anode electrode 9 at the bottom of the groove 4. A depletion layer diffusion preventing region 6 including an N-type impurity having a concentration higher than that of the drift region 2 is formed to cover the electric field relaxation region 7. In other words, depletion layer diffusion preventing region 6 is formed between electric field relaxation region 7 and drift region 2 so that electric field relaxation region 7 does not contact drift region 2, and is formed to be in contact with trench 4. There is.

  A cathode electrode 10 which forms an ohmic junction with the semiconductor substrate 1 is formed on the back surface opposite to the main surface of the semiconductor substrate 1.

[Operation of semiconductor device]
Next, the basic operation of the semiconductor device 100 shown in FIG. 1 will be described with reference to FIGS. 2 (a) and 2 (b).

First, reverse voltage characteristics of the semiconductor device 100 will be described with reference to FIG.
When a positive voltage is applied to the cathode electrode 10 with the anode electrode 9 as a reference, the barrier between the drift region 2 and the anode electrode 9 is blocked and electrons on the anode electrode 9 side do not move to the cathode electrode 10 side. Not flowing. However, a reverse leakage current flows from the cathode electrode 10 to the anode electrode 9 from the point where the electric field concentration occurs. In the case of a grooved diode, an electric field is concentrated at the corner of the groove 4 and reverse leakage current flows, but in the structure of the first embodiment, the depletion layer 11 is formed from the electric field relaxation region 7 formed to cover the bottom of the groove 4. And the electric field at the corners of the groove 4 is relaxed. Thereby, the reverse leakage current from the corner of the groove 4 is suppressed.

Subsequently, referring to FIG. 2B, forward voltage characteristics of the semiconductor device 100 will be described.
When a negative voltage is applied to the cathode electrode 10 based on the anode electrode 9, electrons on the drift region 2 side move to the anode electrode 9 side, and a forward current 13 flows from the anode electrode 9 to the cathode electrode 10. At this time, although the depletion layer 12 from the electric field relaxation region 7 remains due to the band bending due to the PN junction at the bottom of the groove 4, the depletion layer diffusion preventing region 6 suppresses the diffusion of the depletion layer 12, A large forward current 13 can flow.

  Next, with reference to FIGS. 3A and 3B, simulation results of current-voltage characteristics in the case where the depletion layer diffusion preventing region 6 is formed and in the case where it is not formed will be described. In FIG. 3A and FIG. 3B, the horizontal axis indicates voltage (V) and the vertical axis indicates current (A / cm 2). The solid line shows the simulation result when the depletion layer diffusion preventing area 6 is formed, and the dotted line shows the simulation result when the depletion layer diffusion preventing area 6 is not formed. The simulation results shown in FIGS. 3 (a) and 3 (b) illustrate calculation results by the device simulation apparatus T-CAD manufactured by SYNOPSYS.

  As apparent from FIGS. 3 (a) and 3 (b), it can be seen that, by forming the depletion layer diffusion preventing region 6, the forward current is increased while the reverse current is suppressed.

  Next, with reference to FIGS. 4A and 4B, the distribution of the depletion layer 14 when the forward voltage 3 V is applied in the case where the depletion layer diffusion preventing region 6 is formed and in the case where it is not formed will be described. Do. As shown in FIG. 4A, when the depletion layer diffusion preventing region 6 is not formed, it can be seen that the depletion layer 14 spreads from the electric field relaxation region 7 and the path through which the forward current flows becomes narrow. On the other hand, when the depletion layer diffusion preventing region 6 is formed as shown in FIG. 4B, the depletion layer diffusion preventing region 6 suppresses the spread of the depletion layer 14 and the path through which the forward current flows becomes wider. I understand that.

[Method of Manufacturing Semiconductor Device]
Next, a method of manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 5A to 5G.

  First, as shown in FIG. 5A, a drift region 2 composed of an N-type low concentration silicon carbide epitaxial layer is formed on the main surface of a semiconductor substrate 1 which is an N + -type silicon carbide substrate.

  Next, as shown in FIG. 5B, an insulating film is formed on the main surface of drift region 2 and this insulating film is patterned to selectively insulate the insulating film above the portion where groove 4 is to be formed. A film mask 3 (hard mask) is formed. A common photolithography technique can be used for the patterning of the insulating film. The insulating film is etched using the photoresist film patterned on the insulating film as a mask. As an etching method, dry etching such as reactive ion etching can be used. After patterning the insulating film, the photoresist film is removed using oxygen plasma, sulfuric acid or the like. The insulating film is preferably an insulating film such as a silicon nitride film which is not etched with hydrofluoric acid.

  Next, as shown in FIG. 5C, dry etching is performed using the insulating film mask 3 as a mask to form a trench 4 in the main surface of the drift region 2.

  Next, an oxide sacrificial film (not shown) is formed at the corners of the groove 4 and the oxide sacrificial film is etched. By repeating the formation of the sacrificial oxide film and the etching as described above, as shown in FIG. 5D, the groove 4 with rounded corners is formed. That is, the radius of curvature of the corner of groove 4 is longer than that before sacrificial oxidation.

  Next, using the insulating film mask 3 as a mask, ion implantation of an N-type impurity having an N-type impurity concentration higher than that of the material of the drift region 2 is performed to form a depletion layer diffusion preventing region 6. Subsequently, ion implantation of P-type impurities is performed on the drift region 2 to form an electric field relaxation region 7. Thus, as shown in FIG. 5E, the electric field relaxation region 7 and the depletion layer diffusion preventing region 6 are formed. Note that aluminum (Al), boron (B) or the like can be used as the P-type impurity of the electric field relaxation region 7.

  Next, an oxide sacrificial film (not shown) is formed on the side surface of the groove 4 and the oxide sacrificial film is etched. By repeating the formation of the sacrificial oxide film and the etching in this manner, the electric field relaxation region 7 and the depletion layer diffusion preventing region 6 exposed on the side surface of the trench 4 are selectively removed as shown in FIG. The electric field relaxation region 7 and the depletion layer diffusion preventing region 6 remain only at the bottom.

  Next, as shown in FIG. 5G, the entire groove 4 is buried to form an anode electrode 9 on the drift region 2. Further, the cathode electrode 10 is formed on the back surface opposite to the main surface of the semiconductor substrate 1. Thus, the semiconductor device 100 shown in FIG. 1 is completed.

[Effect of First Embodiment]
As described above, according to the first embodiment, the electric field relaxation region 7 is formed in contact with the anode electrode 9 at the bottom of the groove 4. Further, depletion layer diffusion preventing region 6 is formed to cover electric field relaxation region 7. Thereby, the semiconductor device 100 according to the first embodiment improves the reverse breakdown voltage by the formation of the electric field relaxation region 7 and suppresses the spread of the depletion layer by the depletion layer diffusion preventing region 6 so that the forward current Can be increased.

  Further, according to the first embodiment, the anode electrode 9 is formed so as to fill the grooves 4 and is further formed so as to connect the adjacent grooves 4 with each other. Thus, a diode is formed also between the drift region 2 sandwiched by the adjacent grooves 4. Thereby, the forward current can be increased.

  Further, according to the first embodiment, the depletion layer diffusion preventing region 6 is formed between the electric field relaxation region 7 and the drift region 2 and formed in contact with the groove 4. That is, the electric field relaxation region 7 is formed in a region not in direct contact with the drift region 2. Thus, the semiconductor device 100 can increase the forward current by suppressing the spread of the depletion layer.

  Further, according to the first embodiment, the anode electrode 9 is formed of a material different from that of the drift region 2. As a result, the anode electrode 9 and the drift region 2 form a heterojunction to form a unipolar diode. A unipolar diode can suppress reverse recovery charge as compared to a bipolar diode, so that a low loss semiconductor device can be provided.

  The anode electrode 9 may be formed of a semiconductor material (for example, silicon) having a band gap different from that of the drift region 2. As a result, the anode electrode 9 and the drift region 2 form a heterojunction to form a unipolar diode. A unipolar diode can suppress reverse recovery charge as compared to a bipolar diode, so that a low loss semiconductor device can be provided.

  Further, in the method of manufacturing the semiconductor device 100 according to the first embodiment, the insulating film is deposited on the main surface of the drift region 2 and the insulating film is etched by using the resist having an opening in the formation portion of the trench 4 as a mask. A mask is fabricated, and the drift region 2 exposed from the opening of the hard mask is selectively etched to form a groove 4. Then, the N type impurity and the P type impurity are continuously injected into the groove 4 to form the depletion layer diffusion preventing region 6 and the electric field relaxation region 7, and a sacrificial oxide film is selectively formed on the side surface of the groove 4. The sacrificial oxide film is etched. Thereby, the depletion layer diffusion preventing region 6 and the electric field relaxation region 7 can be formed at the bottom of the groove 4, and the semiconductor device 100 according to the first embodiment described above can be manufactured.

  Further, according to the method of manufacturing the semiconductor device 100 according to the first embodiment, after forming the groove 4, a sacrificial oxide film is formed on the side surface of the groove 4, and the sacrificial oxide film is etched. Thereby, the radius of curvature of the corner of groove 4 can be made larger than that before sacrificial oxidation. As a result, as shown in FIG. 2A, the electric field relaxation region 7 can be formed so as to cover from the bottom to the corner of the groove 4, and the depletion layer 11 spreads from the electric field relaxation region 7. The electric field at the corners is relaxed. Thereby, the reverse leakage current from the corner of the groove 4 is suppressed.

  In the first embodiment, the depletion layer diffusion preventing region 6 is formed to cover the electric field relaxation region 7. Therefore, depletion layer diffusion prevention region 6 is in contact with groove 4. However, the region for forming depletion layer diffusion prevention region 6 is not limited to this. For example, the depletion layer diffusion preventing region 6 can be formed to cover the electric field relaxation region 7 and can be formed in a region not in contact with the groove 4. Thus, even if the depletion layer diffusion preventing region 6 is formed, the spread of the depletion layer can be suppressed, and the forward current can be increased.

  In the first embodiment, as shown in FIG. 1, the electric field relaxation region 7 and the depletion layer diffusion preventing region 6 are formed at the bottom of the groove 4, but the region forming the electric field relaxation region 7 and the depletion layer diffusion preventing region 6 is It is not limited to this. For example, as shown in FIG. 6, the electric field relaxation region 7 and the depletion layer diffusion preventing region 6 may be formed at the corners of the groove 4. According to this structure, since there is no electric field relaxation region 7 at the center of the bottom of the groove 4, the center of the bottom of the groove 4 contacts the drift region 2. Thereby, the semiconductor device 100 can allow forward current to flow through the central portion of the bottom of the groove 4.

  In the first embodiment, the anode electrode 9 is described as one type of electrode. However, the present invention is not limited to this, and may be formed of two types of electrodes. For example, as shown in FIG. 7, two types of electrodes, an anode electrode 9a formed so as to embed the groove 4 and an anode electrode 9b in contact with the drift region 2 sandwiched by the adjacent grooves 4 are formed. It is also good. At this time, P-type polycrystalline silicon that forms a high energy barrier with the drift region 2 is used as the material of the anode electrode 9a, and a material with the anode electrode 9b has a low energy barrier with the drift region 2 N-type polycrystalline silicon can be used to make.

  With this configuration, when a reverse voltage is applied, the depletion layer spreads from the corner of the groove 4 to the other corner from the anode electrode 9a having a high energy barrier, and the reverse leakage current can be suppressed. Further, the depletion layer spreading from the electric field relaxation region 7 can further reduce the electric field concentrated at the corner of the trench 4. In addition, when a forward voltage is applied, a large amount of forward current can flow through the anode electrode 9b having a low energy barrier.

Second Embodiment
Next, a semiconductor device 200 according to a second embodiment of the present invention will be described with reference to FIG. The second embodiment is different from the first embodiment in that the semiconductor device 200 has a transistor and a diode. About the composition which overlaps with a 1st embodiment, a code is quoted, the explanation shall be omitted and it explains focusing on difference below.

[Configuration of Semiconductor Device]
The configuration of the semiconductor device 200 according to the second embodiment will be described with reference to FIG. A drift region 2 which is an N-type low concentration SiC layer is formed on the main surface of a semiconductor substrate 1 which is an N-type high concentration silicon carbide substrate.

  Inside the drift region 2, a P-type well region 20 is formed. Well region 20 is formed in the upper region of drift region 2 including the main surface of drift region 2. Inside the well region 20, an N + -type source region 21 is formed. Source region 21 is formed in the upper region of well region 20 including the main surface of well region 20.

  A gate electrode 24 is embedded in the side surface of the groove 22 penetrating the source region 21 and the well region 20 to the drift region 2 via the gate insulating film 23. The gate electrode 24 is adjacent to the source region 21 and the well region 20 and the drift region 2 exposed to the side surface of the groove 22 through the gate insulating film 23. The gate insulating film 23 separates between the bottom surface of the gate electrode 24 and the bottom surface of the groove 22 and between the outer side surface of the inner and outer side surfaces of the gate electrode 24 and the side surface of the groove 22. The gate electrode 24 is covered with an interlayer insulating film 25. The interlayer insulating film 25 covers the inner side surface and the upper surface of the gate electrode 24.

  A P-type anode region 27 is embedded in the contact hole 26 surrounded by the gate electrode 24 via the interlayer insulating film 25. Interlayer insulating film 25 separates the inner side surface of gate electrode 24 from the side surface of anode region 27. The bottom of the anode region 27 is in contact with the drift region 2 to form a diode.

  An electric field relaxation region 29 is formed on the bottom of the gate electrode 24 with the gate insulating film 23 interposed therebetween. A depletion layer diffusion preventing region 28 is formed to cover the electric field relaxation region 29. The gate insulating film 23 separates the bottom surface of the gate electrode 24 from the top surfaces of the electric field relaxation region 29 and the depletion layer diffusion preventing region 28. The electric field relaxation region 29 and the depletion layer diffusion preventing region 28 are in contact with the corner of the groove 22.

  A source electrode 31 is formed on the source region 21, the interlayer insulating film 25 and the anode region 27. The source electrode 31 is electrically connected to the well region 20, the source region 21, and the anode region 27 with low resistance, that is, ohmic connection. The gate electrode 24 and the source electrode 31 are insulated by the interlayer insulating film 25. The drain electrode 30 is ohmically connected to the back surface of the semiconductor substrate 1.

  Specifically, semiconductor device 200 shown in FIG. 8 includes drift region 2 formed on the surface of semiconductor substrate 1, well region 20 formed in drift region 2, and source region 21 formed in well region 20. And a transistor including a groove 22 formed in the well region 20 and a gate electrode 24 formed in the groove 22 with the gate insulating film 23 interposed therebetween. The semiconductor device 200 further includes a diode including the P-type anode region 27 in which the drift region 2 is a cathode region and in contact with the cathode region.

[Operation of semiconductor device]
Next, the basic operation of the semiconductor device 200 shown in FIG. 8 will be described. The semiconductor device 200 functions as a transistor by controlling the potential of the gate electrode 24 in a state where a predetermined positive potential is applied to the drain electrode 30 based on the potential of the source electrode 31. That is, when the voltage between the gate electrode 24 and the source electrode 31 is equal to or higher than a predetermined threshold voltage, an inversion layer is formed on the side surface (channel portion) of the well region 20 adjacent to the side surface of the gate electrode 24 via the gate insulating film 23. Be done. Thus, the transistor is turned on, and current flows from the drain electrode 30 to the source electrode 31.

  On the other hand, when the voltage between the gate electrode 24 and the source electrode 31 is equal to or lower than a predetermined threshold voltage, the inversion layer disappears, the transistor is turned off, and the current is cut off. At this time, a high voltage of several hundred to several thousand volts is applied between the drain and the source.

  When a predetermined negative potential is applied to the drain electrode 30 with reference to the potential of the source electrode 31, a current flows in a diode in which the well region 20 and the anode region 27 are the anode and the drift region 2 is the cathode. At this time, since the depletion layer spreading from the electric field relaxation region 29 is suppressed by the depletion layer diffusion preventing region 28, the current flowing to the diode can be increased.

[Effect of semiconductor device]
As described above, according to the second embodiment, the anode region 27 is formed inside the groove 22 together with the gate electrode 24, and a diode is formed on the bottom of the groove 22. At the time of conduction, the depletion layer diffusion preventing region 28 suppresses the depletion layer spreading from the electric field relaxation region 29. Thus, the semiconductor device 200 can increase the current flowing to the diode.

  While the embodiments of the present invention have been described above, it should not be understood that the statements and drawings that form a part of this disclosure limit the present invention. Various alternative embodiments, examples and operation techniques will be apparent to those skilled in the art from this disclosure.

DESCRIPTION OF SYMBOLS 1 semiconductor substrate 2 drift region 3 insulating film mask 4 groove 6 depletion layer diffusion preventing region 7 electric field relaxation region 9 anode electrode 10 cathode electrode 11, 12, 14 depletion layer 20 well region 21 source region 22 groove 23 gate insulating film 24 gate electrode 25 interlayer insulating film 26 contact hole 27 anode region 28 depletion layer diffusion preventing region 29 electric field relaxation region 30 drain electrode 31 source electrode

Claims (16)

A semiconductor substrate,
A drift region of a first conductivity type formed on the main surface of the semiconductor substrate;
A groove formed from the main surface of the drift region toward the junction surface between the semiconductor substrate and the drift region;
An anode electrode embedded at least in the interior of the groove and forming a diode with the drift region;
An electric field relaxation region of a second conductivity type formed to be in contact with the anode electrode so as to cover the bottom of the groove;
A depletion layer diffusion preventing region in contact with the electric field relaxation region and the drift region and containing a first conductivity type impurity having a concentration higher than that of the drift region;
The semiconductor device characterized by having.   The semiconductor device according to claim 1, wherein the anode electrode forms a diode also between the drift region sandwiched by the adjacent grooves.   The semiconductor device according to claim 1, wherein the depletion layer diffusion preventing region is formed in a region not in contact with the groove. The depletion layer diffusion preventing region is formed between the electric field relaxation region and the drift region.
The semiconductor device according to claim 1, wherein the electric field relaxation region is not in contact with the drift region.   The semiconductor device according to any one of claims 1 to 4, wherein the electric field relaxation region is in contact with a corner of the groove.   The semiconductor device according to any one of claims 1 to 5, wherein the anode electrode is formed of a material different from the drift region, and a unipolar diode is formed between the anode and the drift region.   The semiconductor device according to any one of claims 1 to 6, wherein the anode electrode is formed of a semiconductor material having a band gap different from the material of the drift region. The anode electrode is formed of two types of electrodes, a first anode electrode formed to be embedded in the groove and a second anode electrode in contact with the drift region sandwiched by the adjacent grooves.
The height of the energy barrier that the first anode electrode makes with the drift region is higher than the height of the energy barrier that the second anode electrode makes with the drift region. The semiconductor device according to any one of 7. A semiconductor substrate,
A drift region of a first conductivity type formed on the main surface of the semiconductor substrate;
A groove formed from the main surface of the drift region toward the junction surface between the semiconductor substrate and the drift region;
A well region of the second conductivity type formed in the drift region and in contact with the groove;
A source region of the first conductivity type formed in the well region in contact with the main surface of the drift region;
A gate electrode formed on a side surface of the groove via a gate insulating film;
An interlayer insulating film covering the gate electrode;
A source electrode connected to the well region and the source region;
An anode region embedded in the interior surrounded by the gate electrode and forming a diode with the drift region;
An electric field relaxation region of a second conductivity type formed on the bottom surface of the gate electrode via the gate insulating film;
A depletion layer diffusion preventing region in contact with the electric field relaxation region and the drift region and containing a first conductivity type impurity having a concentration higher than that of the drift region;
A semiconductor device comprising: a drain electrode in ohmic contact with a back surface opposite to the main surface of the semiconductor substrate. A method of manufacturing a semiconductor device according to any one of claims 1 to 8, wherein
A first step of depositing an insulating film on the main surface of the drift region and etching the insulating film using a resist having an opening in a portion where the groove is formed as a mask;
A second step of selectively etching the drift region exposed from the opening of the hard mask to form the groove;
After the second step, a third step of continuously implanting the first conductivity type impurity and the second conductivity type impurity into the groove to form the depletion layer diffusion preventing region and the electric field relaxation region;
A method of manufacturing a semiconductor device, comprising: forming a first sacrificial oxide film selectively on side surfaces of the trench; and etching the first sacrificial oxide film.   After the second step, before the third step, a second sacrificial oxide film is formed on the side surface of the groove, and the second sacrificial oxide film is etched, whereby the curvature of the corner of the groove is obtained. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the radius is made larger than that before sacrificial oxidation. A semiconductor substrate,
A drift region of a first conductivity type formed on the main surface of the semiconductor substrate;
A groove formed from the main surface of the drift region toward the junction surface between the semiconductor substrate and the drift region;
An anode electrode embedded at least in the interior of the groove and forming a diode with the drift region;
An electric field relaxation region of a second conductivity type formed to be in contact with the anode electrode so as to cover at least an end of a bottom of the groove;
A semiconductor device comprising: the electric field relaxation region and a depletion layer diffusion preventing region in contact with the drift region and containing a first conductivity type impurity having a concentration higher than that of the drift region.   The semiconductor device according to claim 12, wherein at least the drift region is present between adjacent ones of the plurality of grooves.   The semiconductor device according to claim 12, wherein the depletion layer diffusion preventing region is formed in a region not in contact with the groove. The depletion layer diffusion preventing region is formed between the electric field relaxation region and the drift region.
The semiconductor device according to claim 12, wherein the electric field relaxation region is not in contact with the drift region.   The electric field relaxation region is formed such that the central portion of the bottom of the groove is in contact with the drift region, and the depletion layer diffusion preventing region is formed between the electric field relaxation region and the drift region. The semiconductor device of any one of Claims 12-15.

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