CN115985852B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN115985852B CN115985852B CN202310279233.9A CN202310279233A CN115985852B CN 115985852 B CN115985852 B CN 115985852B CN 202310279233 A CN202310279233 A CN 202310279233A CN 115985852 B CN115985852 B CN 115985852B
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Abstract
The invention relates to a semiconductor device and a preparation method thereof, wherein the preparation method of the semiconductor device comprises the following steps: providing a semiconductor substrate; forming a first element first conductivity type region in a first element region in a semiconductor substrate; a first conductivity type channel region is formed in a second element region within the semiconductor substrate, the first element first conductivity type region having a doping concentration less than the doping concentration of the first conductivity type channel region, the first element first conductivity type region and the first conductivity type channel region being at least partially in the same horizontal plane. The preparation method of the semiconductor device enables the semiconductor device to be capable of taking the reverse recovery characteristic of the first element and the low latch-up effect of the second element into consideration, and can improve the reverse recovery characteristic of the first element under the condition of ensuring the low latch-up effect of the second element.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a preparation method thereof.
Background
The reverse-conduction insulated gate bipolar transistor RC-IGBT is a power semiconductor device compounded by a diode and an insulated gate bipolar transistor IGBT, and the IGBT is a compound full-control voltage-driven power semiconductor device formed by a bipolar transistor BJT and an insulated gate field effect transistor MOS. Because the improved reverse recovery characteristic of the diode in the reverse-conducting insulated gate bipolar transistor is mutually contradicted with the reduced latch-up effect of the IGBT, the reverse recovery characteristic of the diode and the low latch-up effect of the IGBT cannot be simultaneously considered, and when the lower latch-up effect of the IGBT is ensured, the reverse recovery characteristic of the diode is poor, and no related technical means can solve the problem at present.
Disclosure of Invention
Based on the above, the invention provides a semiconductor device and a preparation method thereof, aiming at the problem that the reverse recovery characteristic and the low latch-up effect cannot be simultaneously considered.
The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate; forming a first element first conductivity type region in a first element region in the semiconductor substrate; and forming a first conductive type channel region in the second element region in the semiconductor substrate, wherein the doping concentration of the first conductive type region of the first element is smaller than that of the first conductive type channel region, and the first conductive type region of the first element and the first conductive type channel region are at least partially in the same horizontal plane.
According to the preparation method of the semiconductor device, the first element first conductive type region is formed in the first element region in the semiconductor substrate in two steps, the first conductive type channel region is formed in the second element region in the semiconductor substrate, and the doping concentration of the first element first conductive type region is smaller than that of the first conductive type channel region, so that the semiconductor device can give consideration to the reverse recovery characteristic of the first element and the low latch-up effect of the second element, and the reverse recovery characteristic of the first element can be improved under the condition that the lower latch-up effect of the second element is ensured.
In one embodiment, the semiconductor device comprises a reverse-conducting insulated gate bipolar transistor, the first element comprises a diode, and the second element comprises an insulated gate bipolar transistor.
In one embodiment, forming the first conductivity type channel region in the second element region within the semiconductor substrate comprises: forming the first conductive type channel region in the second element region in the semiconductor substrate by adopting an ion implantation process, wherein the implantation dosage is 1 multiplied by 10 13 /cm 2 ~1×10 14 /cm 2 Between them. The latch-up effect of the second element can be reduced.
In one embodiment, forming the first element first conductivity type region in the first element region within the semiconductor substrate comprises: forming the first element first conductive type region in the semiconductor substrate by ion implantation, wherein the implantation dosage is 1×10 12 /cm 2 ~1×10 13 /cm 2 Between them.
In one embodiment, the semiconductor substrate includes a second conductivity type drift region located under the first element first conductivity type region and the first conductivity type channel region.
In one embodiment, after forming the first element first conductivity type region and the first conductivity type channel region, further comprising: and forming a groove structure in the semiconductor substrate, wherein the groove structure extends from the upper surface of the semiconductor substrate to the drift region through the first element first conductive type region and/or the first conductive type channel region.
In one embodiment, the trench structure includes a gate trench structure located in the second element region and a source trench structure located in the first element region.
In one embodiment, the spacing between the source trench structures is less than the spacing between the gate trench structures. The doping concentration of the first conductive type region of the first element can be further reduced, the doping concentration of the heavily doped second conductive type region of the first element is further improved, and the performance of the first element is improved.
In one embodiment, after forming the trench structure, the method further includes: and forming a dielectric layer on the upper surface of the semiconductor substrate, wherein the dielectric layer comprises an opening, the opening comprises a first opening, and the first opening exposes the first conductive type channel region.
In one embodiment, after forming the dielectric layer, the method further includes: a second conductivity type source region is formed in the semiconductor substrate through the first opening in the second element region, the second conductivity type source region being located above the first conductivity type channel region.
In one embodiment, before forming the second conductivity type source region, the method further comprises: and forming a first conduction type ohmic contact region in the second element region in the semiconductor substrate through the first opening, wherein the first conduction type ohmic contact region is positioned on one side, close to the second conduction type source region, in the first conduction type channel region. It is possible to ensure that the metal layer forms a good ohmic contact with the first conductivity type channel region.
In one embodiment, forming the first conductivity type ohmic contact region in the second element region within the semiconductor substrate through the first opening includes: forming the first conductive type ohmic contact region in the semiconductor substrate through the first opening by adopting an ion implantation process, wherein the implantation energy is 15 keV-100 keV, and the implantation dosage is 1 multiplied by 10 14 /cm 2 ~5×10 15 /cm 2 Between them. It is possible to ensure that the metal layer forms a good ohmic contact with the first conductivity type channel region.
In one embodiment, after forming the dielectric layer, the method further includes: and forming a metal layer in the opening and on the upper surface of the dielectric layer, wherein the metal layer is electrically connected with the second conduction type source region through the first opening.
In one embodiment, after providing a semiconductor substrate, further comprising: and forming a back first element second conductive type region and a back second element first conductive type region on the back of the semiconductor substrate, wherein the back first element second conductive type region and the back second element first conductive type region are positioned below the second conductive type drift region.
In one embodiment, before the first element region forms the first element first conductivity type region in the semiconductor substrate, the method further comprises: a first element heavily doped second conductivity type region is formed in the semiconductor substrate in the first element region, the first element heavily doped second conductivity type region being located below the first element first conductivity type region. The injection of holes when the first element is conducted can be reduced, and the performance of the first element can be better optimized.
In one embodiment, forming the first element heavily doped second conductivity type region in the first element region within the semiconductor substrate comprises: the first element region forms the first element heavily doped second conductivity type region within the semiconductor substrate, the second element region forms a second element heavily doped second conductivity type region, and the second element heavily doped second conductivity type region is located below the first conductivity type channel region. So that when the second element is conducted, the accumulation of holes is increased, and the conduction voltage drop of the second element is reduced.
In one embodiment, before the second element region forms the first conductivity type channel region in the semiconductor substrate, the method further comprises: forming a second element heavily doped second conductivity type region in the semiconductor substrate in the second element region, the second element heavily doped second conductivity type region being located below the first conductivity type channel region. So that when the second element is conducted, the accumulation of holes is increased, and the conduction voltage drop of the second element is reduced.
In one embodiment, the method further comprises: electron irradiation, platinum doping, or helium irradiation is employed to reduce minority carrier lifetime of the first element. The first element performance is further optimized.
The invention also provides a semiconductor device, which is prepared by adopting the preparation method of the semiconductor device.
According to the semiconductor device, the doping concentration of the first conductive type region of the first element is smaller than that of the first conductive type channel region, so that the semiconductor device can give consideration to the reverse recovery characteristic of the first element and the low latch-up effect of the second element, and the reverse recovery characteristic of the first element can be improved under the condition that the lower latch-up effect of the second element is ensured.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device of the present invention.
Fig. 2 to 13 are schematic structural views showing steps of a method for manufacturing a semiconductor device according to the present invention; fig. 13 is a schematic structural diagram of the semiconductor device according to the present invention.
In the figure: 10. a semiconductor substrate; 101. a second conductivity type drift region; 20. a first element region; 201. the first element heavily dopes the second conductivity type region; 202. a first element first conductivity type region; 203. backside first element second conductivity type region; 30. a second element region; 301. the second element heavily dopes the second conductivity type region; 302. a first conductivity type channel region; 303. ohmic contact regions of the first conductivity type; 304. a second conductivity type source region; 305. a backside second element first conductivity type region; 40. a trench structure; 401. a source trench structure; 402. a gate trench structure; 403. a trench dielectric layer; 404. a trench filling material; 50. a dielectric layer; 501. an opening; 5011. a first opening; 5012. a second opening; 60. a metal layer; 70. and (5) a mask layer.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., are based on the methods or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In one embodiment, the first conductivity type region in the diode in the reverse-conducting insulated gate bipolar transistor RC-IGBT and the first conductivity type channel region 302 in the IGBT are formed in the same step using the same implantation conditions and the doping concentration is the same. The inventors of the present invention found that this would cause the improved reverse recovery characteristics of the diode in the reverse-conducting insulated gate bipolar transistor to contradict the reduced latch-up of the IGBT, and that the reverse recovery characteristics of the diode and the low latch-up of the IGBT could not be simultaneously considered.
In one embodiment, as shown in fig. 1, a method for manufacturing a semiconductor device is provided, including: providing a semiconductor substrate 10; forming a first element first conductivity type region 202 in the first element region 20 in the semiconductor substrate 10; a first-conductivity-type channel region 302 is formed in the semiconductor substrate 10 in the second-element region 30, the first-element first-conductivity-type region 202 having a doping concentration less than that of the first-conductivity-type channel region 302, the first-element first-conductivity-type region 202 and the first-conductivity-type channel region 302 being at least partially at the same level.
In the method for manufacturing a semiconductor device according to the present embodiment, the first element first conductivity type region 202 is formed in the first element region 20 in the semiconductor substrate 10 in two steps, the first conductivity type channel region 302 is formed in the second element region 30 in the semiconductor substrate 10, and the doping concentration of the first element first conductivity type region 202 is smaller than that of the first conductivity type channel region 302, so that the semiconductor device can achieve both the reverse recovery characteristic of the first element and the low latch-up effect of the second element, and the reverse recovery characteristic of the first element can be improved while ensuring the lower latch-up effect of the second element.
The first element first conductivity type region 202 and the first conductivity type channel region 302 are formed in two steps using different implantation conditions, so that the doping concentration of the first element first conductivity type region 202 can be smaller, the hole concentration in the second conductivity type drift region 101 near the first element first conductivity type region 202 is relatively smaller when the first element is turned on, the voltage rising speed of the first element is faster when the first element is in reverse recovery, the maximum reverse recovery current can be smaller, and the softness of the reverse recovery can be lower; the doping concentration of the first conductivity type channel region 302 can be greater, and the latch-up of the second element can be reduced, so that the semiconductor device can give consideration to both the reverse recovery characteristic of the first element and the low latch-up of the second element, and the reverse recovery characteristic of the first element can be improved while ensuring the low latch-up of the second element.
S10: as shown in fig. 2, a semiconductor substrate 10 is provided.
In one embodiment, the semiconductor substrate 10 includes a second conductivity type drift region 101, the second conductivity type drift region 101 being located below the first element first conductivity type region 202 and the first conductivity type channel region 302.
In one embodiment, the material of semiconductor substrate 10 comprises silicon or silicon carbide.
The resistivity and thickness of the second conductivity type drift region 101 are determined by the breakdown voltage of the device. For an IGBT with a breakdown voltage of 650V, the resistivity of the second conductivity type drift region 101 is between 20Ω·cm to 40Ω·cm, for example, the resistivity of the second conductivity type drift region 101 may be 30Ω·cm; the thickness of the second conductivity type drift region 101 is between 50 μm and 80 μm, for example, the thickness of the second conductivity type drift region 101 is 65 μm; for an IGBT with a breakdown voltage of 1200V, the resistivity of the second conductivity type drift region 101 is between 50Ω·cm and 70Ω·cm, for example, the resistivity of the second conductivity type drift region 101 may be 60Ω·cm; the thickness of the second conductivity type drift region 101 is between 100 μm and 140 μm, for example, the thickness of the second conductivity type drift region 101 is 120 μm.
S301: first element first conductivity type region 202 is formed in first element region 20 within semiconductor substrate 10.
In one embodiment, before step S301, the method further includes:
s201: first element heavily doped second conductivity type region 201 is formed in first element region 20 within semiconductor substrate 10, with first element heavily doped second conductivity type region 201 being located below first element first conductivity type region 202. An isolation can be formed, and when the first element is turned on, electron injection is reduced, and hole injection is also reduced, so that injected electrons and holes are reduced, and the performance of the first element can be better optimized.
In one embodiment, step S201 includes: as shown in fig. 3, a first element heavily doped second conductivity type region 201 is formed in the first element region 20 within the semiconductor substrate 10, a second element heavily doped second conductivity type region 301 is formed in the second element region 30, and the second element heavily doped second conductivity type region 301 is located below the first conductivity type channel region 302. So that when the second element is conducted, the accumulation of holes is increased, and the conduction voltage drop of the second element is reduced.
S302: a first-conductivity-type channel region 302 is formed in the semiconductor substrate 10 in the second-element region 30, the first-element first-conductivity-type region 202 having a doping concentration less than that of the first-conductivity-type channel region 302, the first-element first-conductivity-type region 202 and the first-conductivity-type channel region 302 being at least partially at the same level.
In one embodiment, before step S302, further includes:
s202: a second element heavily doped second conductivity type region 301 is formed in the second element region 30 within the semiconductor substrate 10, the second element heavily doped second conductivity type region 301 being located below the first conductivity type channel region 302. When the second element is conducted, accumulation of holes is increased, conduction voltage drop of the second element is reduced, switching loss of the second element is increased somewhat, and saturation voltage and turn-off energy consumption of the IGBT are a compromise.
S301: first element first conductivity type region 202 is formed in first element region 20 within semiconductor substrate 10.
In one embodiment, step S301 includes: an ion implantation process is used to form a first element first conductivity type region 202 in a first element region 20 of a semiconductor substrate 10, wherein the implantation dose is between 1 x 10 12 /cm 2 ~1×10 13 /cm 2 The implantation energy is 80-120 keV. For example, boron is implanted into the first element region 20 in the semiconductor substrate 10 to form a first element first conductivity type region 202, wherein the implant dose is 2×10 12 /cm 2 The implantation energy was 100keV.
In one embodiment, step S301 includes: as shown in fig. 4, first element first conductivity type regions 202 are formed in the semiconductor substrate 10 in the first element region 20 and the second element region 30.
S302: a first-conductivity-type channel region 302 is formed in the semiconductor substrate 10 in the second-element region 30, the first-element first-conductivity-type region 202 having a doping concentration less than that of the first-conductivity-type channel region 302, the first-element first-conductivity-type region 202 and the first-conductivity-type channel region 302 being at least partially at the same level.
In one embodiment, step S302 includes: forming a first conductivity type channel region 302 in the second element region 30 of the semiconductor substrate 10 by ion implantation at an implantation dose of 1×10 13 /cm 2 ~1×10 14 /cm 2 In between, for example, the implant dose may be 2×10 13 /cm 2 、4×10 13 /cm 2 、6×10 13 /cm 2 、8×10 13 /cm 2 . The first conductivity type channel region 302 has a lower doping concentration, which can reduce the base resistance of the second element, reduce the possibility of conducting parasitic NPN and reduce the latch-up effect of the second element.
In one embodiment, step S302 includes:
s3021: as shown in fig. 5, a mask layer 70 is formed on the upper surface of the semiconductor substrate 10 at the first element region 20, and the mask layer 70 exposes the second element region 30;
s3022: as shown in fig. 6, an ion implantation process is used to form a first conductivity type channel region 302 in the second element region 30 within the semiconductor substrate 10;
s3023: as shown in fig. 7, the mask layer 70 is removed.
In one embodiment, the semiconductor device comprises a reverse-conducting insulated gate bipolar transistor, the first element comprises a diode, and the second element comprises an insulated gate bipolar transistor.
In one embodiment, the first element comprises a fast recovery diode.
In one embodiment, the first conductivity type comprises a P-type and the second conductivity type comprises an N-type.
In another embodiment, the first conductivity type comprises an N-type and the second conductivity type comprises a P-type.
In one embodiment, after step S301 and step S302, further includes:
s40: as shown in fig. 8, a trench structure 40 is formed in the semiconductor substrate 10, the trench structure 40 extending from the upper surface of the semiconductor substrate 10 through the first element first conductivity type region 202 and/or the first conductivity type channel region 302 to the drift region.
In one embodiment, trench structure 40 includes a trench fill material 404 and a trench dielectric layer 403 for isolation between trench fill material 404 and semiconductor substrate 10.
In one embodiment, trench dielectric layer 403 includes an oxide layer. The thickness of the trench dielectric layer 403 is 800 a-1200 a, for example, the thickness of the trench dielectric layer 403 may be 1000 a. The trench fill material 404 comprises heavily doped polysilicon.
In one embodiment, trench structure 40 includes a gate trench structure 402 located in second element region 30 and a source trench structure 401 located in first element region 20.
In one embodiment, at least a portion of the source trench structure 401 is located at the interface of the first element region 20 and the second element region 30.
In one embodiment, the ratio of the number of gate trench structures 402 to the number of source trenches is less than or equal to 1, for example, the ratio of the number of gate trench structures 402 to the number of source trenches may be 1:1 or 2:3, and when the area of the first element region 20 is increased, the performance of the first element may be optimized, but for the second element, the saturation voltage may be increased, but the short-circuit current resistance performance of the second element may be better.
In one embodiment, the spacing between source trench structures 401 is less than the spacing between gate trench structures 402. The source trench structure 401 produces lateral depletion of the first element heavily doped second conductivity type region 201; this can increase the doping concentration of the first element heavily doping the second conductivity type region 201; because the lateral depletion is enhanced and the longitudinal depletion is reduced, the doping concentration of the first element first conductivity type region 202 can be further reduced, which is beneficial to the improvement of the performance of the first element.
In one embodiment, after step S40, further comprising:
s50: as shown in fig. 9, a dielectric layer 50 is formed on the upper surface of the semiconductor substrate 10, the dielectric layer 50 includes an opening 501, the opening 501 includes a first opening 5011, and the first opening 5011 exposes the first conductive type channel region 302.
In one embodiment, the opening 501 further includes a second opening 5012, the second opening 5012 exposing the trench fill material 404 of the source trench structure 401.
In one embodiment, the openings 501 further include a third opening exposing the first element first conductivity type region 202.
S70: as shown in fig. 11, a second conductive type source region 304 is formed in the semiconductor substrate 10 through the first opening 5011 in the second element region 30, the second conductive type source region 304 being located above the first conductive type channel region 302.
In one embodiment, before step S70, further comprising:
s60: as shown in fig. 10, 11 and 12, the first conductivity-type ohmic contact region 303 is formed in the second element region 30 in the semiconductor substrate 10 through the first opening 5011, and the first conductivity-type ohmic contact region 303 is located at a side near the second conductivity-type source region 304 in the first conductivity-type channel region 302. It is possible to ensure that the metal layer 60 forms a good ohmic contact with the first conductive-type channel region 302.
In one embodiment, step S60 includes: an ion implantation process is used to form the ohmic contact region 303 of the first conductivity type in the second element region 30 of the semiconductor substrate 10 through the first opening 5011, wherein the implantation energy is 15keV to 100keV, for example, the implantation energy may be 15keV, 40keV, 60keV, 80keV, 100keV. The implantation dosage is 1×10 14 /cm 2 ~5×10 15 /cm 2 In between, for example, the implant dose may be 2×10 14 /cm 2 、4×10 14 /cm 2 、6×10 14 /cm 2 、8×10 14 /cm 2 . It is possible to ensure that the metal layer 60 forms a good ohmic contact with the first conductive-type channel region 302.
In one embodiment, step S60 includes: boron difluoride is implanted through the first opening 5011 into the second element region 30 in the semiconductor substrate 10 to form the first conductivity type ohmic contact region 303.
In one embodiment, after step S50, further comprising:
s70: as shown in fig. 11, a second conductive type source region 304 is formed in the semiconductor substrate 10 through the first opening 5011 in the second element region 30, the second conductive type source region 304 being located above the first conductive type channel region 302.
In one embodiment, step S70 includes: arsenic is implanted into the second element region 30 of the semiconductor substrate 10 through the first opening 5011 to form a second conductivity type source region 304 with an implant dose of 1×10 15 /cm 2 ~1×10 16 /cm 2 In between, for example, the implant dose may be 2×10 15 /cm 2 、4×10 15 /cm 2 、6×10 15 /cm 2 、8×10 15 /cm 2 。
In one embodiment, the second conductivity type source region 304 comprises a second conductivity type heavily doped source region.
In one embodiment, after step S50, further comprising:
s80: as shown in fig. 12, a metal layer 60 is formed in the opening 501 and on the upper surface of the dielectric layer 50, and the metal layer 60 is electrically connected to the second conductive type source region 304 through the first opening 5011.
In one embodiment, the metal layer 60 is electrically connected to the source trench structure 401 through the second opening 5012.
In one embodiment, step S80 includes: tungsten is filled in the opening 501. The material of the metal layer 60 includes aluminum.
In one embodiment, after step S10, further comprising:
s90: as shown in fig. 13, a back first element second conductivity type region 203 and a back second element first conductivity type region 305 are formed on the back side of the semiconductor substrate 10, the back first element second conductivity type region 203 and the back second element first conductivity type region 305 being located below the second conductivity type drift region 101.
In one embodiment, step S90 comprises: boron is implanted into the back surface of the semiconductor substrate 10 to form a back surface second element first conductive type region 305, the implantation energy is smaller between 20keV and 100keV, and the implantation dosage is smaller between 1 multiplied by 10 12 /cm 2 ~1×10 13 /cm 2 In between, the second element performance can be improved, reducing the turn-off speed.
In one embodiment, step S90 includes: phosphorus or arsenic is injected into the back surface of the semiconductor substrate 10 to form a back surface first element second conductive type region 203, the injection energy is 50-150 keV, and the injection dosage is 1×10 14 /cm 2 ~1×10 16 /cm 2 Between them.
In one embodiment, the area of the back second element first conductivity type region 305 may be greater than 80% of the total back surface area, e.g., the area of the back second element first conductivity type region 305 may be 81%, 86%, 90% of the total back surface area.
In one embodiment, further comprising:
s91: electron irradiation, platinum doping, or helium irradiation is employed to reduce minority carrier lifetime of the first element. The first element performance is further optimized.
In one embodiment, as shown in fig. 13, a semiconductor device is provided, and the semiconductor device is prepared by the method for preparing a semiconductor device, including: a semiconductor substrate 10; a first element first conductivity type region 202 formed in the first element region 20 in the semiconductor substrate 10; the first-conductivity-type channel region 302 is formed in the second-element region 30 in the semiconductor substrate 10, the first-element first-conductivity-type region 202 has a doping concentration less than that of the first-conductivity-type channel region 302, and the first-element first-conductivity-type region 202 and the first-conductivity-type channel region 302 are at least partially at the same level.
In the present embodiment, the doping concentration of the first-element first-conductivity-type region 202 is smaller than that of the first-conductivity-type channel region 302, so that the semiconductor device can achieve both the reverse recovery characteristic of the first element and the low latch-up effect of the second element, and can improve the reverse recovery characteristic of the first element while ensuring the low latch-up effect of the second element.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (9)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a second conductive type drift region;
forming a first element first conductivity type region in the semiconductor substrate in a first element region, the first element first conductivity type region being located above the second conductivity type drift region;
forming a first conductive type channel region in the semiconductor substrate, wherein the first conductive type channel region is positioned above the second conductive type drift region, the doping concentration of the first conductive type region of the first element is smaller than that of the first conductive type channel region, the first conductive type region of the first element and the first conductive type channel region are at least partially positioned on the same horizontal plane, the semiconductor device comprises a reverse conductive type insulated gate bipolar transistor, the first element comprises a diode, and the second element comprises an insulated gate bipolar transistor;
forming a trench structure in the semiconductor substrate, wherein the trench structure extends from the upper surface of the semiconductor substrate to the drift region through the first element first conductive type region and/or the first conductive type channel region, the trench structure comprises a gate trench structure positioned in the second element region and a source trench structure positioned in the first element region, and the spacing between the source trench structures positioned in the first element region is smaller than the spacing between the gate trench structures positioned in the second element region;
forming a dielectric layer on the upper surface of the semiconductor substrate, wherein the dielectric layer comprises an opening, the opening comprises a first opening, and the first opening exposes the first conductive type channel region;
forming a first conductive type ohmic contact region in the semiconductor substrate through the first opening in the second element region;
forming a second conductive type source region in the semiconductor substrate through the first opening, wherein the second conductive type source region is positioned above the first conductive type channel region, and the first conductive type ohmic contact region is positioned at one side, close to the second conductive type source region, in the first conductive type channel region;
forming a metal layer in the opening and on the upper surface of the dielectric layer, wherein the metal layer is electrically connected with the second conduction type source region through the first opening, the second conduction type source region is arranged between the metal layer and the first conduction type ohmic contact region, and the first conduction type ohmic contact region is formed in the first conduction type channel region so as to ensure that good ohmic contact is formed between the metal layer and the first conduction type channel region;
forming a back first element second conductive type region and a back second element first conductive type region on the back of the semiconductor substrate, wherein the back first element second conductive type region and the back second element first conductive type region are located below the second conductive type drift region, the back first element second conductive type region is not limited to the first element region, the back second element first conductive type region is not limited to the second element region, and at least part of the back first element second conductive type region is located in the second element region.
2. The method of manufacturing a semiconductor device according to claim 1, wherein forming the first conductivity type channel region in the second element region in the semiconductor substrate comprises: forming the first conductive type channel region in the second element region in the semiconductor substrate by adopting an ion implantation process, wherein the implantation dosage is 1 multiplied by 10 13 /cm 2 ~1×10 14 /cm 2 Between them.
3. The method of manufacturing a semiconductor device according to claim 1, wherein forming the first element first conductivity type region in the semiconductor substrate includes: forming the first element first conductive type region in the semiconductor substrate by ion implantation, wherein the implantation dosage is 1×10 12 /cm 2 ~1×10 13 /cm 2 Between them.
4. The method of manufacturing a semiconductor device according to claim 1, wherein forming the first conductivity type ohmic contact region in the second element region in the semiconductor substrate through the first opening comprises: forming the first conductive type ohmic contact region in the semiconductor substrate through the first opening by adopting an ion implantation process, wherein the implantation energy is 15 keV-100 keV, and the implantation dosage is 1 multiplied by 10 14 /cm 2 ~5×10 15 /cm 2 Between them.
5. The method of manufacturing a semiconductor device according to claim 1, further comprising, before the first element region in the semiconductor substrate forms the first element first conductivity type region: a first element heavily doped second conductivity type region is formed in the semiconductor substrate in the first element region, the first element heavily doped second conductivity type region being located below the first element first conductivity type region.
6. The method of manufacturing a semiconductor device according to claim 5, wherein forming the first element heavily doped second conductivity type region in the semiconductor substrate at the first element region comprises: the first element region forms the first element heavily doped second conductivity type region within the semiconductor substrate, the second element region forms a second element heavily doped second conductivity type region, and the second element heavily doped second conductivity type region is located below the first conductivity type channel region.
7. The method of manufacturing a semiconductor device according to claim 1, further comprising, before the second element region forms the first conductivity type channel region in the semiconductor substrate: forming a second element heavily doped second conductivity type region in the semiconductor substrate in the second element region, the second element heavily doped second conductivity type region being located below the first conductivity type channel region.
8. The method for manufacturing a semiconductor device according to claim 1, further comprising: electron irradiation, platinum doping, or helium irradiation is employed to reduce minority carrier lifetime of the first element.
9. A semiconductor device manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 8.
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| CN106803498A (en) * | 2017-01-18 | 2017-06-06 | 株洲中车时代电气股份有限公司 | A kind of inverse preparation method for leading IGBT device |
| CN108389902B (en) * | 2018-04-28 | 2020-06-26 | 四川大学 | Reverse conducting IGBT with back groove grid |
| CN110797403B (en) * | 2019-10-18 | 2023-08-01 | 上海睿驱微电子科技有限公司 | RC-IGBT semiconductor device |
| CN111244171A (en) * | 2020-03-23 | 2020-06-05 | 嘉兴斯达半导体股份有限公司 | Trench RC-IGBT device structure and manufacturing method thereof |
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| JP7486373B2 (en) * | 2020-07-29 | 2024-05-17 | 三菱電機株式会社 | Semiconductor Device |
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| US20200006538A1 (en) * | 2018-06-27 | 2020-01-02 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |
| CN111211168A (en) * | 2020-01-13 | 2020-05-29 | 上海擎茂微电子科技有限公司 | RC-IGBT chip and manufacturing method thereof |
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