CN104022162B - Isolated form lateral Zener diode and its manufacture method in BCD techniques - Google Patents
Isolated form lateral Zener diode and its manufacture method in BCD techniques Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 144
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 230000005516 deep trap Effects 0.000 claims abstract description 57
- 238000002347 injection Methods 0.000 claims abstract description 54
- 239000007924 injection Substances 0.000 claims abstract description 54
- 238000000926 separation method Methods 0.000 claims abstract description 13
- 230000015556 catabolic process Effects 0.000 claims abstract description 12
- 238000005516 engineering process Methods 0.000 claims description 34
- 238000002513 implantation Methods 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000002019 doping agent Substances 0.000 claims description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000009897 systematic effect Effects 0.000 abstract description 4
- 238000011982 device technology Methods 0.000 abstract 1
- 239000003381 stabilizer Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 4
- 230000000087 stabilizing effect Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 108010063955 thrombin receptor peptide (42-47) Proteins 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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Abstract
The invention discloses the isolated form lateral Zener diode in a kind of BCD techniques, including N-type deep trap；N-type region and p type island region be formed in the first active area surrounded by high pressure p-well and p-well, and be made up of N and p-type source and drain injection region respectively, N-type region and p type island region are transversely arranged and be separated by lateral separation one, doped region by N-type region and p type island region and between the two constitutes the PN junction of isolated form lateral Zener diode, and the breakdown voltage of isolated form lateral Zener diode is adjusted by adjusting lateral separation one；Low pressure N trap, is formed in the N-type deep trap outside the first active area, and surface is formed with the N-type deep trap draw-out area being made up of N-type source and drain injection region.The invention also discloses a kind of manufacture method of the isolated form lateral Zener diode in BCD techniques.Device technology of the present invention can be good with BCD techniques it is integrated, process costs can not only be reduced, moreover it is possible to be improved the systematic function and reliability of whole integrated circuit.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufactures field, the isolated form in more particularly to a kind of BCD techniques is horizontal
Zener diode.The invention further relates to a kind of manufacture method of the isolated form lateral Zener diode in BCD techniques.
Background technology
Zener diode is typically used as voltage-stabiliser tube, is also a kind of crystal diode.It is that have using the breakdown region of PN junction
The characteristic of burning voltage carrys out work.Voltage-stabiliser tube is widely applied in pressure stabilizing device and some electronic circuits.This
The diode of type is referred to as voltage-stabiliser tube, to distinguish the diode used in rectification, detection and other unilateal conduction occasions.Two pole of voltage stabilizing
Pipe the characteristics of be exactly puncture after, the voltage at its two ends is held essentially constant.So, after voltage-stabiliser tube is accessed circuit, if by
Occur to fluctuate in supply voltage, or other reasons, when causing each point variation in voltage in circuit, the voltage for loading two ends will be protected substantially
Hold constant.After voltage-stabiliser tube reverse breakdown, although electric current changes in very large range, the voltage change very little at voltage-stabiliser tube two ends.
Using this characteristic, voltage-stabiliser tube can play pressure stabilization function in circuit.Because this characteristic, voltage-stabiliser tube be mainly incorporated as voltage-stablizer or
Voltage reference device is used.Its C-V characteristic is shown in that Zener diode can be together in series to use on higher voltage, leads to
Cross series connection and be achieved with more burning voltages.
Isolated form lateral Zener diode can realize the loading of generating positive and negative voltage, rather than be only restricted in loading positive voltage or
Person's negative voltage.
BCD techniques are a kind of monolithic integration process technologies, take the lead in succeeding in developing by STMicw Electronics (ST) company within 1986,
This technology can make bipolar transistor on the same chip（Bipolar）, complementary metal oxide semiconductors (CMOS)（CMOS）
And double-diffusion metal-oxide-semiconductor field effect transistor（DMOS）Device.BCD techniques are made Bipolar and cmos device simultaneously
On the same chip, it combines bipolar transistor device high transconductance, strong load driving force and the high and low work(of CMOS integrated levels
The advantage of consumption so as to make up for each other's deficiencies and learn from each other, plays respective advantage.What is more important, it is integrated with DMOS power devices,
DMOS can be worked in switching mode, and power consumption is extremely low.Encapsulation and cooling system that need not be expensive just can be by high-power biographies
Pass load.Low-power consumption is one of major advantage for BCD techniques.The BCD manufacturing process integrated, can be greatly reduced power
Consume, improves systematic function, saves the encapsulation overhead of circuit, and has more preferable reliability.
Due to extensive application of the voltage-stabiliser tube in pressure stabilizing device and some electronic circuits, if it is possible to which isolated form is laterally neat
Receive diode and BCD techniques integrate realization, it will further reduces cost, improve the performance and reliability of circuit system
Property.
The content of the invention
The technical problem to be solved is to provide the isolated form lateral Zener diode in a kind of BCD techniques, energy
Good integrated of enough and BCD techniques, can not only reduce process costs, moreover it is possible to make the systematic function and reliability of whole integrated circuit
Property is improved.For this purpose, the present invention also provides a kind of manufacture method of the isolated form lateral Zener diode in BCD techniques.
To solve above-mentioned technical problem, the isolated form lateral Zener diode in the BCD techniques that the present invention is provided includes：
N-type deep trap, is formed in Semiconductor substrate and for realizing the isolation of isolated form lateral Zener diode.
Fleet plough groove isolation structure is formed with the semiconductor substrate and active area is isolated by the shallow trench.
High pressure p-well, surrounds in being formed at the N-type deep trap and by the N-type deep trap, and the high pressure p-well surrounds an institute
Active area is stated, the first active area is defined as by the active area surrounded by the high pressure p-well.
P-well, the junction depth of the p-well are superimposed upon in the high pressure p-well less than the junction depth and the p-well of the high pressure p-well,
Bottom depth of the junction depth of the p-well more than shallow trench isolation, the p-well surround first active area.
N-type region, the N-type source and drain injection region composition being formed from first active area；P type island region, is formed from described
P-type source and drain injection region composition in first active area；The N-type region and the p type island region are transversely arranged in first active area
Surface in and be separated by lateral separation one, by the N-type region and the p type island region and be located at the N-type region and the p type island region it
Between and the region one for being formed be superimposed by the p-well and the high pressure p-well constitute the isolated form lateral Zener diode
PN junction, adjusts the breakdown voltage of the isolated form lateral Zener diode by adjusting the lateral separation one.
Low pressure N trap, in being formed at the N-type deep trap and outside first active area, on the low pressure N trap surface
It is formed with the N-type deep trap draw-out area being made up of N-type source and drain injection region.
Further improve, in the process conditions and BCD techniques of the N-type deep trap of the isolated form lateral Zener diode
DMOS devices N-type deep trap process conditions it is identical；The technique of the low pressure N trap of the isolated form lateral Zener diode
Condition is identical with the process conditions of the low pressure N trap of the DMOS devices in BCD techniques.
Further improve, the technique of the high pressure p-well of the DMOS devices in the process conditions and BCD techniques of the high pressure p-well
Condition is identical；The process conditions of the p-well are identical with the process conditions of the p-well of the DMOS devices in the BCD techniques.
Further improve, the process conditions of the N-type source and drain injection region of the N-type region and the N-type deep trap draw-out area all and
The process conditions of the N-type source and drain injection region of the cmos device in the BCD techniques are identical；The p-type source and drain injection region of the p type island region
Process conditions it is identical with the process conditions of the p-type source and drain injection region of the cmos device in the BCD techniques.
To solve above-mentioned technical problem, the manufacture of the isolated form lateral Zener diode in the BCD techniques that the present invention is provided
Method comprises the steps：
Step one, N-type deep trap is formed on a semiconductor substrate using ion implantation technology.
Step 2, defined using photoetching process isolated form lateral Zener diode high pressure p-well forming region, carry out
First p-type ion implantation technology forms high pressure p-well in the N-type deep trap of the forming region of the high pressure p-well.
Step 3, fleet plough groove isolation structure is formed on the semiconductor substrate, isolated by the shallow trench
Source region, the high pressure p-well surround an active area, are defined as first by the active area surrounded by the high pressure p-well active
Area.
Step 4, carry out the second p-type ion implantation technology p-well, the P are formed in the forming region of the high pressure p-well
The junction depth of trap is superimposed upon in the high pressure p-well less than the junction depth and the p-well of the high pressure p-well, and the junction depth of the p-well is more than
The bottom depth of the shallow trench isolation, the p-well surround first active area；The first N-type ion implanting is carried out described
Low pressure N trap is formed in the N-type deep trap outside first active area.
Step 5, carry out the injection of N-type source and drain and simultaneously form N-type region and N-type deep trap draw-out area, the N-type region is positioned at described
In the surface of the first active area；The N-type deep trap draw-out area is located at the low pressure N trap surface.
Carry out p-type source and drain to inject to form p type island region, the p type island region is located in the surface of first active area；The N-type
The area and p type island region is transversely arranged in the surface of first active area and is separated by lateral separation one, by the N-type region, institute
State p type island region and between the N-type region and the p type island region and be superimposed and formed by the p-well and the high pressure p-well
Region one constitutes the PN junction of the isolated form lateral Zener diode, adjusts the isolated form by adjusting the lateral separation one
The breakdown voltage of lateral Zener diode.
Further improve, the ion implantation technology of N-type deep trap described in step one is using the DMOS devices in BCD techniques
N-type deep trap injects；Low pressure N trap injection of the first N-type ion implanting described in step 4 using the DMOS devices in BCD techniques.
Further improve, high pressure of the first p-type ion implanting in step 2 using the DMOS devices in BCD techniques
P-well is injected；P-well injection of the second p-type ion implanting in step 4 using the DMOS devices in BCD techniques.
Further improve, the process conditions for forming the first p-type ion implanting of the high pressure p-well are：Implanted dopant
For boron, Implantation Energy is 200keV～260keV, and implantation dosage is 2.0E12cm-2～5.0E12cm-2；Form the institute of the p-well
The process conditions for stating the second p-type ion implanting are：Implanted dopant is boron, and Implantation Energy is 80keV～140keV, and implantation dosage is
8.0E12cm-2～12E12cm-2。
Further improve, N-type source and drain of the N-type source and drain injection in step 5 using the cmos device in BCD techniques
Injection；P-type source and drain injection of the p-type source and drain injection using the cmos device in the BCD techniques.
Further improve, the process conditions of the N-type source and drain injection are：Implanted dopant is arsenic, Implantation Energy be 50keV～
70keV, implantation dosage are 4.0E15cm-2～6.0E15cm-2；The process conditions of p-type source and drain injection are：Implanted dopant is
Boron, Implantation Energy are 13keV～17keV, and implantation dosage is 4.0E15cm-2～6.0E15cm-2。
The structure of isolated form lateral Zener diode of the present invention enables to constitute each of isolated form lateral Zener diode
Functional area process conditions are identical with the various process conditions in BCD techniques such that it is able to realize horizontal two pole of Zener of isolated form
Pipe and good integrated of BCD techniques, can not only reduce process costs, moreover it is possible to make the systematic function and reliability of whole integrated circuit
Property is improved.Isolated form lateral Zener diode of the present invention realizes isolation by N-type deep trap, imitates with good isolation
Really.Breakdown voltage of the lateral separation with regard to energy adjusting means by adjusting N-type region and p type island region of the invention, the device for significantly facilitating
Breakdown voltage adjust, can realize being easy for preparing the device with different breakdown voltages on same silicon chip.
Description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the structural representation of the isolated form lateral Zener diode in embodiment of the present invention BCD technique；
Fig. 2A-Fig. 2 E are the device architecture schematic diagrames in each step of present invention method.
Specific embodiment
As shown in figure 1, being the structural representation of the isolated form lateral Zener diode in embodiment of the present invention BCD technique；
Isolated form lateral Zener diode in embodiment of the present invention BCD technique includes：
N-type deep trap 3, is formed in Semiconductor substrate and for realizing the isolation of isolated form lateral Zener diode.This
Described in bright embodiment, the structure of Semiconductor substrate includes：P-type silicon substrate 1, the n type buried layer 2 formed on the silicon substrate 1,
And the p-type epitaxial layer formed in the surface of the silicon substrate 1 for being formed with the n type buried layer 2；The N-type deep trap 3 leads to
Cross ion implantation technology to be formed in the p-type epitaxial layer.The institute of the isolated form Zener diode in embodiments of the present invention
The process conditions for stating N-type deep trap 3 are identical with the process conditions of the N-type deep trap of the DMOS devices in BCD techniques；So that described
The N-type deep trap of the DMOS devices in the N-type deep trap 3 of isolated form Zener diode and BCD techniques can integrate shape
Into.
It is formed with shallow trench on the semiconductor substrate to isolate 5 structures and isolated by shallow trench isolation 5 active
Area.
High pressure p-well 4, surrounds in being formed at the N-type deep trap 3 and by the N-type deep trap 3, and the high pressure p-well 4 surrounds one
The individual active area, is defined as the first active area by the active area surrounded by the high pressure p-well 4.The technique of the high pressure p-well 4
Condition is identical with the process conditions of the high pressure p-well of the DMOS devices in BCD techniques.
P-well 6, the junction depth of the p-well 6 less than the high pressure p-well 4 junction depth and the p-well 6 is superimposed upon the high pressure p-well
In 4, the junction depth of the p-well 6 isolates 5 bottom depth more than the shallow trench, and the p-well 6 surrounds first active area.Institute
The process conditions for stating p-well 6 are identical with the process conditions of the p-well of the DMOS devices in the BCD techniques.
N-type region 9a, the N-type source and drain injection region composition being formed from first active area.
P type island region 8, the p-type source and drain injection region composition being formed from first active area；N-type region 9a and the P
Type area 8 is transversely arranged in the surface of first active area and to be separated by one S of lateral separation, by N-type region 9a and the p-type
Area 8 and between N-type region 9a and the p type island region 8 and be to be superimposed and formed by the p-well 6 and the high pressure p-well 4
Region one constitute the PN junction 10 of the isolated form lateral Zener diode, adjust described by adjusting one S of lateral separation
The breakdown voltage of isolated form lateral Zener diode.
Low pressure N trap 7, in being formed at the N-type deep trap 3 and outside first active area, in the low pressure N trap 7
Surface is formed with the N-type deep trap draw-out area 9b being made up of N-type source and drain injection region.The isolated form lateral Zener diode it is described
The process conditions of low pressure N trap 7 are identical with the process conditions of the low pressure N trap of the DMOS devices in BCD techniques.
The process conditions of the N-type source and drain injection region of N-type region 9a and the N-type deep trap draw-out area 9b all with the BCD
The process conditions of the N-type source and drain injection region of the cmos device in technique are identical；The technique of the p-type source and drain injection region of the p type island region 8
Condition is identical with the process conditions of the p-type source and drain injection region of the cmos device in the BCD techniques.
As shown in Fig. 2A to Fig. 2 E, be present invention method each step in device architecture schematic diagram.The present invention
The manufacture method of the isolated form lateral Zener diode in embodiment BCD technique comprises the steps：
Step one, as shown in Figure 2 A, first provides semi-conductive substrate, and P-type silicon substrate 1 is selected in the embodiment of the present invention；
N type buried layer 2 is made on the silicon substrate 1, p-type epitaxial layer is formed on the n type buried layer 2 using epitaxial growth technology afterwards.
N-type deep trap 3 is formed on the p-type epitaxial layer using ion implantation technology.The ion implantation technology of the N-type deep trap 3 is adopted
DMOS devices in BCD techniques N-type deep trap injection, in isolated form lateral Zener diode and integrated BCD techniques, it is described every
The N-type deep trap 3 of release lateral Zener diode can be formed together with the N-type deep trap of the DMOS devices in the BCD techniques,
The concrete technology condition of the ion implantation technology of the N-type deep trap 3 is：Implanted dopant is phosphorus, Implantation Energy be 400keV～
440keV, implantation dosage are 1.0E13cm-2～1.5E13cm-2。
Step 2, as shown in Figure 2 B, defines the high pressure p-well 4 of isolated form lateral Zener diode using photoetching process
Forming region, carries out the first p-type ion implantation technology and is formed in the N-type deep trap 3 of the forming region of the high pressure p-well 4
High pressure p-well 4.High pressure p-well injection of the first p-type ion implanting using the DMOS devices in BCD techniques, and the high pressure p-well
The concrete technology condition of injection is：Implanted dopant is boron, and Implantation Energy is 200keV～260keV, and implantation dosage is
2.0E12cm-2～5.0E12cm-2.In isolated form lateral Zener diode and integrated BCD techniques, the isolated form is laterally neat
Receive diode the high pressure p-well 4 can and the BCD techniques in the high pressure p-well of DMOS devices be formed together.
Step 3, as shown in Figure 2 C, forms shallow trench on the semiconductor substrate and isolates 5 structures, by the shallow trench
Isolation 5 isolates active area, and the high pressure p-well 4 surrounds an active area, the active area surrounded by the high pressure p-well 4
It is defined as the first active area.
Step 4, as shown in Figure 2 D, carries out the second p-type ion implantation technology shape in the forming region of the high pressure p-well 4
Into p-well 6, the junction depth of the p-well 6 is superimposed upon in the high pressure p-well 4 less than the junction depth and the p-well 6 of the high pressure p-well 4, institute
The bottom depth of the junction depth more than shallow trench isolation 5 of p-well 6 is stated, the p-well 6 surrounds first active area.Described second
P-type ion implanting forms the second p-type ion implanting of the p-well using the p-well injection of the DMOS devices in BCD techniques
That is the concrete technology condition of p-well injection is：Implanted dopant is boron, and Implantation Energy is 80keV～140keV, and implantation dosage is
8.0E12cm-2～12E12cm-2。
As shown in Figure 2 E, formed in carrying out the N-type deep trap 3 of the first N-type ion implanting outside first active area
Low pressure N trap 7.Low pressure N trap injection of the first N-type ion implanting using the DMOS devices in BCD techniques, the low pressure N trap 7
The concrete technology condition of ion implantation technology be：Implanted dopant is phosphorus, and Implantation Energy is 100keV～160keV, implantation dosage
For 3.0E12cm-2～6.0E12cm-2。
In isolated form lateral Zener diode and integrated BCD techniques, the P of the isolated form lateral Zener diode
Trap 6 can be formed together with the p-well of the DMOS devices in the BCD techniques；The isolated form lateral Zener diode it is described low
Pressure N traps 7 can be formed together with the low pressure N trap of the DMOS devices in the BCD techniques.
Step 5, as shown in figure 1, carry out the injection of N-type source and drain simultaneously formation N-type region 9a and N-type deep trap draw-out area 9b, it is described
N-type region 9a is located in the surface of first active area；The N-type deep trap draw-out area 9b is located at 7 surface of low pressure N trap.
Carry out p-type source and drain to inject to form p type island region 8, the p type island region 8 is located in the surface of first active area；The N
The type area 9a and p type island region 8 is transversely arranged in the surface of first active area and is separated by one S of lateral separation, by the N-type
Area 9a, the p type island region 8 and between N-type region 9a and the p type island region 8 and be by the p-well 6 and the high pressure P
The region one that the superposition of trap 4 is formed constitutes the PN junction 10 of the isolated form lateral Zener diode, by adjusting the lateral separation
One S adjusts the breakdown voltage of the isolated form lateral Zener diode.
N-type source and drain injection of the N-type source and drain injection using the cmos device in BCD techniques, the N-type source and drain injection
Process conditions are：Implanted dopant is arsenic, and Implantation Energy is 50keV～70keV, and implantation dosage is 4.0E15cm-2～6.0E15cm-2.P-type source and drain injection of the p-type source and drain injection using the cmos device in the BCD techniques, the work of the p-type source and drain injection
Skill condition is：Implanted dopant is boron, and Implantation Energy is 13keV～17keV, and implantation dosage is 4.0E15cm-2～6.0E15cm-2。
In isolated form lateral Zener diode and integrated BCD techniques, N-type region 9a of the isolated form lateral Zener diode and
N-type deep trap draw-out area 9b can be formed together with the N-type source and drain injection region of the cmos device in the BCD techniques；The isolation
The p type island region 8 of type lateral Zener diode can be with the p-type source and drain injection region of the cmos device in the BCD techniques together shape
Into.
The present invention is described in detail above by specific embodiment, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (9)
1. the isolated form lateral Zener diode in a kind of BCD techniques, it is characterised in that include：
N-type deep trap, is formed in Semiconductor substrate and for realizing the isolation of isolated form lateral Zener diode；
Fleet plough groove isolation structure is formed with the semiconductor substrate and active area is isolated by the shallow trench；
High pressure p-well, surrounds in being formed at the N-type deep trap and by the N-type deep trap, has described in the high pressure p-well encirclement one
Source region, is defined as the first active area by the active area surrounded by the high pressure p-well；
P-well, the junction depth of the p-well are superimposed upon in the high pressure p-well less than the junction depth and the p-well of the high pressure p-well, the P
Bottom depth of the junction depth of trap more than shallow trench isolation, the p-well surround first active area；
N-type region, is formed in first active area using the N-type source and drain injection technology of the cmos device in BCD techniques；P-type
Area, is formed in first active area using the p-type source and drain injection technology of the cmos device in BCD techniques；The N-type region and
The p type island region is transversely arranged in the surface of first active area and to be separated by lateral separation one, by the N-type region and the P
Type area and between the N-type region and the p type island region and be that the area for being formed is superimposed by the p-well and the high pressure p-well
Domain one constitutes the PN junction of the isolated form lateral Zener diode, adjusts the isolated form horizontal stroke by adjusting the lateral separation one
To the breakdown voltage of Zener diode；
Low pressure N trap, in being formed at the N-type deep trap and outside first active area, forms on the low pressure N trap surface
There is N-type deep trap draw-out area, N-type deep trap draw-out area is formed using the N-type source and drain injection technology of the cmos device in BCD techniques.
2. the isolated form lateral Zener diode in BCD techniques as claimed in claim 1, it is characterised in that：The isolated form is horizontal
To the process conditions phase of the N-type deep trap of the DMOS devices in the process conditions and BCD techniques of the N-type deep trap of Zener diode
Together；The low pressure of the DMOS devices in the process conditions and BCD techniques of the low pressure N trap of the isolated form lateral Zener diode
The process conditions of N traps are identical.
3. the isolated form lateral Zener diode in BCD techniques as claimed in claim 1, it is characterised in that：The high pressure p-well
Process conditions are identical with the process conditions of the high pressure p-well of the DMOS devices in BCD techniques；Process conditions of the p-well and described
The process conditions of the p-well of the DMOS devices in BCD techniques are identical.
4. the isolated form lateral Zener diode in BCD techniques as claimed in claim 1, it is characterised in that：The N-type region and institute
State the process conditions of N-type deep trap draw-out area all with the BCD techniques in cmos device N-type source and drain injection region process conditions
It is identical；The process conditions phase of the p-type source and drain injection region of the cmos device in the process conditions of the p type island region and the BCD techniques
Together.
5. the manufacture method of the isolated form lateral Zener diode in a kind of BCD techniques, it is characterised in that comprise the steps：
Step one, N-type deep trap is formed on a semiconductor substrate using ion implantation technology；
Step 2, defined using photoetching process isolated form lateral Zener diode high pressure p-well forming region, carry out first
P-type ion implantation technology forms high pressure p-well in the N-type deep trap of the forming region of the high pressure p-well；
Step 3, fleet plough groove isolation structure is formed on the semiconductor substrate, active area is isolated by the shallow trench,
The high pressure p-well surrounds an active area, is defined as the first active area by the active area surrounded by the high pressure p-well；
Step 4, carry out the second p-type ion implantation technology p-well is formed in the forming region of the high pressure p-well, the p-well
Junction depth is superimposed upon in the high pressure p-well less than the junction depth and the p-well of the high pressure p-well, and the junction depth of the p-well is more than described
The bottom depth of shallow trench isolation, the p-well surround first active area；The first N-type ion implanting is carried out described first
Low pressure N trap is formed in the N-type deep trap outside active area；
Step 5, N-type region is simultaneously formed using the N-type source and drain injection technology of the cmos device in BCD techniques and N-type deep trap is drawn
Area, the N-type region are located in the surface of first active area；The N-type deep trap draw-out area is located at the low pressure N trap surface；
P type island region is formed using the p-type source and drain injection technology of the cmos device in BCD techniques, the p type island region has positioned at described first
In the surface of source region；The N-type region and the p type island region it is transversely arranged in the surface of first active area and be separated by laterally away from
It is from one, by the N-type region, the p type island region and between the N-type region and the p type island region and be by the p-well and institute
State high pressure p-well and be superimposed the PN junction that the region one to be formed constitutes the isolated form lateral Zener diode, it is described horizontal by adjusting
Distance one adjusts the breakdown voltage of the isolated form lateral Zener diode.
6. method as claimed in claim 5, it is characterised in that：The ion implantation technology of N-type deep trap described in step one is adopted
The N-type deep trap injection technology of the DMOS devices in BCD techniques；First N-type ion implanting described in step 4 is using in BCD techniques
DMOS devices low pressure N trap injection technology.
7. method as claimed in claim 5, it is characterised in that：The first p-type ion implanting in step 2 adopts BCD works
The high pressure p-well injection technology of the DMOS devices in skill；The second p-type ion implanting in step 4 is using in BCD techniques
The p-well injection technology of DMOS devices.
8. method as claimed in claim 7, it is characterised in that：Form the first p-type ion implanting of the high pressure p-well
Process conditions are：Implanted dopant is boron, and Implantation Energy is 200keV～260keV, and implantation dosage is 2.0E12cm-2~
5.0E12cm-2；
The process conditions for forming the second p-type ion implanting of the p-well are：Implanted dopant is boron, and Implantation Energy is 80keV
～140keV, implantation dosage are 8.0E12cm-2～12E12cm-2。
9. method as claimed in claim 5, it is characterised in that：The process conditions of the N-type source and drain injection technology are：Injection is miscellaneous
Matter is arsenic, and Implantation Energy is 50keV～70keV, and implantation dosage is 4.0E15cm-2～6.0E15cm-2；
The process conditions of the p-type source and drain injection technology are：Implanted dopant is boron, and Implantation Energy is 13keV～17keV, is injected
Dosage is 4.0E15cm-2～6.0E15cm-2。
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| CN106158924A (en) * | 2015-04-16 | 2016-11-23 | 北大方正集团有限公司 | A kind of Zener diode and preparation method thereof |
| CN109148563A (en) * | 2018-08-31 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | The preparation method and Zener diode of Zener diode |
| CN112103333A (en) * | 2020-11-19 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor structure and manufacturing method thereof |
| CN113192840A (en) * | 2021-04-27 | 2021-07-30 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN117542899A (en) * | 2023-11-27 | 2024-02-09 | 遵义筑芯威半导体技术有限公司 | Structure and manufacturing method of voltage stabilizing tube chip |
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