CN112802742A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN112802742A
CN112802742A CN202110314445.7A CN202110314445A CN112802742A CN 112802742 A CN112802742 A CN 112802742A CN 202110314445 A CN202110314445 A CN 202110314445A CN 112802742 A CN112802742 A CN 112802742A
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oxide layer
semiconductor device
manufacturing
gate
substrate
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李娜
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, and forming a groove on the substrate; performing a thermal oxidation growth process with the process temperature of 950-1100 ℃ to form a sacrificial oxide layer on the inner wall of the trench; removing the sacrificial oxide layer; and performing a thermal oxidation growth process with the process temperature of 1100-1200 ℃ to form a gate oxide layer on the inner wall of the groove. The manufacturing method of the semiconductor device enables the bottom of the groove to be more smooth by improving the process parameters when the sacrificial oxide layer and the gate oxide layer are formed by the thermal oxidation growth process, and simultaneously improves the thickness uniformity of the gate oxide layer, thereby optimizing the performance of the semiconductor device.

Description

Method for manufacturing semiconductor device
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power Semiconductor device composed of a Bipolar Junction Transistor (BJT) and an Insulated Gate Field Effect Transistor (MOS), and has the advantages of high input impedance of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and low on-state voltage drop of a power Transistor (Giant Transistor, GTR).
The back side process of the IGBT device has undergone a development process from a Punch-Through (PT) type to a Non-Punch-Through (NPT) type to a Field Stop (FS) type. The front side process of the IGBT device has a development process from planar (planar) to trench gate (trench gate). In recent years, the IGBT device is rapidly developed from a large-sized fine trench (trench pitch) to a small-sized fine trench (trench pitch), so that the power density of the IGBT device is greatly improved, and the conduction loss and the switching loss of the IGBT device are reduced.
However, as the size of IGBT devices continues to decrease, the prior art fails to meet increasingly stringent process requirements. Referring to fig. 1, when the width of the trench in the IGBT device is reduced to below 1um, the bottom of the trench 100 becomes sharp, thereby affecting the stability of the topography of the IGBT device and further affecting the product performance. In addition, in the conventional gate oxide layer manufacturing process of the IGBT device, the process temperature of the thermal oxidation growth process is usually between 950 ℃ and 1100 ℃, the gate oxide layer 110 grown at the bottom of the trench 100 is thinner than the gate oxide layer 110 grown on the side wall of the trench 100, and the breakdown voltage of the IGBT device may be affected due to the uneven thickness of the gate oxide layer 110.
Therefore, a method is needed to improve the performance of fine trench IGBT devices.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which enables the bottom of a groove to be more smooth by improving the growth process parameters of a sacrificial oxide layer and a gate oxide layer and improves the thickness uniformity of the gate oxide layer.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising:
providing a substrate, and forming a groove in the substrate;
performing a thermal oxidation growth process with the process temperature of 950-1100 ℃ to form a sacrificial oxide layer on the inner wall of the trench;
removing the sacrificial oxide layer;
and performing a thermal oxidation growth process with the process temperature of 1100-1200 ℃ to form a gate oxide layer on the inner wall of the groove.
Optionally, the width of the trench comprises 0.5um to 1.5 um.
Optionally, a wet etching process is used to remove the sacrificial oxide layer.
Optionally, the thickness range of the sacrificial oxide layer includes
Figure BDA0002991151920000021
Optionally, the thickness range of the gate oxide layer comprises
Figure BDA0002991151920000022
Optionally, after forming the gate oxide layer, the method further includes:
forming a gate material layer in the groove, wherein the gate material layer fills the groove and extends to cover the surface of the substrate;
and etching to remove the gate material layer on the surface of the substrate, wherein the rest gate material layer forms a gate.
Optionally, the material of the gate material layer includes polysilicon.
Optionally, the sacrificial oxide layer and the gate oxide layer are made of the same material and both include silicon dioxide.
Optionally, the substrate comprises a silicon substrate.
Optionally, the manufacturing method of the semiconductor device is used for manufacturing an IGBT device.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, and forming a groove in the substrate; performing a thermal oxidation growth process with the process temperature of 950-1100 ℃ to form a sacrificial oxide layer on the inner wall of the trench; removing the sacrificial oxide layer; and performing a thermal oxidation growth process with the process temperature of 1100-1200 ℃ to form a gate oxide layer on the inner wall of the groove. The manufacturing method of the semiconductor device enables the bottom of the groove to be more smooth by improving the process parameters when the sacrificial oxide layer and the gate oxide layer are formed by the thermal oxidation growth process, and simultaneously improves the thickness uniformity of the gate oxide layer, thereby optimizing the performance of the semiconductor device.
Drawings
FIG. 1 is a schematic view of a trench profile of an IGBT device with a trench width of 1 um;
FIG. 2 is a schematic diagram of the topography of a gate oxide layer formed by a thermal oxidation growth process at 950 ℃ -1100 ℃;
fig. 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 to 8 are structural diagrams corresponding to respective steps in the manufacturing method of the semiconductor device according to the present embodiment;
wherein the reference numbers are as follows:
100-a trench; 110-gate oxide layer;
200-a substrate; 210-a trench; 220-sacrificial oxide layer; 230-a gate oxide layer; 240-gate.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the invention. Referring to fig. 3, the method for manufacturing a semiconductor device includes:
step S01: providing a substrate, and forming a groove in the substrate;
step S02: performing a thermal oxidation growth process with the process temperature of 950-1100 ℃ to form a sacrificial oxide layer on the inner wall of the trench;
step S03: removing the sacrificial oxide layer;
step S04: and performing a thermal oxidation growth process with the process temperature of 1100-1200 ℃ to form a gate oxide layer on the inner wall of the groove.
Fig. 4 to 8 are structural diagrams corresponding to respective steps in the method for manufacturing a semiconductor device provided in this embodiment, and the method for manufacturing a semiconductor device according to this embodiment will be described in detail with reference to fig. 4 to 8.
First, referring to fig. 4, step S01 is performed to provide a substrate 200, and a trench 210 is formed in the substrate 200. Specifically, a patterned photoresist layer (not shown in fig. 4) is formed on the surface of the substrate 200, and the substrate 200 is etched by using the patterned photoresist layer as a mask layer to form the trench 210. In other embodiments of the present invention, the trench 210 may be formed by other processes, which are well known to those skilled in the art and are not listed here. In this embodiment, the substrate 200 is a silicon substrate. Optionally, the width of the trench 210 includes 0.5 μm to 1.5 μm.
Next, referring to fig. 5, in step S02, a thermal oxidation growth process is performed at a process temperature of 950 to 1100 ℃ to form a sacrificial oxide layer 220 on the inner wall of the trench 210. Specifically, a process gas is introduced into the reaction chamber at a temperature of 950 to 1100 ℃, and oxygen contained in the process gas reacts with the substrate 100 (i.e., a silicon substrate), so that a silicon dioxide layer (i.e., the sacrificial oxide layer 220) is formed on the inner wall of the trench 210. Optionally, the thickness range of the sacrificial oxide layer 220 includes
Figure BDA0002991151920000041
Since the thickness uniformity of the oxide layer formed by the thermal oxidation growth process is related to the process temperature, in step S02, the thickness of the portion of the sacrificial oxide layer 220 covering the bottom wall of the trench 210 is thinner than the portion covering the sidewall of the trench 210.
Subsequently, referring to fig. 6, step S03 is performed to remove the sacrificial oxide layer 220. In this embodiment, the sacrificial oxide layer 220 is removed by a wet etching process, and in other embodiments of the present invention, the sacrificial oxide layer 220 may be removed by other methods, which is not limited in the present invention.
As can be seen from a comparison between fig. 4 and fig. 6, when the thermal oxidation growth process is performed at a process temperature of 950-1100 ℃, the thickness of the portion of the generated sacrificial oxide layer 220 covering the bottom wall of the trench 210 is thinner than the portion of the sacrificial oxide layer 220 covering the sidewall of the trench 210, and after the sacrificial oxide layer 220 is removed, the bottom of the trench 210 becomes smooth, so that the bottom profile of the trench is effectively improved, which is helpful for improving the performance of the semiconductor device.
Next, referring to fig. 7, in step S04, a thermal oxidation growth process is performed at a process temperature of 1100 to 1200 ℃ to form a gate oxide layer 230 with a uniform thickness on the inner wall of the trench 210. Since the morphology and thickness uniformity of the gate oxide layer 230 are related to the temperature of the thermal oxidation growth process, the gate oxide layer 230 has good thickness uniformity. Optionally, the thickness range of the gate oxide layer 230 includes
Figure BDA0002991151920000042
Optionally, the sacrificial oxide layer 220 and the gate oxide layer 230 are made of the same material and both include silicon dioxide.
In addition, referring to fig. 8, after the gate oxide layer 230 is formed, the method of manufacturing the semiconductor device further includes: forming a gate material layer (not shown) in the trench 210, wherein the gate material layer fills the trench 210 and extends to cover the surface of the substrate 200; etching is performed to remove the gate material layer on the surface of the substrate 200, and the remaining gate material layer constitutes the gate 240. In this embodiment, the material of the gate material layer includes polysilicon. It should be noted that, in other embodiments of the present invention, the gate electrode 240 may be formed by other methods, for example, the gate electrode material layer is planarized to form the gate electrode 240, which is not limited in the present invention.
As can be seen from comparing fig. 2 and fig. 8, when a thermal oxidation growth process is performed at a process temperature of 950 to 1100 ℃ for a semiconductor device having a trench width of less than 1 μm, the thickness of the portion of the gate oxide layer 110 covering the bottom wall of the trench 100 is thinner than the portion covering the sidewall of the trench 100, which may result in a reduction in the breakdown voltage of the semiconductor device, thereby affecting the performance of the semiconductor device; when the thermal oxidation growth process with the process temperature of 1100-1200 ℃ is carried out, the generated gate oxide layer 230 has good thickness uniformity, the pressure resistance of the gate oxide layer 230 is improved, and the performance of the semiconductor device is further improved.
Therefore, the shapes of the groove and the gate oxide layer in the semiconductor device (especially the semiconductor device with the groove width less than 1 μm) manufactured by the method for manufacturing the semiconductor device are closer to the ideal shape in design, correspondingly, the performance of the semiconductor device manufactured by the method for manufacturing the semiconductor structure with optimized process parameters can better meet the design requirement, and the performance of the semiconductor device is more stable. In this embodiment, the semiconductor device is an IGBT device, and in other embodiments of the present invention, the semiconductor device may be other semiconductor devices having the same structure, which is not limited in the present invention.
In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, and forming a groove in the substrate; performing a thermal oxidation growth process with the process temperature of 950-1100 ℃ to form a sacrificial oxide layer on the inner wall of the trench; removing the sacrificial oxide layer; and performing a thermal oxidation growth process with the process temperature of 1100-1200 ℃ to form a gate oxide layer on the inner wall of the groove. The manufacturing method of the semiconductor device enables the bottom of the groove to be more smooth by improving the process parameters when the sacrificial oxide layer and the gate oxide layer are formed by the thermal oxidation growth process, and simultaneously improves the thickness uniformity of the gate oxide layer, thereby optimizing the performance of the semiconductor device.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, and forming a groove in the substrate;
performing a thermal oxidation growth process with the process temperature of 950-1100 ℃ to form a sacrificial oxide layer on the inner wall of the trench;
removing the sacrificial oxide layer;
and performing a thermal oxidation growth process with the process temperature of 1100-1200 ℃ to form a gate oxide layer on the inner wall of the groove.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a width of the trench includes 0.5um to 1.5 um.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial oxide layer is removed by a wet etching process.
4. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness range of the sacrificial oxide layer includes
Figure FDA0002991151910000011
5. The method of manufacturing a semiconductor device according to claim 1, wherein a thickness range of the gate oxide layer comprises
Figure FDA0002991151910000012
6. The method of manufacturing a semiconductor device according to claim 1, further comprising, after forming the gate oxide layer:
forming a gate material layer in the groove, wherein the gate material layer fills the groove and extends to cover the surface of the substrate;
and etching to remove the gate material layer on the surface of the substrate, wherein the rest gate material layer forms a gate.
7. The method for manufacturing a semiconductor device according to claim 6, wherein a material of the gate material layer includes polysilicon.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial oxide layer and the gate oxide layer are the same material and each comprise silicon dioxide.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate comprises a silicon substrate.
10. The manufacturing method of a semiconductor device according to claim 1, wherein the manufacturing method of a semiconductor device is used for manufacturing an IGBT device.
CN202110314445.7A 2021-03-24 2021-03-24 Method for manufacturing semiconductor device Pending CN112802742A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113643997A (en) * 2021-07-30 2021-11-12 天津环鑫科技发展有限公司 Groove shape monitoring method and structural device
CN113782589A (en) * 2021-08-31 2021-12-10 上海华虹宏力半导体制造有限公司 Process method of groove type power MOSFET device

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CN104347397A (en) * 2013-07-23 2015-02-11 无锡华润上华半导体有限公司 Manufacture method of injection enhanced type insulated gate bipolar transistor
CN104465754A (en) * 2013-09-25 2015-03-25 北大方正集团有限公司 Groove type DMOS unit, manufacturing method thereof and DMOS device
CN109904223A (en) * 2019-01-23 2019-06-18 上海华虹宏力半导体制造有限公司 The process of gate trench top chamfer
CN111933527A (en) * 2019-05-13 2020-11-13 上海先进半导体制造股份有限公司 Trench IGBT and manufacturing method thereof

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US20010006836A1 (en) * 1994-02-04 2001-07-05 Katsumi Nakamura Method of forming a trench mos gate on a power semiconductor device
EP1160852A2 (en) * 1994-02-04 2001-12-05 Mitsubishi Denki Kabushiki Kaisha Method of fabricating a trenched semiconductor device
KR20000025138A (en) * 1998-10-08 2000-05-06 김덕중 Method for fabricating semiconductor device
US20020006704A1 (en) * 2000-07-17 2002-01-17 Mosel Vitelic Inc. Process for forming gate oxide layer
US20060160306A1 (en) * 2005-01-17 2006-07-20 Min-San Huang Method for forming trench gate dielectric layer
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CN104465754A (en) * 2013-09-25 2015-03-25 北大方正集团有限公司 Groove type DMOS unit, manufacturing method thereof and DMOS device
CN109904223A (en) * 2019-01-23 2019-06-18 上海华虹宏力半导体制造有限公司 The process of gate trench top chamfer
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113643997A (en) * 2021-07-30 2021-11-12 天津环鑫科技发展有限公司 Groove shape monitoring method and structural device
CN113782589A (en) * 2021-08-31 2021-12-10 上海华虹宏力半导体制造有限公司 Process method of groove type power MOSFET device

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