JPH065619A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a high density and high speed vertical bipolar transistor. CONSTITUTION:The first groove part 5, reaching the N<+> type buried layer 2 which becomes a collector, is formed on the circumference of an emitter region and a base region in a vertical type NPN transistor, an oxide film 6 is formed on the side wall of the first groove part 5, and a polycrystalline silicon film 7 is formed on the side wall of the first groove part 5. Using the polycrystalline silion film 7 as a mask, the second groove part 8, reaching the semiconductor substrate 1 which becomes an element isolation region, is formed in the first groove part 5, and a CVD-SiO2 film 11 is buried therein. Then the emitter of the vertical type NPN transistor is formed, a part of the poly-crystalline silicon film 7 is formed into N<+> type, and a collector lead-out part is formed. As a result, the margin between the collector lead-out part and the element isolation region is unnecessitated, and the collector lead-out part is formed surrouding the emitter and base regions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a vertical NPN transistor and a vertical PNP transistor are integrated and a method of manufacturing the same, and particularly to a structure of an extraction electrode from a collector buried layer and an element isolation region. And its forming method.

[0002]

2. Description of the Related Art As a conventional semiconductor device, for example, 19
Proceedings of the 91st IEICE Spring National Convention 5-153
The ones shown in are known. FIG. 8 is a structural sectional view of a vertical NPN transistor of this conventional semiconductor device.

In FIG. 8, 51 is a P-type semiconductor substrate, 5
Reference numeral 2 is an N ⁺ -type buried layer which serves as a collector buried layer of the vertical NPN transistor. 53 is an N-type epitaxial layer,
54 is a SiO ₂ film serving as the separation region, the SiO ₂
The film is formed on the surface of the transistor and the groove that separates the transistors. Reference numeral 55 is an N ⁺ type polycrystalline silicon film, which serves as an extraction electrode from the N ⁺ type buried layer of the collector. Reference numeral 56 is an N ⁺ type diffusion layer which is a part of the collector, 57 is a P type diffusion layer which is a base, and 58 is an N ⁺ type diffusion layer which is an emitter. Reference numeral 59 is a P ⁺ -type polycrystalline silicon film which is a part of the base electrode, 60 is an N ⁺ -type polycrystalline silicon film which is a part of the emitter electrode, and 61, 62 and 63 are an emitter electrode, a base electrode and a collector electrode, respectively. is there.

In the conventional semiconductor device having such a structure, since the collector extraction electrode of the vertical NPN transistor is formed of the high-concentration N ⁺ -type polycrystalline silicon film 55, the collector resistance becomes small, and the collector resistance becomes small. The time required for charging and discharging at the base junction is shortened, and the transistor can operate at high speed.

[0005]

[Problems to be Solved by the Invention]
In a conventional semiconductor device, N serving as a collector extraction electrode is used.
⁺ In forming the type polycrystalline silicon film 55, N⁺ Mold embedding
The groove reaching the layer 52 is formed by photolithography and dry etching.
Process of forming a polysilicon film and filling
A step of incorporating is required. This complicates the manufacturing process.
Between the collector extraction electrode 55 and the transistor
SiO to be an element isolation region₂ Margin between the film 54
It is said that the transistor size will increase as it becomes necessary.
Had a problem.

An object of the present invention is to solve the above problems and to provide a high-density, high-speed vertical NPN transistor and a semiconductor device in which the vertical PNP transistor is integrated on the same wafer, and a manufacturing method thereof.

[0007]

In order to solve the above problems, a semiconductor device of the present invention comprises a first conductivity type buried layer and a first conductivity type buried layer formed on a semiconductor substrate of one conductivity type. A first semiconductor layer of opposite conductivity type formed on the semiconductor substrate, a first groove portion formed in the first semiconductor layer and reaching the first buried layer, and formed only on a sidewall of the first groove portion. A first insulating film, a second semiconductor layer of an opposite conductivity type formed in the first groove portion and in contact with the first buried layer, and a second semiconductor layer formed in the first groove portion and reaching the semiconductor substrate. Two trenches and at least a second insulating film formed in the second trench, the first buried layer is a vertical bipolar transistor collector, and the second semiconductor layer is a collector lead-out portion of a vertical bipolar transistor. And the second insulating film is Serial second semiconductor layer in contact, in which the second semiconductor layer is constructed so as to be in contact with the first insulating film.

In the semiconductor device of the present invention, a first conductivity type first buried layer formed on a semiconductor substrate of one conductivity type and a second conductivity type buried layer formed on the semiconductor substrate.
A first semiconductor layer of an opposite conductivity type formed on the semiconductor substrate including the first buried layer and the second buried layer; and the first buried layer and the second buried layer formed on the first semiconductor layer. A first groove portion reaching up to, a first insulating film formed only on a sidewall of the first groove portion, and formed in the first groove portion,
A second semiconductor layer of opposite conductivity type in contact with the first buried layer,
A third semiconductor layer of one conductivity type formed in the first groove portion and in contact with the second buried layer; a second groove portion formed in the first groove portion and reaching the semiconductor substrate;
At least a second insulating film formed in the groove,
The first buried layer serves as a collector of a vertical NPN transistor, the second semiconductor layer serves as a collector extraction portion of a vertical NPN transistor, the second buried layer serves as a collector of a vertical PNP transistor, and the third semiconductor layer serves as a collector. Vertical P
As a collector lead-out portion of an NP transistor, the second insulating film contacts the second semiconductor layer and the third semiconductor layer, the second semiconductor layer contacts the first insulating film, and the third semiconductor layer contacts the first insulating film. One is configured to be in contact with the insulating film.

The semiconductor device manufacturing method of the present invention is
Forming a reverse conductivity type first buried layer on a semiconductor substrate of one conductivity type; forming a reverse conductivity type first semiconductor layer on the semiconductor substrate including the first buried layer;
Forming a first groove in the semiconductor layer that reaches the first buried layer; forming a first insulating film only on the sidewall of the first groove; and forming a second insulating second film in the first groove. A step of forming a semiconductor layer in contact with the first buried layer, and a step of reaching the semiconductor substrate in the first groove portion
At least a step of forming a groove and a step of forming a second insulating film in the second groove, wherein the first buried layer serves as a collector of a vertical bipolar transistor,
The semiconductor layer is used as a collector extraction part of a vertical bipolar transistor, the second insulating film is in contact with the second semiconductor layer,
The second semiconductor layer is formed so as to be in contact with the first insulating film.

Furthermore, the manufacturing method of the present invention comprises the steps of forming a first buried layer of opposite conductivity type on a semiconductor substrate of one conductivity type, and forming a second buried layer of one conductivity type on the semiconductor substrate. Forming a first semiconductor layer of opposite conductivity type on the semiconductor substrate including the first buried layer and the second buried layer; and including the first buried layer and the second buried layer in the first semiconductor layer Forming a reaching first groove portion, forming a first insulating film only on the side wall of the first groove portion, and forming a second insulating film having a second conductivity type in contact with the first buried layer in the first groove portion.
Forming a semiconductor layer, and forming the second groove in the first groove.
A step of forming a third semiconductor layer of one conductivity type in contact with the buried layer; a step of forming a second groove part reaching the semiconductor substrate in the first groove part; and a second insulating film in the second groove part. And forming the first buried layer as a collector of a vertical NPN transistor, the second semiconductor layer as a collector extraction portion of the vertical NPN transistor, and the second buried layer of a vertical PNP transistor. As a collector, the third semiconductor layer is used as a collector extraction portion of a vertical PNP transistor, the second insulating film is in contact with the second semiconductor layer and the third semiconductor layer, and the second semiconductor layer is the first insulating film. And the third semiconductor layer is formed so as to be in contact with the first insulating film.

[0011]

According to the present invention, according to the above-described structure, the first groove portion reaching the collector buried layer is formed around the emitter and base regions of the bipolar transistor, and the insulating film is formed only on the side wall of the groove portion. A semiconductor layer serving as a collector extension is formed only on the side wall of the groove so as to be in contact with the film, and a second groove reaching the semiconductor substrate through the buried layer of the collector is formed using this semiconductor layer as a mask, An element isolation region is formed by embedding an insulating film. Therefore, it is not necessary to provide a margin between the element isolation region and the collector extraction region, unlike the conventional case.
Since a collector extraction region and a device isolation region that is finer than the processing accuracy of photolithography can be formed in the region that was conventionally used for device isolation by self-alignment, a high-density bipolar transistor can be realized with fewer manufacturing steps. . Furthermore, since the collector extraction electrode can be structured to surround the periphery of the emitter and base regions and the collector resistance can be reduced, the speed of the bipolar transistor can be increased.

In addition, the semiconductor layers formed on the sidewalls on both sides in the first trench are respectively N ⁺ type semiconductor layers by using the emitter diffusion of the vertical NPN transistor and the emitter diffusion of the vertical PNP transistor. By using the P ⁺ type semiconductor layer, the vertical NPN transistor and the vertical PNP are formed.
The collector lead-out portion from the buried layer of the transistor can be formed simultaneously adjacent to the fine element isolation region formed between the semiconductor layers. Further, in this case, since the vertical NPN transistor and the collector extraction portion of the vertical PNP transistor can have a structure surrounding the emitter and base regions, the collector resistance of both transistors can be reduced at the same time. Therefore, a high-density, high-speed vertical NPN transistor and a semiconductor device in which the vertical PNP transistor is integrated can be realized by a small number of manufacturing steps.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device has a P
⁺ As the first buried layer formed on the semiconductor substrate 1
A type buried layer 2, an N ⁻ type epitaxial layer 3 as a first semiconductor layer formed on the P type semiconductor substrate 1 including the N ⁺ type buried layer 2, and a N ⁻ type epitaxial layer 3. First groove 5 reaching the N ⁺ type buried layer 2
An oxide film 6 as a first insulating film formed only on the side wall of the first groove 5, and an oxide film 6 formed in the first groove 5,
An N ⁺ type polycrystalline silicon film 15 as a second semiconductor layer which is in contact with the ⁺ type buried layer 2 and a ^P- type polycrystalline silicon film 15 formed in the first groove portion 5,
The second groove portion 8 reaching the semiconductor substrate 1 and the second groove portion 8
And an oxide film 9 as a second insulating film formed in the groove portion 8. Then, the N ⁺ type buried layer 2 is formed into a vertical NPN
A transistor collector buried layer, N ⁺ -type poly-crystalline silicon film 15 has a collector lead-out portion of the vertical NPN transistor, the oxide film 9 is N ⁺ -type polycrystalline silicon film 15
The N ⁺ -type polycrystalline silicon film 15 is in contact with the oxide film 6.

In FIG. 1, 7 is a polycrystalline silicon film provided in the first groove 5, 10 is a P-type channel stopper region formed at the bottom of the second groove 8, and 11 is a second. A CVD / SiO ₂ film embedded in the groove portion 8, 12 is a P-type diffusion layer that serves as a base region of the vertical NPN transistor, 13 is a CVD-SiO ₂ film, 14 is an N ⁺ -type diffusion layer that serves as an emitter region, and 16 is P ⁺ type diffusion layers 17, 18 and 19 serving as base contact regions are an emitter electrode, a base electrode and a collector electrode, respectively.

Next, a method of manufacturing the semiconductor device will be described, and FIGS. 1 to 5 are sectional views showing respective manufacturing steps of the semiconductor device in the first embodiment of the present invention. First,
As shown in FIG. 2, the specific resistance is, for example, 10 to 20 Ω · cm.
Arsenic is added to the P-type (111) semiconductor substrate 1 of 60 keV,
After ion implantation under the condition of 1 × 10 ¹⁵ / cm ² , the temperature is set to 9
A heat treatment is performed at 00 ° C. for about 30 minutes to form an N ⁺ type buried layer 2 which will be a collector buried layer of the vertical NPN transistor. Next, on the semiconductor substrate 1 and the N ⁺ type buried layer 2, for example, N having a specific resistance of 1 Ω · cm and a thickness of about 2 μm is formed.
^{The −} type epitaxial layer 3 is formed. Next 1000 nm
After the CVD / SiO ₂ film 4 having a thickness of 1 is deposited, anisotropic etching is performed using, for example, a resist as a mask to form a vertical N
A width of 1.5 μ that reaches the N ⁺ type buried layer 2 to be the collector extraction portion and element isolation region formation portion of the PN transistor
The first groove 5 of m is formed.

Next, thermal oxidation is performed for 20 minutes at a temperature of 900 ° C., and as shown in FIG. 3, the first groove portion 5 has a thickness of 50 nm.
Oxide film 6 is formed. After that, the oxide film 6 on the bottom surface portion of the first groove portion 5 is removed by anisotropic etching, so that the oxide film 6 is formed only on the side wall portion of the first groove portion 5.
Next, a polycrystalline silicon film 7 is deposited to a thickness of 500 nm and anisotropically etched to leave the polycrystalline silicon film 7 only on the side wall of the first groove 5.

Next, anisotropic etching is performed by using the CVD / SiO ₂ film 4 and the polycrystalline silicon film 7 as a mask, as shown in FIG.
As shown in FIG. 2, a second groove portion 8 penetrating the N ⁺ type buried layer 2 and reaching the semiconductor substrate 1 is formed between the polycrystalline silicon films 7 formed on the sidewalls of the first groove portion 5. Then, thermal oxidation is performed at a temperature of 900 ° C. for 20 minutes to form an oxide film 9 having a thickness of 50 nm in the second groove portion 8.

Next, boron is added at 20 keV, 3 × 10 ¹³ /
Ion implantation is performed under the condition of cm ² , and as shown in FIG. 5, a P-type channel stopper region 10 is formed at the bottom of the second groove portion 8.
Then, the CVD / SiO ₂ film 1 is formed in the second groove 8 after the formation of the
By embedding 1 by etch back, the element isolation region is completed. At this time, the CVD / SiO ₂ film 4 on the surface
Is removed.

Next, using a resist as a mask, for example,
30 keV, 2 × 10¹³/ Cm ² Ion injection under the conditions
After entering, heat treatment at a temperature of 900 ℃ for about 30 minutes,
As shown in FIG. 1, the base region of the vertical NPN transistor is
A P-type diffusion layer 12 to be a region is formed. For example, resist
Use as a mask for the emitter area and collector lead
On the polycrystalline silicon film 7 made of arsenic of 30 keV, 1 × 1
0¹⁶/ Cm² Ion implantation under the conditions of
Heat treatment is performed at 0 ° C. for about 60 minutes to diffuse arsenic. This
, The emitter area has N⁺ The mold diffusion layer 14 is formed.
In addition, since the polycrystalline silicon film has a large diffusion coefficient,
N for the collector drawer⁺ Type polycrystalline silicon film 15
It is formed.

Next, for example, using a resist as a mask, boron is ion-implanted under the conditions of 30 keV and 1 × 10 ¹⁶ / cm ² on a region to be a base contact of the vertical NPN transistor, and then at a temperature of 900 ° C. for 45 minutes. A heat treatment is performed to a certain extent to diffuse boron and form a P ⁺ -type diffusion layer 16 to be a base contact region of the vertical NPN transistor. Then, the CVD / SiO ₂ film 13 is formed to a thickness of 500 nm.
Then, the emitter contact region, the base contact region, and the collector contact region are opened.
Finally, the semiconductor device is completed by forming the emitter electrode 17, the base electrode 18, and the collector electrode 19 using, for example, Al.

As described above, in this embodiment, the first groove portion 5 reaching the N ⁺ type buried layer 2 serving as the collector of the vertical NPN transistor is formed around the emitter and base regions, and the first groove portion is formed. The oxide film 6 is formed only on the side wall of the first groove 5, and then the polycrystalline silicon film 7 is formed only on the side wall of the first groove 5, and this is used as a mask to form an element isolation region in the first groove 5. After forming the second groove portion 8 reaching the P-type semiconductor substrate 1 and filling the inside of the groove portion 8 with the oxide film 9 and the CVD / SiO ₂ film 11, thereafter, simultaneously with the formation of the emitter of the vertical NPN transistor, the collector extraction portion is formed. N ⁺
The feature is that the type polycrystalline silicon film 15 is formed.

Therefore, in the vertical NPN transistor, the margin between the collector extraction portion and the element isolation region becomes unnecessary, and the cell size of the vertical NPN transistor can be reduced. Further, since the collector extraction portion can be formed so as to surround the periphery of the emitter / base region, the collector resistance can be reduced, the time required for charging / discharging at the collector / base junction can be shortened, and the operating speed can be improved. be able to.

6 to 7 are sectional views showing the steps of manufacturing a semiconductor device according to the second embodiment of the present invention. In addition, the first
Those having the same functions as those in the embodiment of FIG. As shown in FIG. 6, the semiconductor device has an N ⁺ -type buried layer 2 as a first buried layer formed on a P-type semiconductor substrate 1.
And a P ⁺ type buried layer 32 as a second buried layer formed on the P type semiconductor substrate 1, and formed on the P type semiconductor substrate 1 including the N ⁺ type buried layer 2 and the P ⁺ type buried layer 32. N ⁻ type epitaxial layer 3 as the first semiconductor layer, and N ⁺ type epitaxial layer 3 formed on this N ⁻ type epitaxial layer 3.
First reaching the type buried layer 2 and the P ⁺ type buried layer 32
Groove portion 5, an oxide film 6 as a first insulating film formed only on the side wall of the first groove portion 5, and a second semiconductor formed in the first groove portion 5 and in contact with the N ⁺ type buried layer 2. An N ⁺ -type polycrystalline silicon film 38 as a layer, a P ⁺ -type polycrystalline silicon film 41 as a third semiconductor layer formed in the first groove portion 5 and in contact with the P ⁺ -type buried layer 32, and a first A second groove portion 8 formed in the groove portion 5 and reaching the P-type semiconductor substrate 1;
It has an oxide film 9 as a second insulating film formed in the second groove portion 8. Then, the N ⁺ -type buried layer 2 is used as the collector of the vertical NPN transistor, the N ⁺ -type polycrystalline silicon film 38 is used as the collector extraction portion of the vertical NPN transistor, and the P ⁺ -type buried layer 32 is used as the collector of the vertical PNP transistor. , P ⁺ -type polycrystalline silicon film 41 is used as a collector extraction portion of a vertical PNP transistor.
At this time, the oxide film 9 is in contact with the N ⁺ -type polycrystalline silicon film 38 and the P ⁺ -type polycrystalline silicon film 41 in the region where the vertical NPN transistor and the vertical PNP transistor are adjacent to each other. In the region where the vertical NPN transistor and the vertical PNP transistor are not adjacent to each other, the N ⁺ type polycrystalline silicon film 38 is in contact with the oxide films 6 and 9, and the P ⁺ type polycrystalline silicon film 4 is formed.
1 is in contact with the oxide films 6 and 9.

In FIG. 6, 31 is a collector region.
And N for separating the semiconductor substrate 1 from ⁺ Mold embedding layer, 33
Is a part of the collector region of the vertical PNP transistor
P^-Type diffusion layer, 34 is the base of a vertical NPN transistor
A region is a P-type diffusion layer, and 35 is a vertical PNP transistor.
N-type diffusion layer, which is the base region of the
N, which is the emitter region of the transistor⁺ Type diffusion layer, 37 is vertical
Which is the base contact region of the NPN transistor
⁺ Type diffusion layer, 39 is an emitter of a vertical PNP transistor
Area P⁺ Type diffusion layer, 40 is a vertical PNP transistor
N, which is the base contact region of the⁺ It is a type diffusion layer.
Reference numerals 42, 43 and 44 are vertical NPN transistor filters.
Mitter electrode, base electrode, collector electrode, 45, 46,
47 is an emitter electrode and a base of a vertical PNP transistor
Electrode, collector electrode, T₁ Is a vertical NPN transistor,
T₂ Is a vertical PNP transistor.

Next, a method of manufacturing the semiconductor device will be described, and FIGS. 6 and 7 are sectional views showing the respective manufacturing steps of the semiconductor device in the second embodiment of the present invention. In FIG. 7, the P type (1
11) Arsenic is applied to the semiconductor substrate 1 at 60 keV and 1 × 10 ¹⁵
Ion implantation under the condition of / cm ₂ and then at a temperature of 900 ° C for 3
Heat treatment is performed for about 0 minutes, the vertical NPN transistor region becomes the collector buried layer in the N ⁺ -type buried layer 2, N ⁺ -type buried for separating the collector region and the semiconductor substrate 1 in the vertical PNP transistor area The layer 31 is formed. Next, for example, using a resist as a mask, boron is added at 40 ke
After ion implantation under the conditions of V, 1 × 10 ¹⁴ / cm ² , a heat treatment is performed at a temperature of 1100 ° C. for about 180 minutes to form a vertical PN.
A P ⁺ type buried layer 32, which will be the collector buried layer of the P transistor, is formed. After that, an N ⁻ type epitaxial layer 3 having a specific resistance of 1 Ω · cm and a thickness of about 2 μm is formed on the semiconductor substrate 1, the N ⁺ type buried layer 2 and the P ⁺ type buried layer 32.

Next, CVD SiO having a thickness of 1000 nm is used.
_{After the two} films are deposited, anisotropic etching is performed using, for example, a resist as a mask to form a vertical NPN transistor and a vertical P
A first groove portion 5 having a width of 1.5 μm reaching the N ⁺ type buried layer 2 and the P ⁺ type buried layer 32, which will be the collector extraction portion and the element isolation region formation portion of the NP transistor, is formed.

Next, thermal oxidation is performed at a temperature of 900 ° C. for 20 minutes to form an oxide film 6 having a thickness of 50 nm in the first groove portion 5. After that, the oxide film 6 on the bottom surface portion of the first groove portion 5 is removed by anisotropic etching, so that the oxide film 6 is formed only on the side wall portion of the first groove portion 5. Then, a polycrystalline silicon film is deposited to a thickness of 500 nm, and anisotropic etching is performed to leave the polycrystalline silicon film 7 only on the side wall of the first groove 5.

Next, anisotropic etching is performed by using the CVD / SiO ₂ film and the polycrystalline silicon film 7 as a mask, and between the polycrystalline silicon films 7 formed on the side walls of the first groove portion 5,
A second groove portion 8 is formed which penetrates the N ⁺ type buried layer 2, the N ⁺ type buried layer 31 and the P ⁺ type buried layer 32 and reaches the semiconductor substrate 1. Then, thermal oxidation is performed at a temperature of 900 ° C. for 20 minutes to form an oxide film 9 having a thickness of 50 nm in the second groove portion 8.

Next, boron is added at 20 keV, 3 × 10 ¹³ /
After ion-implanting under the condition of cm ² to form a P-type channel stopper region 10 at the bottom of the second groove portion 8, the CVD / SiO ₂ film 11 is embedded in the second groove portion 8 by etch back. Complete the element isolation region. At this time, the CVD / SiO ₂ film 4 on the surface is removed.

Next, as shown in FIG.
With a mask of boron at 80 keV, 2 × 10¹²/ Cm
² After ion implantation under the conditions of 60 minutes at a temperature of 1100 ° C
After performing a heat treatment to a certain degree, the vertical PNP transistor collection
Data area P^- The mold diffusion layer 33 is formed. And an example
For example, using the resist as a mask, boron is 30 keV, 2 ×
10¹³/ Cm² After ion implantation under the conditions
Vertical NPN transistor after heat treatment at ℃ for about 30 minutes
A P-type diffusion layer 34 which will be the base region of the capacitor is formed. next
For example, using a resist as a mask, phosphorus at 80 keV, 3.5
× 10¹³/ Cm ² After ion implantation under the conditions
Perform vertical heat treatment for 20 minutes at 0 ℃
An N-type diffusion layer 35 which will be the base region of the star is formed. Next
For example, using a resist as a mask, vertical NPN transistor
The emitter area and collector lead-out area of the
A vertical PNP transistor base is formed on the crystalline silicon film 7.
Arsenic 30 keV, 1 × 1 on the area to be the contact
0¹⁶/ Cm² Ion implantation under the conditions of
Heat treatment is performed at 0 ° C. for about 60 minutes to diffuse arsenic. This
In the vertical NPN transistor,
N in the area⁺ The type diffusion layer 36 is formed, and the polycrystalline silicon
Since the con-film has a large diffusion coefficient,
Is N⁺ A type polycrystalline silicon film 38 is formed. Also,
N is formed in the base contact region of the vertical PNP transistor.
⁺ The mold diffusion layer 40 is formed.

Next, using a resist as a mask, for example, 30 keV of boron is formed on the region which will be the base contact of the vertical NPN transistor and on the polycrystalline silicon film 7 which will be the emitter region and collector extraction portion of the vertical PNP transistor. Ions are implanted under the condition of 1 × 10 ¹⁶ / cm ² , and then heat treatment is performed at a temperature of 900 ° C. for about 45 minutes to diffuse boron. At this time, the P ⁺ type diffusion layer 37 is formed in the base contact region of the vertical NPN transistor. Further, in the vertical PNP transistor, since the P ⁺ type diffusion layer 39 is formed in the emitter region and the polycrystalline silicon film has a large diffusion coefficient, the P ⁺ type polycrystalline silicon film 41 is formed in the collector extraction portion. It

Next, a CVD / SiO ₂ film 13 is formed to a thickness of 500 nm.
Vertical NPN transistor and vertical P
An emitter contact region, a base contact region, and a collector contact region are opened in each of the NP transistors.

Finally, a vertical type N is formed using, for example, Al.
The semiconductor device is completed by forming the emitter electrode 42, the base electrode 43, and the collector electrode 44 in the PN transistor region, and the emitter electrode 45, the base electrode 46, and the collector electrode 47 in the vertical PNP transistor region.

As described above, in this embodiment, the vertical NPN transistor and the N ⁺ type buried layer 2 and the P 2 serving as the collector are formed around the emitter and base regions of the vertical PNP transistor.
Forming a first groove portion reaching the ⁺ type buried layer 32,
After forming the oxide film 6 only on the side wall of the groove part, the polycrystalline silicon film 7 is formed only on the side wall of the first groove part, and using this as a mask, an element isolation region is formed in the first groove part. A second groove reaching the semiconductor substrate is formed, and the inside of this groove is filled with an oxide film 9 and a CVD.SiO ₂ film 11, and thereafter, at the same time when the emitter of the vertical NPN transistor is formed, an N serving as a collector lead-out portion is formed. ^{It is characterized in that the +} type polycrystalline silicon film 38 is formed, and at the same time when the emitter of the vertical PNP transistor is formed, the P ⁺ type polycrystalline silicon film 41 serving as a collector extraction portion is formed.

Therefore, N ^{+ of the} vertical NPN transistor is
-Type collector lead-out part and P of vertical PNP transistor
^{The +} -type collector lead-out portion can be formed in self-alignment with the element isolation region without adding a manufacturing process.
The cell size of the PN transistor and the vertical PNP transistor can be reduced. Further, in the vertical NPN transistor and the vertical PNP transistor, since the collector extraction portion can be formed so as to surround the periphery of the emitter and base regions, the collector resistance can be reduced at the same time without adding a manufacturing process. The time required for charging / discharging at the collector / base junction is shortened, and a high-speed vertical NPN transistor and a vertical PNP transistor can be simultaneously formed.

[0037]

As described above, according to the present invention, in the vertical bipolar transistor, the first trench portion reaching the buried layer of the collector region is formed around the emitter and base regions, and the first trench portion is formed. Since the polycrystalline silicon film that will be the collector extraction part and the fine element isolation region are formed inside by self-alignment, the margin between the collector extraction part and the element isolation region is unnecessary, and the cell size of the vertical bipolar transistor is reduced. can do. Further, since the collector extraction portion can be formed so as to surround the periphery of the emitter / base region, the collector resistance can be reduced, the time required for charging / discharging at the collector / base junction can be shortened, and the operating speed can be improved. be able to.

In addition, a vertical NPN transistor and an N ⁺ -type buried layer serving as a collector and a P around the emitter and base regions of the vertical PNP transistor, respectively.
^A first groove portion reaching the ⁺ type buried layer is formed, and inside the groove portion, an N ⁺ type polycrystalline silicon film which becomes a collector lead-out portion of the vertical NPN transistor and a P which becomes a collector lead-out portion of the vertical PNP transistor are formed. ^{Since the +} type polycrystalline silicon film and the fine element isolation region can be formed by self-alignment without adding a manufacturing process, the cell size of the vertical NPN transistor and the vertical PNP transistor can be reduced. Further, in the vertical NPN transistor and the vertical PNP transistor, since the collector extraction portion can be formed so as to surround the periphery of the emitter and base regions, the collector resistance of both transistors can be reduced without adding a manufacturing process. A semiconductor device in which a high-density and high-speed vertical NPN transistor and a vertical PNP transistor are integrated is provided because the operation time can be improved by shortening the time required for charge / discharge at the collector / base junction. can do.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a structural cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 P-type semiconductor substrate 2 N ⁺ type buried layer (first buried layer) 3 N ⁻ type epitaxial layer (first semiconductor layer) 5 First groove portion 6 Oxide film (first insulating film) 8 Second groove portion 9 Oxidation Film (second insulating film) 15 N ⁺ type polycrystalline silicon film (second semiconductor layer) 32 P ⁺ type buried layer (second buried layer) 38 N ⁺ type polycrystalline silicon film (second semiconductor layer) 41 P ⁺ Type polycrystalline silicon film (third semiconductor layer)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H01L 21/76 R 9169-4M L 9169-4M 27/082 (72) Inventor Masahiro Nakatani Kadoma Osaka Prefecture 1006 Kadoma, Oita-shi Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] 1. A reverse conductivity type first buried layer formed on a semiconductor substrate of one conductivity type, and a reverse conductivity type first semiconductor layer formed on the semiconductor substrate including the first buried layer, A first groove formed in the first semiconductor layer and reaching the first buried layer; a first insulating film formed only on a sidewall of the first groove; a first insulating film formed in the first groove; A second semiconductor layer of opposite conductivity type in contact with the first buried layer, a second groove portion formed in the first groove portion and reaching the semiconductor substrate, and a second insulating film formed in the second groove portion. At least, the first buried layer serves as a vertical bipolar transistor collector, the second semiconductor layer serves as a collector lead-out portion of the vertical bipolar transistor, the second insulating film contacts the second semiconductor layer, and The semiconductor layer is in contact with the first insulating film Semiconductor device. 2. A first buried layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type, a second buried layer of one conductivity type formed on the semiconductor substrate, the first buried layer and a second buried layer. A first semiconductor layer of an opposite conductivity type formed on the semiconductor substrate including a buried layer, and the first semiconductor layer formed on the first semiconductor layer,
A buried layer and a first groove portion reaching the second buried layer;
A first insulating film formed only on the sidewall of the first groove, a second semiconductor layer of the opposite conductivity type formed in the first groove and in contact with the first buried layer, and formed in the first groove. Is
A third semiconductor layer of one conductivity type in contact with the second buried layer,
At least a second groove formed in the first groove and reaching the semiconductor substrate and a second insulating film formed in the second groove are provided, and the first buried layer is formed into a vertical NPN.
The second semiconductor layer serves as a collector of a transistor, and the second semiconductor layer serves as a collector extraction portion of a vertical NPN transistor.
The buried layer serves as a collector of the vertical PNP transistor, the third semiconductor layer serves as a collector lead-out portion of the vertical PNP transistor, the second insulating film contacts the second semiconductor layer and the third semiconductor layer, and the second A semiconductor device in which a semiconductor layer is in contact with the first insulating film and the third semiconductor layer is in contact with the first insulating film. 3. A first substrate of opposite conductivity type on a semiconductor substrate of one conductivity type.
A step of forming a buried layer, a step of forming a first semiconductor layer of an opposite conductivity type on the semiconductor substrate including the first buried layer, and a step of reaching the first buried layer to the first semiconductor layer Forming a groove, forming a first insulating film only on the sidewall of the first groove, and forming a second semiconductor layer of the opposite conductivity type in the first groove so as to contact the first buried layer. And a step of forming a second groove portion reaching the semiconductor substrate in the first groove portion, and a step of forming a second insulating film in the second groove portion, the first embedded layer As a collector of a vertical bipolar transistor, the second semiconductor layer as a collector extraction part of a vertical bipolar transistor, the second insulating film is in contact with the second semiconductor layer, and the second semiconductor layer is the first insulating film. Form to touch Method of manufacturing a conductor arrangement. 4. A first substrate of opposite conductivity type on a first conductivity type semiconductor substrate.
Forming an embedded layer, forming a second embedded layer of one conductivity type on the semiconductor substrate, and forming a first embedded layer and a second embedded layer on the semiconductor substrate having an opposite conductivity type
Forming a semiconductor layer, forming a first groove in the first semiconductor layer that reaches the first buried layer and the second buried layer, and forming a first insulating film only on a sidewall of the first groove. A step of forming, a step of forming a second conductive type second semiconductor layer in contact with the first buried layer in the first groove, and a step of forming a second conductive type first semiconductor layer in contact with the second buried layer in the first groove. At least three steps of forming a semiconductor layer, forming a second groove portion reaching the semiconductor substrate in the first groove portion, and forming a second insulating film in the second groove portion, The first buried layer serves as a collector of a vertical NPN transistor, the second semiconductor layer serves as a collector extraction portion of a vertical NPN transistor, and the second buried layer serves as a vertical PPN transistor.
It is used as a collector of an NP transistor, the third semiconductor layer is used as a collector extraction portion of a vertical PNP transistor, the second insulating film is in contact with the second semiconductor layer and the third semiconductor layer, and the second semiconductor layer is the first semiconductor layer. 1. A method of manufacturing a semiconductor device, wherein the third semiconductor layer is formed so as to be in contact with one insulating film and the third semiconductor layer is in contact with the first insulating film.