JP3474595B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure separated by an insulator, and more particularly to a semiconductor device having a lateral PNP junction transistor. 2. Description of the Related Art Conventionally, a parasitic transistor is formed in a lateral PNP junction type transistor formed by a PN junction isolation method in a P conduction type semiconductor substrate such as a bipolar IC. Therefore, in order to improve the characteristics, it is necessary to form a shape surrounding the P-conductivity type emitter with the P-type collector. A vertical PNP junction transistor that has a higher performance than a horizontal type does not have such a structure, but the formation process is complicated, and there is difficulty in formation control.
Horizontal P that can be easily formed in the manufacturing process of N-type transistor
NP junction transistors are most often used. [0003] In recent years, with the demand for integration, there has been an increasing demand for miniaturization of each element formed on a substrate. Since the technology has not been established, there is a problem that it is difficult to form a small-sized integrated device in the lateral PNP junction transistor. [0004] To solve the above-mentioned problems, the present invention provides a first silicon substrate of N-conductivity type ;
A second silicon substrate bonded across the insulating film, by bonding, the semiconductor device using a semiconductor substrate a buried insulating layer formed therein, N conductivity type
From the first silicon substrate surface to the buried insulating layer,
An island shape to form a groove surrounding the N conductivity type region, the groove and the insulating portion by forming the insulating film, and the insulating portion, by the buried insulating layer, islands that are insulated and separated from other regions of the semiconductor substrate
An element region is formed of, near the surface of the island-like element region, 1
A first P-type region, a first N-type region, and a second P-type region in this order from the end side.
Region, the second N-type region and the third N-type region are aligned in a line.
5 regions are formed, and a first P-type region, a second P-type region and
And the third N-type region are respectively a P-type emitter active layer and a P-type collector.
PNP transistor as active layer and N-type base layer
Is formed, in the vicinity of the surface of the island-like element region, P-type e <br/> emitter active layer is in contact only with the insulating portion and the 1N-type region, a 1N and P-type <br/> active collector layer insulating portion Mold region and second N-type region
Pass the contact only, N-type base layer is in contact only with the insulation part and the 2N-type region, and the third 1N type region and the 2N-type region, the island
No connection is made near the surface of the element region, and P
The semiconductor device is characterized in that it is connected via the inside of the island-shaped element region below the type collector active layer . Since the PNP junction type transistor is completely insulated from the rest of the substrate, no parasitic transistor is formed. The semiconductor device of the present invention has an SOI
(Silicon On Insulator) method to form buried insulating layer
Since it is formed, it can be easily manufactured. Accordingly, it is not necessary to form a shape in which the periphery of the P-conductivity type emitter is surrounded by the P-conductivity type collector as before, and the element can be made sufficiently small without impairing the function, and the integration is improved. Can be used for Semiconductor of the present invention
The device is embedded by SOI (Silicon On Insulator) method.
Since the embedded insulating layer is formed, it can be easily manufactured.
it can. Hereinafter, the present invention will be described with reference to specific examples. FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 1 (a) is a front view, and FIG. 1 (b) is a center XX 'in FIG. 1 (a).
It is sectional drawing of a part. Here, the silicon semiconductor substrate 10
1, a buried insulating layer 102 is formed, and an insulating part 103 insulates the element part 104 from the substrate in a trench shape from the substrate surface. In this example, the cavity formed in the trench is filled with polycrystalline silicon 110 for protection. E, C and B in the figure are emitters, respectively.
Collector, base abbreviation. The outermost surface is a metal electrode such as aluminum, and the electrode is formed on a contact hole provided in an electrode forming portion of an oxide film 105 which is a protective insulating layer on the substrate surface. In the lower region of the E and C electrodes, N
^- emitter activity of the P ⁺ type formed in the layer 108 layer 10
6. A collector active layer 107 is formed, and both ends of both active layers are in contact with an insulating portion 112 formed by a trench. Further, the N ^- layer 108 is formed on the N ⁺ layer 109, N ⁺ layer 109 is connected to the base electrode.
Therefore, the structure is such that the electrodes are linearly arranged in the order of the emitter, the collector, and the base. The forming process of this embodiment will be described. Antimony is diffused by 3 μm on the mirror-polished surface of the N ⁻ silicon substrate by a vapor phase diffusion method to form an N ⁺ layer 109 (FIG. 2). Separately, one principal surface of a P ^- silicon substrate is mirror-polished and then thermally oxidized to a thickness of about 1 μm.
Is formed (FIG. 3). The two substrates are bonded together in a clean atmosphere, and heated to about 1100 ° C. to join them (FIG. 4). The polished by N ^- polished side of the silicon substrate to a thickness of about 15μm from the oxide film (Fig. 5). At this point, an N ⁺ layer 109 having a thickness of about 3 μm is formed on the oxide film 102, and an N ⁻ layer 108 having a thickness of about 12 μm is formed thereon. Thus, a so-called SOI (Silicon On Insulator) substrate is formed. Next, as shown in FIG. 6, after a deep N ⁺ layer 111, a collector region 107 and an emitter region 106 are formed by a photolithographic process and a diffusion process which are often used in the prior art, the surface is thermally oxidized to about 0 °. A field oxide film 105 of 0.5 μm is formed. A nitride film 701 is formed thereon by LPCVD to a thickness of about 0.1 μm (FIG. 7). A resist 801 is applied to the nitride film 701 (FIG. 8), and plasma etching using a fluorine-based etching gas, hydrofluoric acid etching, and reactive ion etching using a fluorine-based etching gas are used to form a region around the element as shown in FIG. A trench 802 is formed up to a buried insulating layer at a location to be an insulating portion. The surface of the trench 802 is oxidized to form an insulating portion, and the remaining cavity is filled with polycrystalline silicon 110 by LPCVD (FIG. 9). After forming an oxide film also on the polycrystalline silicon, the nitride film is removed by dry etching, and an element as shown in FIG. 9 is formed. [0010] Finally, a contact hole is formed in the oxide film 105 to form an electrode wiring, and the bipolar integrated circuit of FIG. 1 is obtained. In the lateral PNP junction type transistor having this configuration, since it is completely separated from the substrate, the P type N
Any type of substrate may be used, and it is not necessary to form a shape in which the periphery of the P-conduction type emitter is surrounded by the P-conduction type collector as in the past. The size of a conventional lateral transistor is shown in FIG. 10 (a), and as shown in FIG. 10 (b) of the same scale, the structure of the present invention makes it possible to reduce the size of the element sufficiently without impairing its function and to contribute to integration. Can be. In addition,
In this embodiment, it can be reduced to approximately 1/15 of the conventional value. In addition, NPN is provided in the same separated element region.
It is often used to integrally form a P-type transistor and a PNP-type transistor at the same time.
An NPN transistor can be integrally formed by forming an N ⁺ layer in the P ⁺ layer 107 and using it as an emitter, with the ⁻ layer 108 as a collector and the P ⁺ type active layer 106 as a base.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a sectional view showing a forming process of the present invention. FIG. 3 is a sectional view showing a forming process of the present invention. FIG. 4 is a sectional view showing a forming process of the present invention. FIG. 5 is a sectional view showing a forming process of the present invention. FIG. 6 is a sectional view showing a forming process of the present invention. FIG. 7 is a sectional view showing a forming process of the present invention. FIG. 8 is a sectional view showing a forming process of the present invention. FIG. 9 is a sectional view showing a forming process of the present invention. FIG. 10 is a configuration diagram comparing a conventional example with the embodiment of the present invention. DESCRIPTION OF SYMBOLS 101 semiconductor substrate 102 buried insulation 103 insulating part 104 element part 105 surface oxide film 110 polycrystalline silicon 111 deep N ⁺ layer 701 nitride film 801 resist 802 trench

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-2-27734 (JP, A)                 JP-A-3-110852 (JP, A)                 Japanese Patent Laid-Open No. 50-152674 (JP, A)                 JP-A-58-170062 (JP, A)                 JP-A-2-119229 (JP, A)                 Hideaki Ikoma, Akira Ichiseta "Bipolar               Integrated Circuit "March 20, 1989, First Edition, Second Printing               Published by Modern Science, P.S. 37, 40

Claims (1)

(57) a first silicon substrate of the Claims 1] N conductivity type, and a second silicon substrate bonded across the insulating film, by bonding, embedding insulation therein In a semiconductor device using a semiconductor substrate on which a layer is formed, a groove surrounding an N-conductivity-type region from the surface of the N-conductivity-type first silicon substrate to the buried insulating layer is formed, and the groove is formed. Forming an insulating film to form an insulating portion; forming an island-shaped element region insulated and separated from another region of the semiconductor substrate by the insulating portion and the buried insulating layer; and a surface of the island-shaped element region. The neighborhood is the first from the one end side
P-type region, first N-type region, second P-type region, second N-type region
And five regions are formed such that the third N-type regions are aligned in a line.
The first P-type region, the second P-type region, and the third N-type region.
The regions are P-type emitter active layer, P-type collector active layer and
And a PNP transistor serving as an N-type base layer is formed , and near the surface of the island-shaped element region, the P-type emitter active layer is in contact only with the insulating portion and the first N-type region , The P-type collector active layer includes the insulating portion and the first N
Contact only -type region and the first 2N-type region, the N-type base <br/> scan layer at hotel in contact only with the said insulated portion first 2N-type region
Ri, wherein The first 1N type region and the first 2N-type region, not connected in the vicinity of the surface of the island-shaped <br/> element region, the P
A semiconductor device which is connected via an inside of an island-shaped element region below a type collector active layer .