JP2005057171A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the outer base of an npn bipolar transistor uses p<SP>+</SP>-polysilicon, this not allowing its base resistance to be lowered. <P>SOLUTION: The outer base 36 of an npn bipolar transistor uses n<SP>+</SP>-polysilicon to form a tunnel junction 24 with its inner base 38. Thus, the reduction of the base resistance is realized. The inner base 38 is preferably made of SiGe and preferably of SiGeC. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a bipolar transistor having an external base structure.

  In recent years, BiCMOS / LSI technology, in which bipolar transistors are formed on the same substrate as a MOS transistor and highly integrated, has attracted attention. Since BiCMOS technology enables high-performance analog circuits and high-performance digital circuits to be mixed, the number of components and the chip area can be reduced, and a low-cost and small-size chip can be manufactured. Recently, a technology for integrating a Si / SiGe heterobipolar transistor (HBT) having a base layer composed of a SiGe layer on a Si substrate has attracted attention (see, for example, Non-Patent Document 1).

  The SiGe layer is capable of continuously changing the band gap by changing the composition of Ge, and has been attracting great interest because it exhibits excellent high-frequency characteristics by applying this.

There are two types of bipolar transistors, NPN type and PNP type. The NPN type is widely used because an element with excellent performance can be manufactured in a small area. Further, in the high performance NPN type bipolar transistor, an external base structure is used in which the base is drawn from the P type internal base using P ⁺ polysilicon in order to minimize the collector capacitance (see, for example, Non-Patent Document 2). .

  The prior art of an NPN type bipolar transistor using a SiGe base layer will be described below with reference to FIG.

A collector layer 11 of a bipolar transistor containing an N-type impurity formed by an epitaxial growth method or an ion implantation method is formed in the Si substrate 10. The N-type impurity concentration of the collector layer 11 is adjusted to about 1 × 10 ¹⁷ cm ⁻³ . The element isolation region includes a deep trench isolation having a depth of about 2 μm formed by embedding the second insulator 15 (non-doped polysilicon) and the first insulator 14 (silicon oxide), and a third insulator 13 ( It is formed from a shallow trench isolation having a depth of about 0.35 μm formed by embedding silicon oxide. Further, an isolation P ⁺ region 12 for channel stopper is provided in a region located below the deep trench isolation.

Further, an N ⁺ collector extraction layer 16 for taking an electrode of the collector layer 12 is formed in the Si substrate 10. A fourth insulating layer 19 having a thickness of about 30 nm is provided above the collector layer 11, and a P ⁺ -type Si _1-x Ge _x internal base 38 having an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ and A Si layer 39 is formed. UHV-CVD (Ultra High Vacuum Chemical Vapor Deposition) apparatus is used for the deposition of the P ⁺ -type Si _1-x Ge _x internal base 38 and the Si layer 39. A single crystal (SiGe internal base 38, Si layer 39) is deposited above the collector layer, and a polycrystal (SiGe external base 40, Si external base 41) is deposited above the fourth insulating layer 19. The external base is P-type doped with an impurity concentration as high as about 1 × 10 ²⁰ cm ⁻³ .

Above the Si layer 39, an N ⁺ polysilicon emitter 28 doped with high-concentration N-type impurities is provided. N ⁺ around the polysilicon emitter 28 and the insulator 26 of the sidewall 25 and the seventh is provided, and electrically insulates the external base and the N ⁺ polysilicon emitter 28. The Si layer 39 is doped N-type by impurity diffusion from the N ⁺ polysilicon emitter layer 28, and this Si layer 39 functions as the emitter of the NPN bipolar transistor.

A Ti silicide layer 29 having a thickness of about 25 nm is formed on the surfaces of the N ⁺ collector lead layer 16, the external base, and the N ⁺ polysilicon emitter layer 28 in order to reduce resistance. .

An interlayer insulating film 30 is provided on the Ti silicide layer 29, penetrates the interlayer insulating film 30, and is electrically connected to the internal base 38, the N ⁺ polysilicon emitter 28, and the collector layer 11, respectively. A base electrode 31, an emitter electrode 32, and a collector electrode 33 are formed.
T. Sakai, Y. Kobayashi, H. Yamauchi, M. Sato, T. Makino, "High speed bipolar ICs using super self-aligned process technology", Jpn. J. Appl. Phys., 20, Suppl. 20-1 , pp.155-159 (1980). T. Sakai, Y. Kobayashi, H. Yamauchi, M. Sato, T. Makino, "High speed bipolar ICs using super self-aligned process technology", Jpn. J. Appl. Phys., 20, Suppl. 20-1 , pp.155-159 (1980).

In the bipolar transistor, the reduction of the base resistance Rb is an important issue for improving the performance of the transistor. This means that for applied voltage V _BE between the emitter and base being externally supplied voltage product of the base resistance Rb and the base injection current Ib is applied between the interior of the emitter-base junction, i.e. Rb-Ib This is because the voltage drop is reduced by the voltage drop. When attention is paid to the maximum oscillation frequency (Fmax) of the bipolar transistor, Fmax uses the cutoff frequency (Ft), collector capacitance (Cjc), and base resistance (Rb) of the bipolar transistor,
Fmax = (Ft / (8π · Cjc · Rb)) ^1/2
Given in. Therefore, Fmax can be improved by reducing the base resistance Rb.

In order to reduce the base resistance Rb in this way, in the NPN bipolar transistor having the external base structure, P ⁺ polysilicon doped with B (boron) at a sufficiently high concentration is used as the external base. However, since it is not possible to dope boron beyond the solid solution limit into Si, the current situation is that the base resistance cannot be further reduced.

Therefore, in the present invention, an N ⁺ -type impurity-doped layer (N ⁺ polysilicon) is used on the external base of an NPN-type bipolar transistor. The hole base injection current Ib is injected from the N ⁺ type external base into the P type internal base layer by a tunnel current. Since N ⁺ polysilicon has a conductivity about twice as large as that of P ⁺ polysilicon, a low base resistance can be realized.

  Since the base resistance can be reduced by the present invention, a high-performance NPN bipolar transistor can be manufactured.

In the present invention, in order to reduce the external base resistance, the resistance is reduced by using N ⁺ polysilicon for the external base of the NPN type bipolar transistor.
(First embodiment)
First, a bipolar transistor manufacturing method according to the present embodiment will be described with reference to FIGS. Here, the manufacturing method will be described by taking an HBT (heterobipolar transistor) having a SiGe layer as a base layer as an example.

FIG. 4 (a)
First, a collector layer 11 of a bipolar transistor containing an N-type impurity is formed on the Si substrate 10 by ion implantation. P (phosphorus) or As (arsenic) is used as the implantation species, and the N-type impurity concentration is adjusted to about 1 × 10 ¹⁷ cm ⁻³ . The N-type collector layer 11 may be formed using an epitaxial growth method. In this case, doping may be performed during epitaxial growth. Next, element isolation is formed by DTI (deep trench isolation). After a groove having a depth of about 2 μm is formed by dry etching, B (boron) is implanted into the isolation P ⁺ region 12 serving as a channel stopper at the bottom of the groove. After forming the first insulator 14 on the inner wall of the groove, the inside of the groove is filled with the second insulator 15. Silicon oxide is preferably used for the second insulator 14. When silicon oxide is used, the groove inner wall silicon portion may be oxidized by thermal oxidation. Further, non-doped polysilicon is preferably used for the first insulator 15. When non-doped polysilicon is used, the inside of the groove can be filled without a gap by using the CVD method.

FIG. 4 (b)
Next, the base / emitter formation region 34 and the collector lead-out region 35 are separated by STI (shallow trench isolation). The STI is formed by embedding the third insulator 13 and has a depth of about 0.35 μm. Silicon oxide is preferably used for the third insulator 13. Next, As (arsenic) or P (phosphorus) is ion-implanted into the collector extraction region 35 at a high concentration (about 2 × 10 ²⁰ cm ⁻³ ) to form the N ⁺ collector extraction layer 16. At this time, the width of the base / emitter formation region 34 is W1.

FIG. 4 (c)
Further, a fourth insulating layer 19 having a thickness of about 30 nm is deposited. As a material of the fourth insulating layer 19, silicon oxide may be deposited by a CVD method or the like. Next, an opening is formed in the base / emitter formation region 34 by dry etching or wet etching.

FIG. 4 (d)
A Si _1-x Ge _x layer 20 (0 <x ≦ 0.3) and a Si layer 21 are sequentially deposited on the entire surface of the Si substrate 10. UHV-CVD (Ultra High Vacuum Chemical Vapor Deposition) apparatus is used for deposition. By performing crystal growth on the substrate having the openings as described above, a single crystal film is formed on the base / emitter formation region 34 (single crystal region 17), and the third insulator 13 and the fourth insulating layer are formed. A polycrystalline film (polycrystalline region 18) is formed on 19. The film thickness of the Si _1-x Ge _x layer 20 is set to about 30 nm to 60 nm, and the thickness of the Si layer 21 is set to about 10 nm to 40 nm. The Si _1-x Ge _x layer 20 is P-type doped with B (boron) to about 1 × 10 ¹⁹ cm ⁻³ during crystal growth. At this time, the Si layer 21 is undoped. Si _1-x Ge _x layer 20 of the single-crystal region 17 serves as the internal base of HBT, Si _1-x Ge _x layer 20 of polycrystalline region 18 functions as an external base. As described above, it is known that high frequency characteristics can be improved by using a SiGe / Si laminated structure for the base portion of the HBT.

Further, instead of the Si _1-x Ge _x layer 20, a Si _{1-x -y} Ge _x C _y layer (0 <x ≦ 0.3, 0 <y ≦ 0.02) may be used. Si _1-x - The use of _y Ge _x C _y layer, the base portion of the B (boron) is diffused into the emitter and collector regions, it is possible to prevent the base width is increased.

FIG.
Next, a fifth insulating layer 22 and a sixth insulating layer 23 are sequentially deposited on the entire surface of the Si substrate 10. Silicon oxide with a thickness of about 30 nm may be used for the fifth insulating layer 22, and silicon nitride with a thickness of about 50 to 100 nm may be used for the sixth insulating layer 23. The silicon oxide film of the fifth insulating layer 22 functions as an etch stopper when the emitter opening is formed. Next, the fifth insulating layer 22 and the sixth insulating layer 23 are processed into a mesa shape by dry etching. When the width of the fifth insulating layer 22 and the sixth insulating layer 23 is W2, W2 may be set so as to satisfy W2 <W1.

If a mixed gas of tetrafluoromethane (CF ₄ ), trifluoromethane (CHF ₃ ), and hydrogen (H ₂ ) is used as the dry etching gas, the fifth insulating layer 22 and the Si layer 21 are hardly etched. The sixth insulating layer 23 can be processed.

FIG.
Thereafter, As (arsenic) or P (phosphorus) is ion-implanted into the Si substrate 10. At this time, the fifth insulating layer 22 and the sixth insulating layer 23 function as an implantation mask, and ions are not implanted into the Si layer 39 and the Si _1-x Ge _x internal base 38 in the single crystal region 17. Region 18 is doped N-type. Accordingly, the N + type Si _1-x Ge _x external base 36 and the N ⁺ type Si external base 37 are formed. Needless to say, the Si _1-x Ge _x external base 36 is derived from the SiGe layer 20, and the N ⁺ -type Si external base 37 is derived from the Si layer 21. At this time, the tunnel junction 24 is formed by N-type doping at a high concentration of about ³ × 10 ²⁰ cm ⁻³ . Note that the Si layer 39 finally functions as an emitter layer.

FIG. 5 (c)
After forming the tunnel junction 24, an insulator made of silicon oxide or silicon nitride is deposited on the entire surface of the Si substrate 10, and the sidewall 25 is formed by etching back the entire surface.

FIG. 5 (d)
A seventh insulator 26 having a thickness of about 100 nm is deposited on the entire surface of the substrate. A silicon oxide film may be used for the sixth insulator 26.

FIG. 6 (a)
6A and 6B, the emitter opening 27 is formed in two stages. First, a part of the seventh insulator 26 and a part of the sixth insulating layer 23 are removed by dry etching, and an emitter opening 27 is formed. If the width of the emitter opening is W3, it may be set so as to satisfy W3 <W2.

FIG. 6 (b)
Next, the fifth insulating layer 22 is removed by wet etching. In the case where a silicon oxide film is used for the fifth insulating layer 22, hydrofluoric acid or buffered hydrofluoric acid may be used for the etchant. By using wet etching in this way, it is possible to avoid etching damage to the Si layer 39.

FIG. 6 (c)
N ⁺ polysilicon doped with high-concentration N-type impurities is deposited on the Si substrate 10. N ⁺ polysilicon is deposited using a CVD method to fill the emitter opening 27. Next, an N ⁺ polysilicon emitter 28 is formed using dry etching. By using a mixed gas composed of chlorine (Cl ₂ ), hydrogen bromine (HBr), argon (Ar), etc. as the dry etching gas, only polysilicon can be selectively processed. By doping the Si layer 39 to N-type by impurity diffusion from the N ⁺ polysilicon emitter 28, an emitter of an NPN heterobipolar transistor is formed.

FIG. 6 (d)
The seventh insulator 26 is processed by dry etching to expose the external base region 40 on the surface.

FIG. 7 (a)
The Si layer 21, the Si _1-x Ge _x layer 20, and the fourth insulating layer 19 are processed by dry etching to expose the N ⁺ collector extraction layer 16 on the surface.

FIG. 7 (b)
A Ti silicide layer 29 having a thickness of about 25 nm is formed on the surfaces of the N ⁺ polysilicon emitter 28, the N ⁺ collector lead layer 16, and the N ⁺ polysilicon external base layer 27.

FIG. 7 (c)
After the interlayer insulating film 30 is deposited and contact holes are formed, a base electrode 31, an emitter electrode 32, and a collector electrode 33 are formed to complete the device.

In this manufacturing method, in the step of FIG. 5B, N-type impurity ions are implanted before the sidewall 25 is formed. However, after the sidewall 25 is formed, N-type impurity ions are implanted. Also good. When ion implantation of N-type impurities is performed after the formation of the sidewall 25, the structure of the completed NPN-type bipolar transistor is as shown in FIG. Compared with FIG. 7C, the tunnel junction 24 is formed at a position (outside) away from the internal base by the width of the sidewall 25. In this way, the risk of a short circuit between the N ⁺ external base and the N emitter can be avoided by moving the tunnel junction slightly away from the internal base.

Next, the tunnel junction will be described with reference to FIG. According to the present invention, as shown in FIG. 1, a tunnel junction 24 is generated between the P ⁺ -type Si _1-x Ge _x inner base 38 and the N ⁺ -type Si _1-x Ge _x outer base 36.

FIG. 2A shows an energy band structure before bonding. In a semiconductor doped with impurities at a high concentration, as shown in FIG. 2A, it is known that the Fermi level E _f enters the allowable band and enters a degenerate state.

Next, FIG. 2B shows the P ⁺ N ⁺ junction energy band structure of the P ⁺ type semiconductor and the N ⁺ type semiconductor thus doped at a high concentration. Even when no voltage is applied, electrons pass from the conduction band of the N ⁺ type semiconductor to the valence band of the P ⁺ type semiconductor by the tunnel effect.

Next, FIG. 2C shows an energy band structure when a voltage is applied in the reverse direction. When a reverse bias is applied, the depletion layer width of the P ⁺ N ⁺ junction is narrowed, so that the electric field applied to the junction increases and the tunnel current easily flows.

  Next, FIG. 2D shows a case where a voltage is applied in the forward direction. When forward voltage is applied, the tunnel current is difficult to flow, so the current value decreases.

  Further, FIG. 2E shows a case where a forward voltage is applied. When the forward voltage increases, the diffusion current starts to flow, and the current value increases. Thus, since the energy band changes with voltage application, the tunnel diode exhibits a current-voltage characteristic as shown in FIG.

  It should be noted that the tunnel diode exhibits a low resistance when the voltage is around 0 volts and when the reverse direction is applied. The present invention makes good use of this characteristic.

Next, the operation of the bipolar transistor using the tunnel junction base will be described with reference to FIG. N and P in the figure represent the polarity of the semiconductor. In general, bipolar transistors are used with a common emitter. FIG. 3A shows a voltage relationship in the common emitter transistor grounded emitter operation. The transistor operates with a forward bias applied between the base and the emitter. Since the external base is formed of P ⁺ type, the base resistance Rb is large.

FIG. 3B shows the voltage relationship in the grounded emitter operation of the bipolar transistor according to the present invention. Since the external base is N ⁺ type, the base resistance Rb is small. It can be seen that there is a tunnel junction between the outer base and the inner base, and this tunnel junction is biased in the opposite direction. As described above, a tunnel junction causes a current to flow due to a tunnel current at a reverse voltage.

Therefore, according to the present invention, by using an N ^{+ type} external base doped with a high concentration of impurities, the base resistance can be drastically reduced to about a half of that of the conventional P ^{+ type} external base. It becomes. FIG. 10 shows the relationship between the maximum oscillation frequency Fmax and the collector current Ic. Fmax can be increased by about 20 to 30% due to the base resistance reduction effect of the present invention.

In the description, an NPN type heterobipolar transistor using a Si _1-x Ge _x base is taken as an example, but an NPN type bipolar transistor using an Si base (that is, x = 0 in the Si _1-x Ge _x base). It is obvious that the same effect of reducing the base resistance can be obtained in. However, considering a second embodiment described later, the internal base is preferably made of SiGe or SiGeC, and more preferably made of SiGeC.
(Second Embodiment)
Next, a second embodiment corresponding to claim 3 will be described. In this embodiment, a polycrystalline Si _1-xy Ge _{x Cy} layer (1 ≧ x> 0, 1 ≧ y ≧ 0) doped with N-type at a high concentration is used as the N ⁺ external base material. .

The tunnel probability T _t in quantum mechanics is given by (Equation 1) below.
(Equation 1)
T _t = exp [-2 ^5/2 m ^1/2 Eg ^3/2 / 3heE]
Here, m is the effective mass, Eg is the band gap of the material, h is the Planck constant, e is the elementary charge, and E is the electric field applied to the junction.

When attention is paid to Eg, it is understood that the tunnel probability can be increased by using a material having a small Eg, and the tunnel current of the tunnel junction 24 can flow efficiently. Polycrystalline Si _1-xy Ge _{x Cy} is generally used for polycrystalline Si,
Eg polycrystalline Si of Eg> polycrystalline Si _1-xy Ge _x C _y layer
Thus, it can be seen that it is effective to manufacture the N ⁺ external base with a polycrystalline Si _1-xy Ge _x C _y layer.
(Other embodiments)
Not only a single polysilicon type but also a double polysilicon type can be applied as shown in FIG. In this case, the tunnel coupling 24 is formed between the N-type second polysilicon and the Si _1-x Ge _x internal base 38.

  Further, arsenic (As), which is an N-type dopant, is more easily activated at a lower temperature than boron (B), which is a P-type dopant, and this structure is effective in reducing the base resistance.

  Since the base resistance can be reduced by the present invention, a high-performance NPN bipolar transistor can be manufactured.

The figure which shows the cross-section of the hetero bipolar transistor in 1st Embodiment Diagram showing operating principle of tunnel junction The figure which shows the voltage relationship at the time of the transistor operation | movement in 1st Embodiment. The figure which shows the manufacturing process in 1st Embodiment. The figure which shows the manufacturing process in 1st Embodiment. The figure which shows the manufacturing process in 1st Embodiment. The figure which shows the manufacturing process in 1st Embodiment. The figure which shows the modification of 1st Embodiment. The figure which shows the cross-sectional structure of the conventional hetero bipolar transistor Diagram showing the relationship between maximum oscillation frequency and collector current The figure which shows the case where this invention is applied to a double polysilicon type bipolar transistor

Explanation of symbols

10 Si substrate 11 Collector layer 12 P ⁺ region 13 for separation Third insulator 14 First insulator 15 Second insulator 16 N ⁺ collector lead layer 17 Single crystal region 18 Polycrystalline region 19 Fourth insulating layer 20 Si _1-x Ge _x layer 21 Si layer 22 Fifth insulating layer 23 Sixth insulating layer 24 Tunnel junction 25 Side wall 26 Seventh insulator 27 Emitter opening 28 N ⁺ polysilicon emitter 29 Ti silicide 30 Interlayer insulation Film 31 Base electrode 32 Emitter electrode 33 Collector electrode 34 Base / emitter formation region 35 Collector extraction region 36 N ⁺ -type Si _1-x Ge _x external base 37 N ⁺ -type Si external base 38 P ⁺ -type Si _1-x Ge _x internal Base 39 Si layer 40 External base region 41 P ⁺ type Si _1-x Ge _x external base 42 P ⁺ type Si external base

Claims (3)

A substrate having a first semiconductor layer of a first conductivity type that functions as a collector of a bipolar transistor;
A second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the substrate and functioning as a base of a bipolar transistor;
A third semiconductor layer of a first conductivity type provided on the second semiconductor layer and functioning as an emitter of a bipolar transistor;
In a bipolar transistor comprising an external base layer provided to connect to the second semiconductor layer,
The semiconductor device according to claim 1, wherein the external base layer is of a first conductivity type. The semiconductor device according to claim 1,
The substrate is a Si layer,
The first semiconductor layer is a Si layer;
The second semiconductor layer is a Si _1-xy Ge _{x Cy} layer (1 ≧ x> 0, 1 ≧ y ≧ 0),
The semiconductor device, wherein the third semiconductor layer is a Si layer. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the external base layer is an n-type polycrystalline Si _1-xy Ge _{x Cy} layer (1 ≧ x> 0, 1 ≧ y ≧ 0).

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