JPH0992742A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the operational performance and the current amplification factor of a bipolar transistor while preventing the digital-analog interference. SOLUTION: At the time of fabricating a semiconductor device where vertical bipolar transistors, lateral bipolar transistors and MOS transistors are arranged on one substrate 10, second conductivity type buried diffusion layers 13a, 13b are formed deeper than the buried collector layer 14a of vertical bipolar transistor under the regions 11b, 11c for forming a lateral bipolar transistor and a MOS transistor of the substrate 10. The collectorlayer 17b of the lateral bipolar transistor is formed in the same process as that for forming a first conductivity type isolation layer 17a between the well layer 17c of the MOS transistor and each transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a Bi-MOS structure in which a bipolar transistor and a MOS transistor are arranged on the same substrate, and a semiconductor device.

[0002]

2. Description of the Related Art A semiconductor device 6 shown in FIG. 6 (f) is a semiconductor device having a so-called Bi-MOS structure, and the same substrate 1 is used.
A vertical bipolar transistor (hereinafter referred to as V-Tr) 10a and a horizontal bipolar transistor (hereinafter, referred to as V-Tr) 0
L-Tr) 10b and a MOS transistor (hereinafter, referred to as “L-Tr”)
MOS-Tr) 10c is arranged. The semiconductor device 6 is formed by the following procedure, for example.

First, as shown in FIG. 5A, a first oxide film 12 is formed on the surface of a P-type semiconductor substrate 11 by an oxidation treatment.
After forming the film, the V-Tr regions 11a and L for forming the V-Tr by the known lithography method and etching method.
The portion of the first oxide film 12 above the L-Tr region 11b forming the −Tr is removed. Then, the semiconductor substrate 11 is heat-treated in an atmosphere containing antimony oxide to obtain V-Tr.
An N type buried collector layer 14a is formed in the region 11a, and an N type buried diffusion layer 14b is formed in the L-Tr region 11b.

After removing the first oxide film 12, as shown in FIG.
As shown in (b), the N-type epitaxial layer 15 is formed on the upper surface of the semiconductor substrate 11, and the substrate 10 including the epitaxial layer 15 and the semiconductor substrate 11 is formed.

Next, as shown in FIG. 5C, a second oxide film 16 is formed on the surface of the substrate 10 by oxidation treatment.
Thereafter, a well layer 17c is formed in the MOS-Tr region 11c forming the MOS-Tr by a diffusion layer forming technique such as a known lithography method, an ion implantation method, and a heat treatment method, and the isolation layer 17 is provided between the transistor regions.
a is formed. The well layer 17c and the isolation layer 17a are formed in the same step as a P-type diffusion layer reaching the P-type semiconductor substrate 11 from the front surface side of the substrate 10.

Next, as shown in FIG. 6D, a LOCOS film 18 is formed on the surface of the substrate 10 by a known LOCOS (Local Oxidation of Silicon) method. Then, a thin oxide film 19 is formed on the surface of the substrate 10 exposed from the LOCOS film 18, and a polysilicon gate 20 is formed on the thin oxide film 19 in the MOS-Tr region 11c. Then, by a known diffusion layer forming technique, V-T
A base layer 21a is formed in the r region 11a, and an emitter layer 21b and a collector layer 21c are formed in the L-Tr region 11b. These diffusion layers are formed in the same step as P-type diffusion layers having a depth that does not reach the buried collector layer 14a and the buried diffusion layer 14b.

Next, as shown in FIG. 6E, an emitter layer 22a and a collector contact layer 22b are formed in the V-Tr region 11a by a known diffusion layer forming technique, and L-
Forming a base contact layer 22c in the Tr region 11b,
A source layer 22d and a drain layer 22e are formed in the MOS-Tr region 11c. These diffusion layers are formed in the same step as N-type diffusion layers shallower than the base layer 21a formed in the V-Tr region 11a.

After performing the above steps, as shown in FIG. 6 (f), a third oxide film 23 is formed on the substrate 10 by the CVD (Chemical Vapor Deposition) method, and the third electrode film 23 is formed by the known electrode forming method. An aluminum electrode 24 connected to the impurity diffusion layer is formed. As a result, the same substrate 10
N-channel MOS-Tr1 with V-Tr10a having NPN junction and L-Tr10b having PNP junction on top
0c is formed to form the semiconductor device 6.

[0009]

However, the semiconductor device manufacturing method and the semiconductor device described above have the following problems. That is, in the manufacturing process of the semiconductor device, V
-Tr10a embedded collector layer 14a and L-Tr1
Since the buried diffusion layer 14b of 0b is formed in the same step, the buried collector layer 14a and the buried diffusion layer 14b have the same depth. For this reason,
When the epitaxial layer 15 is thinned to narrow the width of the base layer 21a in the depth direction for the purpose of improving the high speed operation performance of the V-Tr 10a, the depth position of the buried diffusion layer 14b is the same as that of the buried collector layer 14a. To rise.
Then, due to the increase of the depth position of the buried diffusion layer 14b, the effective base concentration of the L-Tr 10b increases, and the current amplification factor hFE of the L-Tr 10b decreases.
As described above, the high-speed operation performance of the V-Tr 10a and the LT
There is a trade-off relationship with the current amplification factor of r10b, and both cannot be improved.

Further, the well layer 17 of the MOS-Tr 10c
Since the c is formed in the same step as the isolation layer 17a, the well layer 17c is connected to the semiconductor substrate 11. Therefore, not only it is not possible to apply an independent arbitrary voltage to the well layer 17c, but also
A so-called digital-analog interference occurs in which noise in the semiconductor substrate 11 passes through the well layer 17c and enters the signal circuit from the source layer 22d and the drain layer 22e.

Therefore, the present invention improves the operating performance of the vertical bipolar transistor and the current amplification factor of the horizontal bipolar transistor, and prevents digital-analog interference between the bipolar transistor and the MOS transistor. An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device that can be manufactured.

[0012]

According to the method of manufacturing a semiconductor device of the present invention for achieving the above object, when a vertical bipolar transistor, a lateral bipolar transistor and a MOS transistor are formed on the same substrate, the lateral bipolar transistor is formed. A collector layer of the first MOS transistor disposed between the well layer of the MOS transistor and each of the transistors.
It is characterized in that it is formed in the same step as the conductive type isolation layer.

Further, a step of forming a buried diffusion layer of the second conductivity type deeper than the buried collector layer of the vertical bipolar transistor under the lateral bipolar transistor formation region and the MOS transistor formation region on the substrate. It is characterized by having.

In the method of manufacturing a semiconductor device, the collector layer of the lateral bipolar transistor is formed in the same step as the isolation layer and the well layer of the MOS transistor. Therefore, the collector layer is formed in the same step as the base layer of the vertical bipolar transistor. Compared with the case of forming
The collector layer is deeply formed without increasing the number of steps. Therefore, a semiconductor device having a lateral bipolar transistor having a large PN junction area is formed.

Further, since the buried diffusion layer below the lateral bipolar transistor is formed deeper than the buried collector layer of the vertical bipolar transistor, the buried diffusion layer and the buried collector layer are formed in the same step as compared with the case where the buried diffusion layer and the buried collector layer are formed in the same step. Thus, the epitaxial layer portion above the buried diffusion layer becomes wider. Therefore, the effective base region between the emitter layer and the collector layer of the lateral bipolar transistor is widened, and the current amplification factor of the lateral bipolar transistor is improved.

Further, since the second conductivity type buried diffusion layer is formed under the first conductivity type well layer in the MOS transistor in the same step as the buried diffusion layer of the lateral bipolar transistor, only the buried diffusion layer is formed. The connection between the well layer and the semiconductor substrate is prevented without providing a special step for forming the well.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments to which the method for manufacturing a semiconductor device of the present invention is applied will be described in detail below with reference to the drawings. Here, a vertical bipolar transistor having an NPN junction (hereinafter referred to as V-Tr) and a PNP
A lateral bipolar transistor having a junction (hereinafter, L-
And a N-channel MOS transistor (referred to as MOS-Tr) are arranged on the same substrate as an example of a method for forming a Bi-MOS structure semiconductor device.
The first conductivity type is P type and the second conductivity type is N type. 1 and 2 are views for explaining the manufacturing method according to claims 1 and 2 of the present invention. First, the manufacturing of the semiconductor device according to claims 1 and 2 will be described with reference to these figures. A first embodiment of the method will be described.

As shown in FIG. 1A, a first oxide film 12 having a thickness of about 300 nm is formed on the surface of a semiconductor substrate 11 made of P-type (that is, first conductivity type) silicon by an oxidation treatment. . After that, a region (hereinafter, referred to as “V-Tr”) to be formed by a known lithography method and etching method.
A portion of the first oxide film 12 above the V-Tr region) 11a is removed. Then, by a known lithography method and ion implantation method, a region for forming L-Tr (hereinafter, L-Tr) is formed.
-Tr region) 11b and MOS-Tr forming region (hereinafter referred to as MOSTr region) 11c on the surface side of the semiconductor substrate 11, an implantation region formed by introducing phosphorus (P) ions as N-type impurities. 13 is formed.

At this time, the ion implantation energy is finally set to the maximum energy in the range in which the surface of the P-type semiconductor substrate 11 is not P-inverted. Thereby, the implant region 1
When the N-type impurity concentration on the surface of No. 3 is lowered and an epitaxial layer is formed on the semiconductor substrate 11 later,
The diffusion of the type impurities upward into the epitaxial layer is suppressed, and a buried layer formed by diffusing the N type impurities is formed at a deep position of the semiconductor substrate 11. Therefore, here, phosphorus ions are implanted into the semiconductor substrate 11 with an implantation energy of 400 keV. Further, the implantation amount of phosphorus ions is set such that the P-type well layer of the MOS-Tr and the collector layer of the L-Tr which will be formed later and the semiconductor substrate 11 are formed.
The minimum dose required to secure the withstand voltage between and. This suppresses the operation of the PNP junction formed by the well layer of the MOS-Tr, the buried diffusion layer, and the semiconductor substrate. Therefore, here, 10 ¹³ pieces / cm
Phosphorus ions with a dose of about ² are implanted into the semiconductor substrate 11.

Next, after removing the resist pattern, as shown in FIG. 1B, a heat treatment is carried out at 1200 ° C. for several hours in an atmosphere containing antimony oxide to thereby form a semiconductor in the V-Tr region 11a. A buried collector layer 14a formed by diffusing antimony, which is an N-type impurity, is formed on the surface side of the substrate 11. Along with this, the phosphorus ions in the implantation region (13) are deeply diffused into the semiconductor substrate 11, and the L-Tr region 11b and the MOS-Tr region 11c are
Then, N type buried diffusion layers 13a and 13b deeper than the buried collector layer 14a are formed.

Next, after removing the first oxide film 12,
As shown in FIG. 1C, the N-type epitaxial layer 15 is formed on the upper surface of the semiconductor substrate 11, and the epitaxial layer 1 is formed.
A substrate 10 composed of 5 and a semiconductor substrate 11 is formed. Here, the upper diffusion of impurities from the buried diffusion layers 13a, 13b into the epitaxial layer 15 is suppressed, and the buried diffusion layers 13a, 13b
The surface of 13b is deeper.

Then, as shown in FIG. 1D, a second film having a film thickness of about 50 nm is formed on the surface of the substrate 10 by oxidation treatment.
The oxide film 16 is formed. Then, the isolation layer 17a is formed between the transistor regions 11a, 11b, and 11c by a known diffusion method such as a lithography method, an ion implantation method, and a heat treatment method, and the L-Tr region 1 is formed.
1b, the collector layer 17b is formed, and the MOS-Tr region 1 is formed.
A well layer 17c is formed on 1c. These isolation layer 17a, collector layer 17b and well layer 17c
Is formed in the same step as a P-type diffusion layer reaching the semiconductor substrate 11 from the front surface side of the substrate 10.

Then, as shown in FIG. 2E, the LOCOS (Local Oxidation of Silicon) method is used to form a LOCOS film having a thickness of about 400 nm on the surface of the substrate 10.
The S film 18 is formed. Next, a thin oxide film 19 having a thickness of about 30 nm is formed on the surface of the active region of the substrate 10 exposed from the LOCOS film 18. Then the known CVD
Method, lithographic method and etching method
A polysilicon gate 20 is formed on the thin oxide film 19 in the S-Tr region 11c.

Next, by a known diffusion layer forming technique, V
The base layer 21a is formed in the -Tr region 11a, and the L-Tr
The emitter layer 21b is formed in the region 11b, and LT
A collector contact layer 21c is formed above the collector region 17b in the r region 11b. These diffusion layers are formed by diffusing boron (B), which is a P-type impurity, for example, and the buried collector layer 14a and the buried diffusion layers 13a and 13 are formed.
The P-type diffusion layer having a depth not exceeding b is formed in the same step. As a result, the collector layer 17b of the L-Tr region 11b is formed deeper and the PN junction area of the collector contact layer 21c facing the emitter layer 21b is widened as compared with the conventional example without increasing the number of steps.

Next, as shown in FIG. 2 (f), the V-Tr region 1 is formed by a known diffusion layer forming technique as in the conventional example.
1a includes an emitter layer 22a and a collector contact layer 22b
To form a base contact layer 2 on the L-Tr region 11b.
2c is formed, and the source layer 22 is formed in the MOS-Tr region 11c.
d and the drain layer 22e are formed. These diffusion layers are formed by diffusing, for example, arsenic (As) which is an N-type impurity, and are formed in the same step as N-type diffusion layers shallower than the base layer 21a formed in the V-Tr region 11a.

After performing the above steps, as shown in FIG. 2 (g), a CVD (Chemical Vapor Depo Depo
sition) method, the third oxide film 23 is formed on the substrate 10, and the aluminum electrode 24 connected to each impurity diffusion layer is formed by a known electrode forming method. As a result, the V-Tr 10a and the V-Tr 10b are formed on the same substrate 10.
And the MOS-Tr 10c are arranged to form the semiconductor device 1.

The semiconductor device 1 formed as described above
Is greater than the P of the collector layer 17b in the L-Tr 10b with respect to the width in the depth direction of the base layer 21a of the V-Tr 10a, as compared with the semiconductor device formed by the conventional method.
The N junction area and the effective base region on the buried diffusion layer 13a are wide. Therefore, it is possible to improve the high-speed operation performance of the V-Tr 10a and the current amplification factor of the L-Tr 10b. Furthermore, the buried diffusion layer 13a under the MOS-Tr 10c prevents the well layer 17c from being connected to the semiconductor substrate 11 and prevents digital-analog interference.

Next, FIGS. 3A to 3D are views for explaining the manufacturing method of claim 5 in the present invention, and the semiconductor device of claim 5 will be described below with reference to these figures. An example of the manufacturing method will be described. In the method of manufacturing a semiconductor device according to the second embodiment, as shown in FIG. 3A, a substrate 30 is formed by forming an insulating substrate 32 on a semiconductor substrate 31 and forming an epitaxial layer 15 on the upper surface thereof. Then, the same method as in the first embodiment is used to form each transistor.
The insulating substrate 32 may be an insulating layer formed on the surface of the semiconductor substrate 31. First, the substrate 30 formed with the N-type buried collector layer 34 is formed on the bottom of the N-type epitaxial layer 15 in the V-Tr region 11a.

Next, in the step shown in FIG. 3B, in the same manner as shown in FIG. 1D in the first embodiment, the isolation layer 17a is formed between the transistor regions while reaching the insulating substrate 32. , The collector layer 17b is formed in the L-Tr region 11b, and the well layer 17c is formed in the MOS-Tr region 11c.

Thereafter, in the step shown in FIG. 3C, the base layer 21a is formed in the V-Tr region 11a by the same procedure as shown in FIGS. 2E and 2F in the first embodiment. , The emitter layer 21b and the collector contact layer 21c are formed in the L-Tr region 11b, and then the V-Tr region 11a
An emitter layer 22a and a collector contact layer 22b are formed on the substrate, a base contact layer (not shown) is formed on the L-Tr region 11b, and a source layer 22d and a drain layer 22e are formed on the MOS-Tr region 11c. However, since the N-type buried diffusion layer is not formed below the L-Tr region 11b here, as shown in FIG.
FIG. 4 shows a layout of the impurity diffusion layers formed in the L-Tr region 11b so that the N-type epitaxial layer 15 between b and the emitter layer 21b is connected to the N-type base contact layer 22c. To change.

After the above, the step shown in FIG. 3D is performed in the same manner as shown in FIG. 2G in the first embodiment,
The semiconductor device 4 is completed. As described above, the semiconductor device 4 including the L-Tr 10b having a large current amplification factor as in the first embodiment is formed without increasing the number of steps as compared with the conventional example.

In each of the above embodiments, when the first conductivity type is N type and the second conductivity type is P type, a vertical bipolar transistor having a PNP junction and a lateral bipolar transistor having an NPN junction are provided. , P channel M
The OS transistor and the OS transistor are formed over the same substrate. Also,
The material used in each of the above embodiments is merely an example, and the present invention is not limited to the above.

[0033]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the number of steps can be reduced by forming the collector layer of the lateral bipolar transistor in the same step as the isolation layer and the well layer of the MOS transistor. The collector layer is deepened to increase its PN junction area without increasing it, and the buried diffusion layer of the lateral bipolar transistor is formed deeper than the buried collector layer of the vertical bipolar transistor. The effective base region between the collector layer and the collector layer can be expanded. Also, in the same process as the buried diffusion layer of the lateral bipolar transistor,
By forming the buried diffusion layer of the second conductivity type under the well layer of the first conductivity type in the MOS transistor, the well layer and the semiconductor substrate can be formed without providing a special step for forming only the buried diffusion layer. The connection with can be prevented. Therefore, in a semiconductor device in which a vertical bipolar transistor, a horizontal bipolar transistor, and a MOS transistor are arranged on the same substrate, it is possible to improve the operating performance of the vertical bipolar transistor and the current amplification factor of the horizontal bipolar transistor. In addition, it is possible to prevent digital-analog interference between the bipolar transistor and the MOS transistor.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram (1) of a semiconductor device to which the present invention is applied.

FIG. 2 is a manufacturing process diagram (2) of a semiconductor device to which the present invention is applied.

FIG. 3 is a manufacturing process diagram of another semiconductor device to which the present invention is applied.

FIG. 4 is a layout diagram of main part diffusion layers of another semiconductor device.

FIG. 5 is a manufacturing process diagram (1) of a conventional semiconductor device.

FIG. 6 is a manufacturing process diagram (2) of the conventional semiconductor device.

[Explanation of symbols]

 1,4 Semiconductor device 10,30 Substrate 10a V-Tr (vertical bipolar transistor) 10b L-Tr (horizontal bipolar transistor) 10c MOS-Tr (MOS transistor) 11 Semiconductor substrate 11a V-Tr region 11b L-Tr region 11c MOS-Tr regions 13a and 13b Buried diffusion layer 14a Buried collector layer 15 Epitaxial layer 17a Isolation layer 17b Collector layer (of L-Tr) 17c Well layer 21b Emitter layer (of L-Tr) 32 Insulating substrate

Claims (5)

[Claims] 1. A semiconductor in which a vertical bipolar transistor, a lateral bipolar transistor, and a MOS transistor are formed on a substrate composed of a semiconductor substrate of a first conductivity type and an epitaxial layer of a second conductivity type formed on the semiconductor substrate. A method of manufacturing a device, wherein the collector layer of the lateral bipolar transistor is formed in the same step as the well layer of the MOS transistor and the isolation layer of the first conductivity type disposed between the transistors. Of manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a step of forming a buried collector layer of a second conductivity type in a formation region of the vertical bipolar transistor on the substrate, and a method of forming a horizontal bipolar transistor on the substrate. In the lower part of the formation region and the lower part of the formation region of the MOS transistor,
And a step of forming a buried diffusion layer of the second conductivity type deeper than the buried collector layer. 3. A vertical bipolar transistor, a horizontal bipolar transistor, and a MOS transistor are arranged on a substrate composed of a semiconductor substrate of a first conductivity type and an epitaxial layer of a second conductivity type formed on the semiconductor substrate. In the semiconductor device, the lateral bipolar transistor includes a well layer of the MOS transistor and a collector layer formed in the same step as the isolation layer of the first conductivity type disposed between the transistors. A semiconductor device characterized by: 4. The semiconductor device according to claim 3, wherein a buried collector layer of the second conductivity type disposed in the vertical bipolar transistor and a position deeper than the buried collector layer of the vertical bipolar transistor are provided. A semiconductor device comprising: a second bipolar buried diffusion layer disposed below a lateral bipolar transistor and below the MOS transistor. 5. A vertical bipolar transistor, a horizontal bipolar transistor and a MOS are formed on a substrate composed of an insulating substrate and an epitaxial layer formed on the insulating substrate.
A method of manufacturing a semiconductor device, including forming a transistor, wherein the collector layer of the lateral bipolar transistor is formed in the same step as a well layer of the MOS transistor and an isolation layer arranged between the transistors. And a method for manufacturing a semiconductor device.