JPH02161767A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the speed of an I<2>L device by locally forming the emitter and collector of a lateral transistor and the base contact area of a longitudinal transistor adjacent to a buried insulating film. CONSTITUTION:An n<+> type buried layer 12, n<-> type semiconductor layer 13, and oxide film 14 are formed on a semiconductor substrate. Then an Si nitride film 15 which covers an activated area is formed and a buried insulating film 16 which insulates a lateral transistor(Tr) and longitudinal Tr areas from each other is formed by selective oxidation. Thereafter, etching and side etching are respectively performed to the films 16 and 14. By this process, the layer 13 is exposed in a birdbeak part. After exposing the layer 13, the film 15 is removed and an n-type area 19 corresponding to a base 1 area 18 and collector area is formed. Then a patterned polycrystalline Si film 20 is formed. After forming the film 20, the film is conducted by diffusing boron. Then an n<+> type contact area 24 is formed by diffusing an n type impurity and, thereafter, electrodes 25 and 26 are formed. Therefore, all of unnecessary parts are contained in the film 16.

Description

[Detailed Description of the Invention] [Summary] The so-called 1! which combines a horizontal transistor and a vertical transistor. Regarding a method suitable for manufacturing a semiconductor device called L, it is possible to easily produce a semiconductor device with improved switching characteristics by eliminating unnecessary junction-related capacitance or carrier accumulation in unnecessary regions. A method for manufacturing a semiconductor device including a lateral transistor and a vertical transistor, which includes a step of forming an insulating film on a surface of a conductive semiconductor layer, and then forming a lateral transistor. forming a buried insulating film by selective oxidation to insulate the transistor region from the vertical transistor region, and then removing the bird's beak portion at a predetermined side of the buried insulating film. opening a window exposing the layer, and then a conductor made of polycrystalline silicon containing impurities of opposite conductivity type connecting said window in the lateral transistor region and said window in the vertical transistor region. forming a layer and then diffusing impurities in the conductor layer to form emitter and collector regions in the lateral transistor regions and base contact regions in the vertical transistor regions; Configure it so that it includes.

[Industrial application field]

The present invention relates to a method suitable for manufacturing a so-called 1''L semiconductor device that combines a lateral transistor and a vertical transistor.

The 1"L is a composite of a so-called reverse structure particle transistor, in which the emitter and collector are reversed from the normal planar bipolar transistor, and a complementary lateral transistor, with the base of this transistor as the collector. This logic element is a logic element with a structure.By applying a DC power supply voltage to the emitter of a lateral transistor, this transistor acts as an injector that injects charge into the base of a reverse structure particle transistor. Structure Particle transistor operates as an inverter, and it has a small logic amplitude, can operate at high speed and with low electrode consumption, and at the same time can be highly integrated, and is the same as a conventional bipolar integrated circuit. It is attracting attention as something that can coexist on chips.

[Conventional technology]

FIGS. 13(a) and 13(fb) show a cutaway side view and a plan view of a main part for explaining a conventional I2L device.

In the illustrated I''L device, p-type head regions 2 and 3 are formed in an epitaxially grown n-type semiconductor layer 1;
An n-type region 4 is formed in a p-type head region 3, and a portion QL surrounded by a broken line is a pnp lateral transistor for an injector, and a portion Qv surrounded by a broken line is an npn transistor for an inverter. The parts that constitute the vertical transistors are necessary for the part Q, which is the active region, and the junction included in Qv to function as a transistor, and the parts constituting the other junctions are In operation, it plays the role of a conductor.

This I"L device can be manufactured by applying a normal bipolar integrated circuit manufacturing method, and a partial oxidation technique is used to isolate the I"L element group.

The 1”L features within a single relatively large base area:
Since a collector is formed that corresponds to a conventional emitter, and there is no need for insulation separation between the collectors, the above-mentioned high degree of integration can be achieved.

[Problem to be solved by the invention]

Considering the above-mentioned function of I"L, the semiconductor region necessary for I"L is the opposing p-type region in a pnp lateral transistor, and the area under the collector region in an npn vertical transistor. It is limited to the base region and emitter region, and the other base region only plays the role of a conductor, and is caused by the capacitance of the junction and the accumulated charge of carriers in the unnecessary region. The switching characteristics are deteriorated.

According to the present invention, in the above-mentioned type of semiconductor device, by leaving only the necessary active region and forming an insulating layer on other unnecessary parts, it is possible to easily realize a semiconductor device with improved functions such as switching speed. In addition, in order to easily realize an I2L device in which the base regions of the vertical transistors of the 12L device are divided and the bases are connected to each other on the buried insulating film, furthermore, The bird's beak portion of the buried insulating film is removed and impurities are introduced into the exposed semiconductor layer to form the emitter region and collector region of the lateral transistor, as well as the base contact region of the vertical transistor. and a conductor layer connecting the base contact region and the collector region.
``We are trying to make it easy to realize L devices.

[Means to solve the problem]

According to the present invention, in a semiconductor device including a horizontal transistor and a vertical transistor, the vertical transistor has (a) a base region having an area necessary for transistor operation and distributed in a distributed manner, fb) each a buried insulating film that surrounds the base regions and insulates them from each other; (C1 a conductor layer that is on the buried insulating film and connects each base region; (dl a base connection provided on a part of the conductor layer; t
el collector connections formed on each of the distributed base regions;

That is, a plurality of mesa portions are formed on one surface of a semiconductor substrate of one conductivity type. The emitter region and collector region of the lateral transistor in the I2L device are formed in the 10th mesa portion, and the vertical transistor is formed in the 2019th mesa portion. A buried insulating film that surrounds a plurality of mesa portions and insulates them from each other is provided on one surface of the substrate. Preferably, the lateral and vertical transistors have the minimum dimensions necessary for transistor operation; for this purpose, the emitter and collector of the lateral transistor and the base contact area of the vertical transistor are It is formed locally adjacent to the embedded insulating film. In order to form these regions, a predetermined side portion of the upper surface of the mesa portion is exposed, and impurities are introduced from the exposed mesa portion.
Preferably, the localized region is formed by:
By removing the bird's beak generated at the same time when forming the buried insulating film by local oxidation, and introducing the impurity through the exposed mesa portion, each region with the minimum dimensions can be achieved. can do. The collector region of the horizontal transistor and the base region of the vertical transistor.
The contact region is electrically connected to the contact region by a conductor layer disposed on the buried insulating film between them. a plurality of vertical transistors are formed in a series of a plurality of mesa portions;
These transistors are insulated from each other by a buried insulating film, and in order to set their respective bases at a common potential, the base contact layers of adjacent vertical transistors are electrically connected to each other by a conductor layer. A feature of the present invention is that a buried insulating film is applied to the vertical transistor of I"L.
A high speed L device is achieved.

As described above, the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a lateral transistor and a vertical transistor, and includes a semiconductor layer of one conductivity type (for example, an n-type semiconductor layer). A step of forming an insulating film (for example, oxide film 14, etc.) on the surface of the semiconductor layer 13), and then forming a buried insulating film (for example, thick oxide film 16) to insulate the horizontal transistor region and the vertical transistor region.
) by selective oxidation, then opening a window to expose the semiconductor layer by removing bird's beak portions at predetermined sides of the buried insulating film; , a conductor layer made of polycrystalline silicon containing impurities of opposite conductivity type and connecting the window in the horizontal transistor region and the window in the vertical transistor region (
For example, a step of forming a polycrystalline silicon film 20) and then diffusing impurities in the conductor layer to form the emitter region and collector region in the lateral transistor region and the base region in the vertical transistor region. The method includes a step of forming a contact region.

[Effect]

By adopting the above-mentioned means, it is possible to easily manufacture an I''L type semiconductor device in which only necessary active regions exist and unnecessary parts are made into insulating layers to improve switching characteristics.

〔Example〕

Figures 1 (al and b) are plane explanatory diagrams of essential parts of a semiconductor device manufactured according to an embodiment of the present invention and fa), cut along line A-A' and viewed in the direction of the arrow. It shows a cutaway side view of the main part.

In the figure, 11 is a silicon semiconductor substrate, 12 is an n++
13 is an n-type semiconductor layer, 16 is an oxide film, 18 is a p'' type active Hebe region, 19 is an n-type region, 20 is a polycrystalline silicon film, 21 is a p+ type region 22 is a p+ type region of the injector The mold region 23 is an oxide film, 24 is an n++ contact)
SR regions 25 and 26 indicate electrodes, respectively.

Note that the pnp type transistor portion and the npn transistor portion are indicated in (a) of the figure.

Figures 2 to 7 are cross-sectional side views of important parts at key points in the process to explain the case of manufacturing the semiconductor devices shown in Figures 1 (al and (bl). This will be explained with reference to the drawings.It should be noted that the same symbols as those used in FIG. 1 indicate the same parts or have the same meanings.

See Figure 2 2l-1 Form an n+ type buried layer 12 and an epitaxially grown n- type semiconductor layer 13 with a thickness of about 2 [μm] on the p-plastic or n-type silicon semiconductor substrate 11 (see Figure 1). Until then, it is carried out using conventional techniques.

By applying a thermal oxidation method, the thickness can be reduced to, for example, 1000 mm.
~1300 (people) of oxidized M14 is formed.

+2+-3 Chemical vapor deposition (chemical vapor deposition).

A silicon nitride film 15 having a thickness of, for example, about 2,500 μm is formed by applying the CVD method, and this is patterned using normal photolithography to form a pnp transistor formation region and an npn transistor formation region. What covers the active region, such as the type transistor formation region, is left and the rest is removed.

Refer to Figure 3 +3)-1 By applying the selective thermal oxidation method, the thickness can be reduced to 1
．． A thick oxide film 16 of about 5 [μm] is formed. It goes without saying that this includes the oxide film 4.

+3)-2 In the next step, the oxide films 16 and 14 are etched to expose a part of the n-type semiconductor layer 13 around the active region, and in a later step, p-type impurities are introduced into the exposed portion. A p+ type impurity region is formed by etching the oxide films 16 and 14, but the etching range of the oxide films 16 and 14 must be limited in order to prevent short-circuiting between adjacent elements through the p+ type impurity region. It won't happen.

Therefore, in this step, a mask 17 made of a photoresist film is formed (see especially the sandy area in FIG. 1 (al)). The etching of the n''' type half conductor layer is prevented. Note that symbol 52 indicates the area where the bird's beak will be formed.

Referring to FIG. 4, etching of the oxide film 16 and side etching of the oxide film 14 are performed.

By adopting this step, the n-type semiconductor layer portion 13 is exposed in a portion commonly called a bird's beak.

The remaining thickness of the oxide film 16 at this time was approximately 7000 C.

See Figure 5 The silicon nitride film 15 is removed.

+5) -2 A photoresist film mask (not shown) covering the pnp transistor formation region is formed.

By applying the ion implantation method, the acceleration energy can be reduced to 1
80 (KeV), and the dose was set to 2 x 1012 (
Boron ions are implanted at cm-23 to form the base region 18.

Same (by applying the ion implantation method, the acceleration energy is 360 (KeV) and the dose is 3X
Boron ions are implanted as IQ''(cffI-'') to form an n-type region 19 corresponding to the collector region 9.

By applying the CVD method (see Fig. 6), the thickness can be reduced to, for example, 400
Then, a polycrystalline silicon film 20 of about 1.5 cm is grown.

+61-2 Patterning of the polycrystalline silicon film 20 is performed by applying photolithography technology.

Boron is diffused to make the polycrystalline silicon film 20 conductive.

At this time, boron is also diffused into the n'' type semiconductor layer portion 13 exposed at the bird's beak portion, forming a p+ type region 21 and a p+ type region 22 of the injector. Since this is carried out in an oxidizing atmosphere, an oxide film 23 with a thickness of, for example, about 3,000 mm is formed on the entire surface.

See Figure 7(?)-1 By applying photolithography technology, windows for impurity diffusion are opened in the oxide films 23 and 14, and then,
An n++ contact region 24 is formed by diffusing n-type impurities.

(7) ~ 2 Opening windows for electrode contacts by applying photolithography technology, and then forming electrodes 25 and 26
form.

In the semiconductor device manufactured in this way, the first
All of the unnecessary portions explained with reference to FIG. 3 are made of oxide film 16.

Now, in the case of the present invention, since it is important to expose a part of the n-type semiconductor layer by etching the bird's beak portion, one of the preferred methods will be explained.

FIGS. 8 to 10 are cross-sectional side views of essential parts of a semiconductor device for explaining the preferred method, and the following description will be made with reference to these figures.

Refer to Figure 8 +81-1 The silicon semiconductor substrate 31 is thermally oxidized to a thickness of, for example, 500 mm.
An oxide film 32 of about 1,000 (persons) is formed.

By applying the CVD method, the thickness, for example, 1000 ~
A silicon nitride film 33 of approximately 4,000 (persons) thickness is formed.

By applying the CVD method, the thickness, for example, 1000 ~
A silicon dioxide film 34 having a thickness of about 4,000 people is formed.

+81-4 By applying photolithography technology, the silicon dioxide film 34 and the silicon nitride film 33 are patterned to expose the portion where a thick oxide film is to be formed.

Selective oxidation is performed by applying a thermal oxidation method to form a thick oxide film 35 having a thickness of, for example, about 8,000 to 15,000 C.

Refer to FIG. 9. During the thermal oxidation treatment in step (8)-5, an oxide film with a thickness of, for example, about 50 to 200 [people] is etched, which is formed on the exposed part (end face part) of the silicon nitride film 33. and remove it.

For example, side etching of the silicon nitride film 33 is performed by applying a dipping method using hot phosphoric acid as an etchant. The effective amount is approximately 5000 to 1 in the lateral direction.
It is about 0000 people.

Referring to FIG. 10, the oxide film 35 is etched to expose a portion of the silicon semiconductor substrate 31 at the bird's beak portion. At this time, the silicon dioxide film 34 is also removed by the etching.

GO)-2 The silicon nitride film 33 is removed together with the silicon dioxide film 34.

According to this technique, a thick oxide film 35 and a thin oxide film 32
It is possible to expose the three parts of the board at the bird's beak part while maintaining the board in a practically sufficient state.

As can be seen from the above description, the 1”L obtained according to the present invention
In this type of semiconductor device, the so-called active region is kept to the necessary minimum in order to obtain the junction necessary for transistor operation, and all parts that conventionally had only the function of a conductor are covered with an oxide film. Since the conductor function is carried out by the silicon layer on the oxide film, it is possible to eliminate the decrease in switching speed caused by the presence of an extra junction, that is, a capacitance.

Incidentally, it has been proposed that the propagation delay time tpd and drive current or power of an I''L device generally have a relationship as shown in FIG. 11(a).

That is, in a region where the drive current is relatively small, the intrinsic delay time is expressed as t=e, and as the current increases, the delay time becomes the intrinsic delay time. time) tat, resistive delay time (resistive delay time) jd
It has a characteristic determined by r. And f'') Lam depends on the junction capacitance and wiring capacitance and is inversely proportional to the current.In other words, p is the power consumption per gate.■ is the injector voltage Δ■. The logic amplitude α is the common base current gain α' CEII and emitter-base junction capacitance CclI represent the reverse base-grounded current gain and CclI represent the base-collector junction capacitance, respectively.

For traditional I2L devices, CEII/2 Ccll#
1/1 to 2/1, and 1" obtained according to the present invention
For the L device, the dimensions of the conventional I”L device are
When defined as shown in FIG. 1(b), the area of CEll becomes the width of the 6 (1, +22) d −W dip+ type region 21, which can be reduced to 1/10 or less.

(b) t, i are the rise of the collector structure IC and n
It depends on the amount of accumulated charge in the type region 13, where Q, - is the amount of accumulated charge in the n- region, ND is the impurity concentration in the n- region, SE is the emitter area Sc, and is expressed by the collector area.

In the structure of the semiconductor device obtained according to the present invention, St/Sc can be reduced to a fraction of that by reducing S.

fC) jdr depends on the base lateral resistance, jdr
tpd cannot be realized below the point where and jda intersect.

In the semiconductor device obtained according to the present invention, a polycrystalline silicon film is doped with boron at a high concentration when forming the base region, and a sheet resistance ρ similar to that of a normal base can be achieved.

There are advantages such as

The present invention can be modified in various ways, and other embodiments will now be described.

In general, a Schottky collector structure is known as an I"L device, and such a structure can also be used in the present invention without going through the step f71-1, that is, in the n++ contact region 24. This can be achieved by entering the following steps of +7)-2 and below without forming.

Further, in the above embodiment, the wiring was formed using the polycrystalline silicon film 20, but the polycrystalline silicon film 20 may be made of, for example, a heat-resistant metal doped with boron, such as tungsten, molybdenum, platinum, or other metals. In that case, a heat-resistant metal doped with boron is formed, this is buttered, and then an oxide film 23 is preferably formed and a diffusion process is performed there. It is preferable to perform this step to form p+ type regions 21 and 22.

Furthermore, the steps (61-1 to (61-3) above can be modified as follows.

By applying an ion implantation method or the like, the exposed n-type semiconductor layer portion 13 is doped with boron to form p+-type regions 21 and 22.

A metal layer such as Al, Mo, MoSi, etc. is deposited on the entire surface and then patterned.

+61-3 Insulating film 2 is formed by applying ordinary vapor phase growth method etc.
form 3.

If a heat-resistant metal material such as MO is used in the above step (61-2), if the steps in the above embodiment (7i1 and subsequent steps are carried out), a metal conductor can be used instead of polycrystalline silicon. Furthermore, if a metal material without heat resistance such as A1 is used, it can be applied to the case of forming a silicon collector that does not require a subsequent diffusion process.

In the semiconductor device shown in FIG.
npn) In the transistor part, if
All four sides of the f-type silicon nitride film were etched, but in order to miniaturize the device, etching was performed only on two opposing sides, or in some cases, only on one side to form the n-type semiconductor layer 1.
3 may be exposed.

FIG. 12 (al is an explanatory plan view of the main part of the npn transistor part in the I2L device in which the semiconductor layer 13 is exposed only on two opposing sides, and FIG. 12 (b) is +8+
Each figure represents a cutaway side view of the main part taken along the line B-B' as seen in Figures 1 to 7, and the same symbols as those used in Figures 1 to 7 indicate the same parts or have the same meaning. .

In the step (4)-5, the oxide films 16 and 14 are selectively etched to expose the n-type semiconductor layer 13 only in the portion indicated by the symbol 52, as shown in FIG. 12(a). Then, when performing p++ diffusion here to form a p+ type region 21, and opening a window as in step (?)-1, the upper and lower ends of the mask overlap the thick oxide film 16. By doing so, you can obtain alignment margin.

〔Effect of the invention〕

A method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a surface of a semiconductor layer of one conductivity type; A step of forming a buried insulating film that insulates the horizontal transistor region and the vertical transistor region by selective oxidation, and then removing bird's beak portions at predetermined sides of the buried insulating film. opening a window to expose the semiconductor layer;
Next, a step of forming a conductor layer made of polycrystalline silicon containing impurities of opposite conductivity type and connecting the window in the horizontal transistor region and the window in the vertical transistor region; The impurities in the conductor layer are diffused to form the emitter and collector regions in the lateral transistor region and the base and collector regions in the vertical transistor region.
(contact) forming a 5M area.

By employing the above structure, it is possible to easily manufacture an I''L type semiconductor device in which only necessary active regions exist and unnecessary parts are made into insulating layers to improve switching characteristics.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are an explanatory plan view of the main part of a semiconductor device manufactured according to an embodiment of the present invention, and a cutaway side view of the main part taken along the line A-A' shown in FIG. 1(a). , FIGS. 2 to 7 are cut-away side views of essential parts of a semiconductor device at key points in the process to explain one embodiment of the present invention, and FIGS. 8 to 10 show preferred examples of oxide film etching. FIG. 11(a) is a cut-away side view of the main part of the semiconductor device at key points in the process for explanation, and shows the switching time and drive current (power) of the semiconductor device manufactured according to one embodiment of the present invention. 11 (bl is a plan view of the main part showing the dimensions of the conventional I"L device, FIG. 12 fa) and (b)
13 is an explanatory plan view and a cutaway side view of the main part of a vertical transistor portion in an I2L device according to another embodiment of the present invention, and FIG. A cut-away side view and a plan view of the main parts are shown respectively for explaining the above. 16 is an oxide film, 18 is a p- type active base region, 19 is an n-type region, 20 is a polycrystalline silicon film, 21 is a p + type region 22 is a p + type region of the injector 23 is an oxide film, 24 is an n + type contact'
6M area, 25 and 26 indicate electrodes, respectively. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Shoji Aitani

Claims (1)

[Claims] A method for manufacturing a semiconductor device including a lateral transistor and a vertical transistor, comprising: forming an insulating film on the surface of a semiconductor layer of one conductivity type; forming a buried insulating film by selective oxidation to insulate the buried insulating film from the transistor region; and then exposing the semiconductor layer by removing bird's beak portions at predetermined sides of the buried insulating film. Next, a conductor layer made of polycrystalline silicon containing impurities of opposite conductivity type is formed to connect the window in the horizontal transistor region and the window in the vertical transistor region. and then diffusing impurities in the conductor layer to form an emitter region and a collector region in the lateral transistor region and a base contact region in the vertical transistor region. A method of manufacturing a semiconductor device, characterized in that: