JPH0645620A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the characteristic of the title device by a small occupied area and to miniaturize the title device by a method wherein an insulating film is opened, a lower-part polysilicon layer and an upper-part polysilicon layer are bring parts of the same conductivity type in a continuity, the area of a P-N junction part is increased and a resistance portion in the forward direction is reduced. CONSTITUTION:A p-type polysilicon region 20 and an n-type polysilicon region 21 in an upper-part polysilicon layer 19 as well as a p-type polysilicon region 14 and an n-type polysilicon region 15 in a lower-part polysilicon layer 13 are made conductive in respective corresponding regions in opening parts. Thereby, without increasing the area occupied on a semiconductor substrate 11 by the lower-part polysilicon layer 13 and the upper-part polysilicon layer 19, the area of the P-N junction of the p-type polysilicon regions 14, 20 to the n-type polysilicon regions 15, 21 can be made large. The resistance portion in the forward direction of a polysilicon diode formed between an anode electrode 24 and a cathode electrode 25 which are adjacent is reduced, and it is possible to realize the miniature and the high integration of a semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which, for example, a polysilicon diode or a capacitive element is provided by a polysilicon layer formed to form a semiconductor active element on a semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, a polysilicon layer is provided on a semiconductor substrate with an insulating layer interposed between the polysilicon layer and a complementary MOS transistor or bipolar / complementary M transistor.
There is a semiconductor device in which an active element such as an OS transistor is formed.

In such a semiconductor device, for example, a complementary type M
There is one in which a polysilicon diode and a capacitor are simultaneously formed by the same polysilicon layer provided in the process of forming an OS transistor. The related art of such a device will be described below with reference to FIGS. 12 is a cross-sectional view of the main part, FIG. 13 is a plan view of the main part, and FIG. 14 is a characteristic diagram corresponding to FIG.
FIG. 15 is a plan view of a main part of another conventional example shown in comparison with FIG. 13, and FIG. 16 is a characteristic diagram corresponding to FIG.

In FIGS. 12 and 13, 1 is a semiconductor substrate, and 2 is an insulating layer formed by thermally oxidizing the upper surface of the semiconductor substrate 1. Reference numeral 3 is a polysilicon layer formed on the upper surface of the insulating layer 2, in which p-type polysilicon regions 4 and n-type polysilicon regions 5 are formed by diffusing impurities so as to be arranged alternately. ing.

Reference numeral 6 denotes an interlayer insulating film laminated on the upper surface of the polysilicon layer 3. The p-type polysilicon region 4 and the n-type polysilicon region 5 and the electrode are formed through the through holes formed in the interlayer insulating film 6. 7 and 8 are electrically connected to each other. Then, a polysilicon diode is formed by the PN junction between the p-type polysilicon region 4 and the n-type polysilicon region 5 which are adjacent to each other in the polysilicon layer 3.

However, in the device having such a structure, when an attempt is made to increase the current flowing through the polysilicon diode, the voltage in the horizontal axis and the vertical axis in the vertical axis in FIG. 14 depend on the forward resistance of the PN junction. It is possible to obtain only the characteristic of the curve X having a gentle slope as shown by taking the current.

For this reason, as shown in FIG. 15, the area of the polysilicon layer 3'for forming the polysilicon diode is increased, the area of the PN junction is increased, and the horizontal axis in FIG. It is conceivable to have a characteristic of a steeply sloped curve Y as shown by taking the current as shown in FIG. Note that 7'and 8'are electrodes corresponding to the electrodes 7 and 8 in FIG.

However, increasing the area of the polysilicon layer 3'reduces the resistance of the PN junction in the forward direction and improves the characteristics, but it is against the direction of miniaturization and high integration of the semiconductor device. Will be.

Further, by increasing the thickness of the polysilicon layer 3, it is possible to increase the area of the PN junction portion while reducing the area occupied on the semiconductor substrate 1, and to reduce the resistance in the forward direction. Will be improved.

However, when the gates of complementary MOS transistors (not shown) formed on the same semiconductor substrate 1 are formed by using the same polysilicon layer 3, the polysilicon layer 3 is formed.
Since the thickness is thick, proper characteristics of the complementary MOS transistor cannot be obtained. Therefore, it is not possible to increase the thickness of the polysilicon layer and share it.

The insulating layer 2 formed on the semiconductor substrate 1 is interposed between the polysilicon layer 3 and the insulating layer 2
Is used as a dielectric layer between the electrodes, and the semiconductor substrate 1 and the electrodes 7 and 8 are used as both pole portions to form a capacitor.

However, with the capacitor thus constructed, it is difficult to form a capacitor having a desired appropriate capacitance due to the problem of parasitic capacitance, and good operation of the semiconductor device cannot be realized.

[0013]

When a polysilicon diode or a capacitor is simultaneously formed by the polysilicon layer provided for forming an active element on the semiconductor substrate as described above, the conventional polysilicon diode is If the resistance is reduced in order to improve the forward characteristics of the PN junction, there is a problem that the occupied area becomes large and the semiconductor device cannot be downsized, or the polysilicon layer cannot be shared. When forming, there was a problem due to parasitic capacitance. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device in which the above-mentioned problems are improved and miniaturization can be easily realized.

[0014]

The semiconductor device of the present invention comprises:
Lower polysilicon formed so that an insulating layer provided on a semiconductor substrate and at least one p-type polysilicon region and at least one n-type polysilicon region stacked on the insulating layer are alternately arranged in a plane direction. Layer and an overlying layer having an insulating film formed on the upper surface of the lower polysilicon layer, and p-type and n-type polysilicon regions of the lower polysilicon layer formed on the upper surface of the insulating film of the overlying layer. And an upper polysilicon layer having p-type polysilicon regions and n-type polysilicon regions which are alternately arranged corresponding to the upper side of the Has an opening formed so as to open in a direction intersecting the arrangement direction of the p-type polysilicon region and the n-type polysilicon region, and the polysilicon film adjacent to the insulating film by the opening. p of the corresponding same conductivity type layer
Type polysilicon regions and n-type polysilicon regions are electrically connected to each other, and electrodes are provided in each of the p-type polysilicon regions and the n-type polysilicon regions of the upper polysilicon layer. And, in addition,
An insulating layer provided on the semiconductor substrate, and a lower polysilicon layer formed so that p-type polysilicon regions and n-type polysilicon regions formed on the insulating layer are alternately arranged in the plane direction, The insulating film formed on at least a part of the upper surface of the lower polysilicon layer and the upper side of the p-type polysilicon region and the n-type polysilicon region of the lower polysilicon layer stacked on the upper surface of the insulating film are oppositely corresponding. An upper polysilicon layer having an n-type polysilicon region and a p-type polysilicon region alternately arranged, and an n-type polysilicon region and a p-type polysilicon region of the upper polysilicon layer and a lower polysilicon layer. It is characterized in that it is provided with a capacitor configured to have electrodes provided in the p-type polysilicon region and the n-type polysilicon region, respectively.

[0015]

In the semiconductor device configured as described above, at least one p-type polysilicon region and at least one n-type polysilicon region are alternately arranged by the polysilicon layer provided for forming an active element on the same semiconductor substrate. The arrayed lower polysilicon layer is formed by providing an insulating film on the upper surface, and the upper polysilicon layer in which p-type polysilicon regions and n-type polysilicon regions are alternately arrayed is provided on the insulating film. When forming a polysilicon diode, an insulating film is opened, the same conductivity type portions of the lower polysilicon layer and the upper polysilicon layer are made conductive, and the area of the PN junction is increased to reduce the forward resistance. The characteristics are improved with a small occupation area. On the other hand, when forming a capacitor, different conductive type portions of the lower polysilicon layer and the upper polysilicon layer are opposed to each other through an insulating film, and the polysilicon regions of the lower polysilicon layer and the upper polysilicon layer are connected to the electrode portion. The insulating film can be formed as a dielectric layer in a state of being floated from the semiconductor substrate, and stable capacitance can be obtained. Then, miniaturization of the semiconductor device can be easily realized.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment will be described with reference to FIGS. In this embodiment, a semiconductor substrate, for example, a complementary MO
Since an S transistor is formed and a polysilicon diode is formed, a description will be given of a polysilicon diode portion which is a main part thereof.

FIG. 1 is a sectional view of the first step, FIG. 2 is a sectional view of the second step, and FIG. 3 is a line A--A in FIG.
4 is a cross-sectional view taken in the direction of the arrow, FIG. 4 is a cross-sectional view of the third step, FIG. 5 is a cross-sectional view taken in the direction of arrow BB in FIG. 4, and FIG. FIG. 7 is a cross-sectional view as seen from a direction, FIG. 7 is a cross-sectional view at a fourth step, FIG. 8 is a cross-sectional view of an essential part of this embodiment, and FIG. Is.

That is, in the first step shown in FIG. 1, the semiconductor substrate 11 made of silicon (Si) is exposed to an oxidizing atmosphere at a high temperature, and an insulating layer of silicon oxide (SiO ₂ ) is formed on the semiconductor substrate 11 by thermal oxidation. 12 is formed. Further, a polysilicon having a predetermined thickness is formed on the upper surface of the formed insulating layer 12 by a known CVD method (chemical vapor deposition method), and the formed polysilicon is formed into a predetermined shape by a photolithography technique and a dry etching method. Then, the lower polysilicon layer 13 is formed.

Next, in the second step shown in FIGS. 2 and 3, boron (B) having a dose of about 1.0 to 2.0 × 10 ¹¹ cm ⁻² is formed over the entire surface of the lower polysilicon layer 13.
Then, the lower polysilicon layer 13 is made to be p-type polysilicon having a sheet resistance ρ _s of several MΩ / □ by injecting r) and further performing thermal diffusion.

In addition, p type polysilicon regions 14 and n are formed in the lower polysilicon layer 13 which is entirely made of p type polysilicon.
A dose amount of 2.0 × 10 ¹⁵ is obtained while forming masks having slit-shaped openings on the upper surface of the lower polysilicon layer 13 so that the type polysilicon regions 15 are alternately arranged parallel to the surface direction. Boron and arsenic (As) of about cm ⁻² are injected, and thermal diffusion is performed in an oxygen (O ₂ ) gas atmosphere.

As a result, a film thickness of 0.05 μm due to thermal oxidation is formed on the lower polysilicon layer 13 in which the p-type polysilicon regions 14 and the n-type polysilicon regions 15 are alternately formed.
The insulating film 16 is formed to some extent. Then, on the insulating film 16,
Openings 17 opened in a direction orthogonal to the p-type polysilicon regions 14 and the n-type polysilicon regions 15 arranged alternately.
Are formed by a photolithography technique and an etching method which have been conventionally used. In this way, the multi-layer portion 18 including the lower polysilicon layer 13 and the insulating film 16 is formed.

Subsequently, in a third step shown in FIGS. 4 to 6, a known CV is formed on the upper surface of the insulating film 16 including the opening 17.
A polysilicon having a predetermined thickness is formed by the D method, and the formed polysilicon is formed into the same shape as the lower polysilicon layer 13 by the photolithography technique and the dry etching method to form the upper polysilicon layer 19.

As in the lower polysilicon layer 13, the dose amount is 1.0 to 2.0 × 10 ¹¹ c over the entire surface.
By implanting boron of about m ⁻² and further performing thermal diffusion, the lower polysilicon layer 13 is made to be p-type polysilicon having a sheet resistance ρ _s of several MΩ / □.

Further, in the upper polysilicon layer 19 which is entirely made of p-type polysilicon, p-type polysilicon regions 20 and n are formed.
A mask having slit-shaped openings is formed on the upper surface of the upper polysilicon layer 19 so that the type polysilicon regions 21 are alternately arranged in parallel to the surface direction, as in the lower polysilicon layer 13. Meanwhile, boron and arsenic having a dose of about 2.0 × 10 ¹⁵ cm ⁻² are injected and diffused.

At this time, the opening 17 causes the p-type polysilicon region 20 and the n-type polysilicon region 21 of the upper polysilicon layer 19 to correspond to the p-type polysilicon region 14 and the n-type polysilicon region 14 of the lower polysilicon layer 13, respectively. The silicon region 15 is brought into conduction.

Then, in a fourth step shown in FIG.
An interlayer insulating film 22 is formed by stacking a silicon oxide film on the upper surfaces of the p-type polysilicon region 20 and the n-type polysilicon region 21 of the upper polysilicon layer 19 by a known CVD method.

After that, a part of the upper surfaces of the p-type polysilicon region 20 and the n-type polysilicon region 21 of the upper polysilicon layer 19 are independently exposed on the interlayer insulating film 22 by the photolithography technique and the etching method. Through hole 23 is formed. And through hole 23
After selectively growing and burying a metal layer in the aluminum, an aluminum (Al) film is further formed thereon by a sputtering method, and the formed aluminum film is patterned by a photolithography technique and RIE (reactive ion etching). Anode electrodes 24 and cathode electrodes 25 are formed alternately.

In this way, a PN junction is provided between each anode electrode 24 and cathode electrode 25, and a polysilicon diode is formed.

According to the present embodiment configured as described above,
The p-type polysilicon region 20 and the n-type polysilicon region 21 of the upper polysilicon layer 19 and the lower polysilicon layer 1
The p-type polysilicon region 14 and the n-type polysilicon region 15 of No. 3 are connected to each other in the regions corresponding to each other in the opening 17.

As a result, the p-type polysilicon regions 14, 20 are not increased in area occupied by the lower polysilicon layer 13 and the upper polysilicon layer 19 on the semiconductor substrate 11.
The area of the PN junction between the and n-type polysilicon regions 15 and 21 becomes large. And the adjacent anode electrode 2
The resistance of the polysilicon diode formed between the cathode 4 and the cathode electrode 25 in the forward direction becomes small.

Further, since the lower polysilicon layer 13 and the upper polysilicon layer 19 do not have to be particularly thick, they are the same as the gates of complementary MOS transistors (not shown) formed on the same semiconductor substrate 11. Since it can be formed of a polysilicon layer, the characteristics of the polysilicon diode can be improved while obtaining the proper characteristics of the complementary MOS transistor, and the semiconductor device can be made compact and highly integrated.

In the above-mentioned structure, the polysilicon diode is formed by stacking the insulating film 16 on the lower polysilicon layer 13 and the upper polysilicon layer 19 on the single overlying layer portion 18.
However, it is also possible to form a plurality of multi-layered portions depending on the thickness of each polysilicon layer, desired characteristics, and the like.

Next, the second embodiment will be described with reference to FIGS.
Will be described. In this embodiment, for example, a complementary MOS transistor and a capacitor are formed on a semiconductor substrate, and a capacitor portion of the main part will be described. 10 is a cross-sectional view of a main part, and FIG. 11 is a cross-sectional view taken along the line EE in FIG.

That is, in FIGS. 10 and 11, 2
Reference numeral 6 denotes a lower polysilicon layer, which is formed by stacking polysilicon on the insulating layer 12 provided on the upper surface of the semiconductor substrate 11 by a known CVD method, molding the polysilicon into a predetermined shape, and further by implanting impurities and thermal diffusion. After the whole is made of p-type polysilicon, it is formed in the same manner as in the first embodiment so that the p-type polysilicon regions 27 and the n-type polysilicon regions 28 are alternately arranged in parallel with the surface direction. .

Then, an insulating film 29 is formed on the upper surface of the lower polysilicon layer 26 by thermal oxidation when forming both polysilicon regions 27 and 28, whereby the multi-layer portion 30 is formed.
Is formed.

Further, on the insulating film 29, in the same manner as the lower polysilicon layer 26 is formed, each polysilicon is parallel to the p-type polysilicon region 27 and the n-type polysilicon region 28 of the lower polysilicon layer 26. An upper polysilicon layer 33 in which n-type polysilicon regions 31 and p-type polysilicon regions 32 of different conductivity types corresponding to the silicon regions 27 and 28 are alternately arranged is laminated. The upper polysilicon layer 31 is formed in a shape that partially overlaps with the upper portion of the lower polysilicon layer 26 with the insulating film 29 in between.

Further, the upper surfaces of the n-type polysilicon region 31 and the p-type polysilicon region 32 of the upper polysilicon layer 33 and the upper surface of the insulating film 29 on which the upper polysilicon layer 33 is not stacked are oxidized by the CVD method. An interlayer insulating film 34 formed by stacking films is formed.

Then, a part of the interlayer insulating film 34 on the upper surfaces of the n-type polysilicon region 31 and the p-type polysilicon region 32 of the upper polysilicon layer 33 is removed by the photolithography technique and the etching method, and each polysilicon region is removed. Through hole 35 in which parts of 31, 32 are independently exposed
Is formed, a part of the interlayer insulating film 34 on the upper surface of the insulating film 29 is removed together with the insulating film 29, and a part of each polysilicon region 27, 28 of the lower polysilicon layer 26 is independently exposed through hole 36. Is formed.

After that, a metal layer is selectively grown and embedded in the through holes 35 and 36, an aluminum film is further formed thereon by a sputtering method, and the formed aluminum film is formed by a photolithography technique and RIE. Pattern and alternate top polysilicon layer 33
Side electrodes 37, 38 and lower polysilicon layer 26 side electrodes 39, 40 are formed.

Thus, a capacitor is formed with the insulating film 29 sandwiched between the electrodes 37 and 38 on the upper polysilicon layer 33 side and the electrodes 39 and 40 on the lower polysilicon layer 26 side.

According to the present embodiment configured as described above, the insulating film 29 whose thickness is controlled is used as the dielectric layer, and the electrodes 37 and 38 on the upper polysilicon layer 33 side and the lower polysilicon layer 26 side. By appropriately selecting the electrodes 39 and 40 of 1, the capacitor insulated from the semiconductor substrate 11 and having a stable required capacitance can be obtained.

Further, the lower polysilicon layer 26 and the upper polysilicon layer 33 can be formed by the same polysilicon layer as the complementary MOS transistor (not shown), polysilicon diode, etc., which are formed on the same semiconductor substrate 11, and thus the semiconductor device. It is possible to realize small size and high integration.

The present invention is not limited to the above-mentioned embodiments, but can be implemented with various modifications without departing from the scope of the invention.

[0045]

As is apparent from the above description, the present invention is applicable to the case where a polysilicon layer for forming an active element is simultaneously formed on the same semiconductor substrate to form a polysilicon diode or a capacitor. In addition, a polysilicon diode having improved characteristics can be formed in a small occupied area, a capacitor having a stable electrostatic capacity that is insulated from the semiconductor substrate can be formed, and size reduction can be easily achieved.

[Brief description of drawings]

FIG. 1 is a sectional view of a first step of a first embodiment of the present invention.

FIG. 2 is a sectional view of a second step in the above embodiment.

FIG. 3 is a sectional view taken along the line AA in FIG.

FIG. 4 is a sectional view of a third step in the above embodiment.

5 is a sectional view taken along the line BB of FIG.

6 is a cross-sectional view taken along the line CC in FIG.

FIG. 7 is a cross-sectional view of a fourth step in the above embodiment.

FIG. 8 is a cross-sectional view of an essential part of the above embodiment.

9 is a cross-sectional view taken along the line DD in FIG.

FIG. 10 is a cross-sectional view of essential parts of a second embodiment of the present invention.

11 is a sectional view taken along the line EE in FIG.

FIG. 12 is a cross-sectional view of a main part of a conventional example.

FIG. 13 is a plan view of an essential part in the above.

FIG. 14 is a characteristic diagram corresponding to FIG.

15 is a plan view of relevant parts of another conventional example shown in comparison with FIG.

16 is a characteristic diagram corresponding to FIG.

[Explanation of symbols]

 11 ... Semiconductor substrate 12 ... Insulating layer 13 ... Lower polysilicon layer 14, 20 ... P-type polysilicon region 15, 21 ... N-type polysilicon region 16 ... Insulating film 17 ... Opening 18 ... Overlayer 19 ... Upper polysilicon layer

Claims (3)

[Claims] 1. An insulating layer provided on a semiconductor substrate, and at least one p-type polysilicon region and n-type polysilicon region laminated on the insulating layer are formed so as to be arranged alternately in the plane direction. And a p-type polysilicon layer of the lower polysilicon layer formed on the upper surface of the insulating film of the lower polysilicon layer and the insulating film formed on the upper surface of the lower polysilicon layer. Area and n
A semiconductor device comprising: an upper polysilicon layer having p-type polysilicon regions and n-type polysilicon regions which are alternately arranged above the type polysilicon region. 2. The insulating film of the multi-layer portion has an opening formed so as to open in a direction intersecting the arrangement direction of the p-type polysilicon region and the n-type polysilicon region, and the insulating film is formed by the opening. The p-type polysilicon region and the n-type polysilicon region of the same conductivity type corresponding to the respective polysilicon layers adjacent to each other are electrically connected to each other via the p-type polysilicon region and the n-type polysilicon region The semiconductor device according to claim 1, wherein an electrode is provided in each of the silicon regions. 3. A lower part formed so that an insulating layer provided on a semiconductor substrate and p-type polysilicon regions and n-type polysilicon regions formed on the insulating layer are alternately arranged in a plane direction. A polysilicon layer, an insulating film formed on at least a part of the upper surface of the lower polysilicon layer, the p-type polysilicon region and the n-type polysilicon of the lower polysilicon layer stacked on the upper surface of the insulating film. An upper polysilicon layer having an n-type polysilicon region and a p-type polysilicon region alternately arranged above the region, and the n-type polysilicon region and the p-type polysilicon region of the upper polysilicon layer. A capacitor having a silicon region and electrodes provided in the p-type polysilicon region and the n-type polysilicon region of the lower polysilicon layer, respectively, is provided. A semiconductor device characterized by the above.