JPH0687496B2 - Bipolar integrated circuit - Google Patents

Description

FIELD OF THE INVENTION The present invention relates to bipolar integrated circuits.

[Conventional technology]

With the recent large capacity ratio of memory integrated circuits, miniaturization of transistor cell design has been required more and more.

Emitter-coupled memory cells with a Schottky barrier diode and a resistor connected in parallel are widely used in high-speed bipolar RAM.

FIG. 3 is an equivalent circuit diagram of an example of a conventional bipolar memory cell.

In the memory cell 15, two collectors are connected in parallel to a resistor R _L and a Schottky barrier diode SBD, load cells 13 are respectively connected to the cathode side, and two first emitters are commonly connected to a constant current power supply 14. And a pair of bipolar transistors Q ₁ and Q _{2 in} a flip-flop configuration.

High potential word line W _T is a Schottky barrier diode SBD
Is commonly connected to the anode side of the pair of bit lines B and B and is tangent to the second emitters of the transistors Q ₁ and Q ₂ , respectively.

The current of the constant current source 13 flows through the Schottky barrier diode SBD connected to the collector of one of the transistors Q ₁ or Q _{2 in} the ON state.

Since the base current of the transistor in the off state flows into the load resistance R _L connected to the collector of the other transistor, for example, in the case of a 16 kilobit RAM with a power consumption of 1 W, the value of the load resistance R _L needs to be about 250 kΩ. Become.

As the load resistance _RL , conventionally, a diffusion resistance value of a silicon epitaxial single crystal film or a polycrystalline silicon film deposited on an insulating film such as a silicon oxide film is used.

[Problems to be solved by the invention]

When the polycrystalline silicon film, which is one of the conventional examples described above, is used as the load resistance _RL , there is a problem that the usable resistance value has an upper limit.

That is, the absolute value of the temperature coefficient of the load resistance R _L must be 2000 ppm / ° C or less in the circuit design, but the upper limit of the layer resistance of the polycrystalline silicon film corresponding to that is at most 10 kΩ / □.
Since it is up to, to realize the resistance value of 200 kΩ mentioned above,
The area occupied by the chip surface is 80-150 μm ^{2 with a} normal width
Therefore, the total area occupied by the two load resistors R _L is 100 to 300 μ.
The area of the memory cell 15 reaches about 20 to 40% as m ^{2 and} there is a problem that high integration cannot be achieved.

Also, when the p-type diffusion resistance layer is provided as the other diffusion resistance layer, for example, in the n-type conductive region, the upper limit of the resistance value is limited for the same reason as described above, and there is a similar problem. , A separation process for forming a diffusion resistance layer, and pn
Problems such as delay in operating speed due to junction capacitance were added.

The object of the present invention is to provide the semiconductor wafer 9 as the load resistance R _L.
The purpose of the present invention is to provide a resistor of a silicon embedded body in the opening of the above, and to provide a highly integrated bipolar integrated circuit using a load resistance R _L having a small area and a high resistance value.

[Means for solving problems]

The bipolar integrated circuit of the present invention comprises: (A) a semiconductor substrate of one conductivity type, a collector layer of the opposite conductivity type selectively formed on the semiconductor substrate, and a conductivity type of the opposite conductivity type formed on the entire surface including the collector layer. (B) a semiconductor wafer having an epitaxial layer and an oxide film selectively covering the surface of the epitaxial layer, and (B) an opening selectively formed from an upper surface of the semiconductor wafer to an intermediate depth of the collector layer, C) An insulating film provided on the side wall of the opening, (D) A resistor made of a silicon embedded body formed in the opening, (E) Platinum silicidation on a part of the exposed surface of the epitaxial layer. And a Schottky barrier diode formed by providing an object.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.
It corresponds to the load cell 13 of the equivalent circuit of FIG.

As shown in FIG. 1A, a semiconductor wafer 9 includes a p-type silicon substrate 1 and an n-type buried collector layer 2 having a thickness of about 2 μm.
An n-type epitaxial layer 3 and a silicon oxide film 4 each having a thickness of about 1.5 μm are formed in this order.

A resist layer 10 selectively formed by the photolithography technique is provided thereon, and the silicon oxide film 4, the n-type epitaxial layer 3, and the n-type buried collector layer are formed by using the resist layer 10 as a mask by the reactive ion etching method. 2 is etched to a depth of 2.5 μm so as not to penetrate to the p-type silicon substrate 1, and an opening having a surface area of about 1.0 μm ² is provided.

Next, as shown in FIG. 1B, after removing the resist layer 10 by oxygen plasma, a silicon nitride film having a thickness of about 100 nm is deposited on the entire surface, and then reactive ion etching is used. Etching is performed while leaving the silicon nitride film 5 only on the side walls.

Next, as shown in FIG. 1 (c), a polycrystalline silicon film is deposited to a thickness of about 2 μm, the surface is flattened, and etching is performed by a reactive ion etching method to form polycrystalline silicon only inside the openings. Leave as an embedded body 6.

Next, as shown in FIG. 1 (d), the n-type epitaxial layer 3 adjacent to the opening is selectively exposed using a photolithography technique, and a platinum film with a thickness of about 30 nm is formed on the entire surface. After depositing by sputtering and forming a platinum silicide at a temperature of 500 to 600 ° C., the unreacted platinum film is removed by hot aqua regia, and the Schottky junction S and the polycrystalline silicon embedded body 6 are each schottky. Two platinum silicide layers 7a and 7b are formed as electrodes and ohmic electrodes of the barrier diode SBD.

Finally, as shown in FIG. 1 (e), the electrode 8 is formed to form a load cell in which the Schottky barrier diode SBD and the load resistor R _L are connected in parallel.

Here, the value of the load resistance R _L can be set to a high resistance value of several hundred kΩ by doping phosphorus as an impurity when depositing the polycrystalline silicon film of FIG. 1 (c) to change the phosphorus concentration. .

In this embodiment, polycrystalline silicon is used as the buried member 6, but single crystal silicon may be deposited and grown instead.

FIG. 2 is a sectional view of a chip of a load cell having a high resistance value according to the second embodiment of the present invention. After forming the opening portion 11 shown in FIG. 1 (a), the bottom portion of the opening portion 11 has 5 to 10 parts.
A thin oxide film 12 having a thickness of about nm is formed, and then a high resistance polycrystalline silicon burying body 6 which is not doped with impurities is provided.

In this way, if the thin oxide film 12 is also provided on the bottom surface of the opening,
Even if a high-temperature heat treatment is performed for a long time in the subsequent manufacturing process, it is possible to obtain an effect that the resistance value is not lowered by the diffusion of impurities from the n-type collector layer and the resistance value is not varied.

The value of the load resistance R _L is a high resistance value in series of a number MΩ determined by the leakage current of the tunnel phenomenon passing through the thin oxide film 2 and a resistance value MΩ of the polycrystalline silicon embedded body 6.

〔The invention's effect〕

As described above, the bipolar integrated circuit of the present invention,
The area occupied by the load resistance is about 2 μm ² per cell,
By setting it to 1% or less of the conventional value, there is an effect that a high degree of integration can be obtained and, at the same time, a load resistance having a high resistance value which cannot be conventionally obtained can be easily obtained.

[Brief description of drawings]

1A to 1E are sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIG. 2 is a sectional view of the second embodiment of the present invention. FIG. 3 is an equivalent circuit diagram of an example of a conventional bipolar memory cell. 1 ... p-type silicon substrate, 2 ... n-type buried collector layer, 3 ...
n-type epitaxial layer, 4 ... Silicon oxide film, 5 ... Silicon nitride film, 6 ... Polycrystalline silicon buried body, 7a, 7b ... Platinum silicide, 8 ... Electrode, 9 ... Semiconductor wafer, 10 ... Resist film, 11 ... opening, 12 ... thin oxide film, 13 ... load cell, 14 ... constant current power supply, 15 ... memory cells, Q _1, Q ₂ ... bipolar transistor, R _L ... load resistor, S ... Schottky junction, SBD ...
Schottky barrier diode, W _B, W _T ... word line.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a collector layer of opposite conductivity type selectively formed on the semiconductor substrate, and an epitaxial layer of opposite conductivity type formed on the entire surface including the collector layer. And (B) a semiconductor wafer having an oxide film selectively covering the surface of the epitaxial layer, (B) an opening selectively formed from the upper surface of the semiconductor wafer to an intermediate depth of the collector layer, (C) the An insulating film provided on the side wall of the opening, (D) A resistor made of a silicon embedded body formed in the opening, (E) Providing platinum silicide on a part of the exposed surface of the epitaxial layer. A Schottky via diode formed by the above, and a bipolar integrated circuit.