JPS5982760A - Complementary semiconductor integrated circuit device - Google Patents

Complementary semiconductor integrated circuit device

Info

Publication number
JPS5982760A
JPS5982760A JP57193198A JP19319882A JPS5982760A JP S5982760 A JPS5982760 A JP S5982760A JP 57193198 A JP57193198 A JP 57193198A JP 19319882 A JP19319882 A JP 19319882A JP S5982760 A JPS5982760 A JP S5982760A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
layer
type
wiring layer
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57193198A
Other languages
Japanese (ja)
Inventor
Koji Eguchi
江口　宏次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57193198A priority Critical patent/JPS5982760A/en
Publication of JPS5982760A publication Critical patent/JPS5982760A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enable to attain integration in high density of a complementary semiconductor integrated circuit device by a method wherein diffusion layers containing mutually reversely conductive type impurities are wired using polycrystalline silicon, and the same conductive type impurities with both the diffusion layers respectively are made to be contained in the polycrystalline silicon wiring layer on both the diffusion layers. CONSTITUTION:A P type diffusion layer 22 is formed on an N type silicon substrate 21, an N type diffusion layer 24 is formed on a P type buried layer 23, openings for electrodes are formed on the layers 22, 24 according to the photoetching method, a non doped polycrystalline silicon layer is left as the desired polycrystalline silicon wiring layer 25, and another part is etched to be removed. Boron ions are implanted in high concentration according to the ion implantation method in the polycrystalline silicon wiring layer containing the contact region between the layers 22, 25, and phosphorus ions are implanted in high concentration in the polycrystalline silicon wiring layer containing the contact region between the layers 24, 25 to attain ohmic contacts respectively. After then, a high melting point metal layer 27 is formed according to the vacuum evaporation method, and finally, the unnecessary parts are etched to be removed according to the photoetching method to form the high melting point metal layer on the polycrystalline silicon wiring layer 26 containing P type impurities and N type impurities.

Description

【発明の詳細な説明】 本発明は相補型半導体集積回路装置に係シ、特にＰ型拡
散層とＮ型拡散層との電気的接続方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary semiconductor integrated circuit device, and particularly to a method for electrically connecting a P-type diffusion layer and an N-type diffusion layer.

Ｐ型拡散層とＮ型拡散層とを同−基体上に形成した相補
型半導体構造において、その両拡散層間を電気的に接続
する方法としては、従来から金属配線層としてアルミニ
ウムが使用されていた。しかし、近年における高密度集
積化や電気的特性の向上を目的に各種配線パターンの微
細化やウェハー製造工程における拡散層のシャロー化が
進んでくると拡散層中へのアルミ浸透が発生してくる。In a complementary semiconductor structure in which a P-type diffusion layer and an N-type diffusion layer are formed on the same substrate, aluminum has traditionally been used as a metal wiring layer to electrically connect the two diffusion layers. . However, in recent years, as various wiring patterns have become finer and diffusion layers have become shallower in the wafer manufacturing process for the purpose of high-density integration and improved electrical characteristics, aluminum has become infiltrated into the diffusion layers. .

この解決法としてはアルミニウム配線層にかわってコン
タクトすべき拡散層と同一導電型の不純物を含んだ多結
晶シリコンを用いる方法がある。即ち、第１図に示すよ
うにＰ型拡散層１１　とはＰ型不純物を含む多結晶シリ
コン１２とＮ型拡散層１３とはＮ型不純物を含む多結晶
シリコン１４とでそれぞれオーミックなコンタクトをと
っている。One solution to this problem is to use polycrystalline silicon containing impurities of the same conductivity type as the diffusion layer to be contacted, instead of the aluminum wiring layer. That is, as shown in FIG. 1, the P-type diffusion layer 11 is in ohmic contact with the polycrystalline silicon 12 containing P-type impurities, and the N-type diffusion layer 13 is in ohmic contact with the polycrystalline silicon 14 containing N-type impurities. ing.

しかし多結晶シリコンにおけるＰ型不純物とＮ型不純物
との境界線１５上では、前記Ｐ型多結晶シリコン１２と
Ｎ型多結晶シリコン１４　との電気的導通を得るためア
ルミニウム１６で更ニオーミックなコンタクトをとる必
要が生じてくる。従って、多結晶シリコンの使用はアル
ミ浸透の防止は可能であるが、主配線層としてアルミニ
ウム配線が使用されている現在では、高密度集積化には
寄与しなかった。However, on the boundary line 15 between the P-type impurity and the N-type impurity in polycrystalline silicon, a further niohmic contact is made with aluminum 16 in order to obtain electrical continuity between the P-type polycrystalline silicon 12 and the N-type polycrystalline silicon 14. There will be a need to take it. Therefore, although the use of polycrystalline silicon can prevent aluminum penetration, it does not contribute to high-density integration, as aluminum wiring is currently used as the main wiring layer.

本発明では上記したアルミ浸透を々くし更に高密度集積
化を可能にした構造を提供するものである。The present invention provides a structure that reduces the above-mentioned aluminum penetration and enables higher density integration.

本発明によれば、−導電型不純物を含む拡散層と、これ
とは反対導電型の不純物を含む拡散層を多結晶シリコン
で配線し、前記両波散層と同一導電型の不純物を少なく
とも前記両波散層上の前記多結晶シリコン中に含み更に
前記多結晶シリコン上には、リフ２クタリメタル（高融
点金属物質）又は、シリサイドを形成して成る相補型半
導体集積回路装置が得られる。According to the present invention, a diffusion layer containing an impurity of a -conductivity type and a diffusion layer containing an impurity of an opposite conductivity type are interconnected with polycrystalline silicon, and the impurity of the same conductivity type as both of the diffusion layers is connected to at least the diffusion layer. A complementary semiconductor integrated circuit device is obtained in which a reflux metal (high melting point metal material) or silicide is formed on the polycrystalline silicon and is contained in the polycrystalline silicon on both diffusion layers.

次に、図を用いて本発明の詳細な説明する。Next, the present invention will be explained in detail using figures.

第２図には、Ｎ型シリコン基体２１上にＰ型拡散層２２
Ｐ型埋込み層２３上にＮ型拡散層２４　とを形成し、前
記Ｐ型拡散層２２、Ｎ型拡散層２４上には電極用開孔を
写真蝕刻法でこのノンドープ多結晶シリコンを所望の多
結晶シリコン配線層２５として残し、他の部分をエツチ
ング除去した図を示す。次にＰ型拡散層２２と多結晶シ
リコン配線層２５とのコンタクト領域を含む多結晶シリ
コン配線層中には、イオン注入法によシ高濃度のボロン
を注入しオーミックコンタクトをとる。又、Ｎ型拡散層
２４と多結晶シリコン配線層２５とのコンタクト領域を
含む多結晶シリコン配線層中には同様な方法で高濃度の
リンを注入してオーミックコンタクトをとる。その後モ
リブデンやタングステン等のようなりフラクタリメタル
（高融点金層物質）を真空蒸着法で形成し、最後に写真
蝕刻法によシエッチング除去してＰ型不純物とＮ型不純
物を含んだ多結晶シリコン配線層２６上に形成し、第３
図に示すように完成する。FIG. 2 shows a P-type diffusion layer 22 on an N-type silicon substrate 21.
An N-type diffusion layer 24 is formed on the P-type buried layer 23, and openings for electrodes are formed on the P-type diffusion layer 22 and the N-type diffusion layer 24 by photolithography to form a desired polycrystalline silicon layer. The figure is shown in which a crystalline silicon wiring layer 25 is left and other parts are etched away. Next, high concentration boron is implanted into the polycrystalline silicon wiring layer including the contact region between the P-type diffusion layer 22 and the polycrystalline silicon wiring layer 25 by ion implantation to establish ohmic contact. Further, high concentration phosphorus is implanted in the same manner into the polycrystalline silicon wiring layer including the contact region between the N type diffusion layer 24 and the polycrystalline silicon wiring layer 25 to establish ohmic contact. After that, a fractary metal (high melting point gold layer material) such as molybdenum or tungsten is formed by vacuum evaporation, and finally removed by photoetching to form a polycrystalline material containing P-type impurities and N-type impurities. Formed on the silicon wiring layer 26, the third
Complete as shown in the figure.

このように、Ｎ型不純物とＰ型不純物とがそれぞれに分
かれて存在する多結晶シリコン配線層上にリフラクタリ
メタルを形成することによって上記多結晶シリコン配線
層内で形成されるＰＮジャンクションを破壊し、電気的
に導通状態にするばかシでなく低抵抗配線層へと導くも
のである。更に、主配線としてのアルミ配線層が第２の
配線層として使用出来、高密度集積化に寄与するもので
ある。尚、本実施例ではりフラクタリメタルを使用した
場合を説明したがシリサイドを用いても良い。In this way, by forming a refractory metal on a polycrystalline silicon wiring layer in which N-type impurities and P-type impurities exist separately, the PN junction formed in the polycrystalline silicon wiring layer can be destroyed. This leads to a low-resistance wiring layer rather than making it electrically conductive. Furthermore, the aluminum wiring layer as the main wiring can be used as the second wiring layer, contributing to high-density integration. In this embodiment, a case where a fractary metal is used has been described, but a silicide may also be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の多結晶シリコン層を配線に使った相補型
半導体装置の断面図であシ第２図と第３図は本発明の実
施例の断面図を示す。 図中、１１，２２・・・・・・Ｐ型拡散層、１２・・・
・・・Ｐ型不純物を含んだ多結晶シリコン、１３．２４
・・・・・・Ｎ型拡散層、１４・・・・・・Ｎ型不純物
を含んだ多結晶シリコン、１５・・・・・・Ｐ型不純物
とＮ型不純物との境界線、１６・・・・・・アルミニウ
ム配線層、２１・・・・・・Ｎ型シリコン基体、２３・
・・・・・Ｐ型埋込み層、２５・・・・・・ノンドープ
の多結晶シリコン、２６・・・・・・　Ｐ型及びＮ型不
純物を含んだ多結晶シリコン、２７・・・・・・　リフ
ラクタリメタル。 ３ 力／［Ｄ 第２国 、ｖ５３閉FIG. 1 is a sectional view of a complementary semiconductor device using a conventional polycrystalline silicon layer for wiring, and FIGS. 2 and 3 are sectional views of an embodiment of the present invention. In the figure, 11, 22...P-type diffusion layer, 12...
...Polycrystalline silicon containing P-type impurities, 13.24
......N-type diffusion layer, 14...Polycrystalline silicon containing N-type impurity, 15...Boundary line between P-type impurity and N-type impurity, 16... ...Aluminum wiring layer, 21...N-type silicon substrate, 23.
...P-type buried layer, 25...Non-doped polycrystalline silicon, 26...Polycrystalline silicon containing P-type and N-type impurities, 27... refractory metal. 3 Power/[D 2nd country, v53 closed

Claims (1)

【特許請求の範囲】[Claims] 一導電型不純物を含む拡散層と、これとは反対導電型の
不純物を含む拡散層を電気的に結ぶ配線として多結晶シ
リコンを使用し前記両波散層と同一導電型の不純物を少
なくとも前記内拡散層上の前記多結晶シリコン中に含み
更に前記多結晶シリコン°上にはりフラクタリメタル又
は、シリサイドを形成して成る相補型半導体集積回路装
置。Polycrystalline silicon is used as a wiring that electrically connects a diffusion layer containing an impurity of one conductivity type and a diffusion layer containing an impurity of the opposite conductivity type, and impurities of the same conductivity type as those of both diffusion layers are used as wiring. 1. A complementary semiconductor integrated circuit device comprising a fractary metal or silicide contained in the polycrystalline silicon on the diffusion layer and further formed on the polycrystalline silicon.
JP57193198A 1982-11-02 1982-11-02 Complementary semiconductor integrated circuit device Pending JPS5982760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57193198A JPS5982760A (en) 1982-11-02 1982-11-02 Complementary semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57193198A JPS5982760A (en) 1982-11-02 1982-11-02 Complementary semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5982760A true JPS5982760A (en) 1984-05-12

Family

ID=16303930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57193198A Pending JPS5982760A (en) 1982-11-02 1982-11-02 Complementary semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5982760A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61210662A (en) * 1985-01-22 1986-09-18 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン Semiconductor structural body
JPS6218064A (en) * 1985-07-05 1987-01-27 シ−メンス、アクチエンゲゼルシヤフト Making of cross connection for static write/read memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61210662A (en) * 1985-01-22 1986-09-18 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン Semiconductor structural body
JPS6218064A (en) * 1985-07-05 1987-01-27 シ−メンス、アクチエンゲゼルシヤフト Making of cross connection for static write/read memory

Similar Documents

Publication Publication Date Title
JP2697812B2 (en) Semiconductor memory device and method of manufacturing the same
US4543595A (en) Bipolar memory cell
JPH0343778B2 (en)
JPH0644603B2 (en) Semiconductor device and its manufacturing method
JPS5811107B2 (en) Programmable memory cell with semiconductor diode
JPS622708B2 (en)
EP0078220B1 (en) Polycrystalline silicon interconnections for bipolar transistor flip-flop
JPH05102439A (en) Semiconductor device
EP0030147A1 (en) Method for manufacturing a semiconductor integrated circuit
JP2605030B2 (en) Quadrature bipolar transistor
US4883772A (en) Process for making a self-aligned silicide shunt
JPS5982760A (en) Complementary semiconductor integrated circuit device
JPS5978576A (en) Semiconductor device and manufacture thereof
US4624863A (en) Method of fabricating Schottky diodes and electrical interconnections in semiconductor structures
JPS5818784B2 (en) Hand-crafted construction work
EP0264309B1 (en) Self-aligned base shunt for transistor
JP2876716B2 (en) Semiconductor device
JPS5838939B2 (en) integrated circuit
JPH0554263B2 (en)
JP2654056B2 (en) Method for manufacturing semiconductor device
JPS6158981B2 (en)
JPH0282639A (en) Semiconductor device and manufacture thereof
KR100325469B1 (en) Method for forming contact part for metallization in semiconductor device and structure thereof
JPS6161548B2 (en)
KR100206579B1 (en) Semiconductor device and manufacture thereof