JPS5484980A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5484980A
JPS5484980A JP15318377A JP15318377A JPS5484980A JP S5484980 A JPS5484980 A JP S5484980A JP 15318377 A JP15318377 A JP 15318377A JP 15318377 A JP15318377 A JP 15318377A JP S5484980 A JPS5484980 A JP S5484980A
Authority
JP
Japan
Prior art keywords
layer
substrate
type
film
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15318377A
Other languages
Japanese (ja)
Inventor
Yasuo Matsukura
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15318377A priority Critical patent/JPS5484980A/en
Publication of JPS5484980A publication Critical patent/JPS5484980A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE: To produce a high-speed MOS device by providing a N-type poly-Si layer on an insulating film provided selectively on a Si substrate and providing a gate electrode through a P-type Si layer and a gate film on the substrate.
CONSTITUTION: Layer 103 is selectively formed around the center of SiO2 film 102 in a concentric ring shape on the surface of P+-type Si substrate 101, and poly-Si layers 104 and 105 are formed on the upper face and are made into a N+-type layer by phosphorus diffusion. P-type Si layer 106 is provided on the substrate between films 102 and 103. SiO2 gate film 107 and poly-Si gate electrode 108 are laminated on layer 106. Al drain electrode 110 and source electrode 111 extending onto SiO2 film 109 are led out from layers 104 and 105, and wiring 112 is formed from the gate electrode. Substrate 101 is provided with electrode 113. In this constitution, there is SiO2 at the bottom of the source and the drain, and the junction capacity is considerably reduced. Since a conduction inversion layer is formed on the surface of a Si single crystal layer, operation characteristic is superior to perform a stable FET operation.
COPYRIGHT: (C)1979,JPO&Japio
JP15318377A 1977-12-19 1977-12-19 Semiconductor device Pending JPS5484980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15318377A JPS5484980A (en) 1977-12-19 1977-12-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15318377A JPS5484980A (en) 1977-12-19 1977-12-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5484980A true JPS5484980A (en) 1979-07-06

Family

ID=15556849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15318377A Pending JPS5484980A (en) 1977-12-19 1977-12-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5484980A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831574A (en) * 1981-08-19 1983-02-24 Toshiba Corp Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831574A (en) * 1981-08-19 1983-02-24 Toshiba Corp Semiconductor device and manufacture thereof

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