JPS5522881A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5522881A
JPS5522881A JP10576578A JP10576578A JPS5522881A JP S5522881 A JPS5522881 A JP S5522881A JP 10576578 A JP10576578 A JP 10576578A JP 10576578 A JP10576578 A JP 10576578A JP S5522881 A JPS5522881 A JP S5522881A
Authority
JP
Japan
Prior art keywords
layer
film
electrode
laminated
successively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10576578A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP10576578A priority Critical patent/JPS5522881A/en
Publication of JPS5522881A publication Critical patent/JPS5522881A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To form the lower side electrode of a static capacity by providing an n-type Si layer through an insulation film on an Si substrate and the upper side electrode by laminating a p-type Si layer through the insulation layer film. CONSTITUTION:A field oxidization film is formed to be buried on a p-type Si substrate and an n<+>Si layer is laminated to be covered with Pt. An n<+>Si made electrode or leads 4 and 5 is formed on the buried layer by a selective etching. Successively, an SiO26, Si3N47 and SiO28 are laminated to prevent a charge transfer between the Si3N4 and gate film. Successively, an Si layer 9 and an Mo layer 10 are laminated to form a static capacity 19 and gate electrode 15, and a diffusion is provided from an opening to form n<+>layers 13 and 14. Successively, an SiO216 is covered and an opening is selectively provided to attach an Al electrode 18 thereto. According to such a method, a MISFET and static capacity are formed on the same substrate. Therefore, the function of a device can be deversified.
JP10576578A 1978-08-30 1978-08-30 Manufacturing method of semiconductor device Pending JPS5522881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10576578A JPS5522881A (en) 1978-08-30 1978-08-30 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10576578A JPS5522881A (en) 1978-08-30 1978-08-30 Manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3062571A Division JPS5624385B1 (en) 1971-05-07 1971-05-07

Publications (1)

Publication Number Publication Date
JPS5522881A true JPS5522881A (en) 1980-02-18

Family

ID=14416277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10576578A Pending JPS5522881A (en) 1978-08-30 1978-08-30 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5522881A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432006A (en) * 1979-08-30 1984-02-14 Fujitsu Limited Semiconductor memory device
US4735915A (en) * 1983-07-05 1988-04-05 Oki Electric Industry Co., Ltd. Method of manufacturing a semiconductor random access memory element
US4949154A (en) * 1983-02-23 1990-08-14 Texas Instruments, Incorporated Thin dielectrics over polysilicon
USRE34535E (en) * 1983-02-23 1994-02-08 Texas Instruments Incorporated Floating gate memory with improved dielectric

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3519901A (en) * 1968-01-29 1970-07-07 Texas Instruments Inc Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3519901A (en) * 1968-01-29 1970-07-07 Texas Instruments Inc Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432006A (en) * 1979-08-30 1984-02-14 Fujitsu Limited Semiconductor memory device
US4949154A (en) * 1983-02-23 1990-08-14 Texas Instruments, Incorporated Thin dielectrics over polysilicon
USRE34535E (en) * 1983-02-23 1994-02-08 Texas Instruments Incorporated Floating gate memory with improved dielectric
US4735915A (en) * 1983-07-05 1988-04-05 Oki Electric Industry Co., Ltd. Method of manufacturing a semiconductor random access memory element

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