JPH11317518A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain electrons generated in a depletion layer from being accelerated by an electric field in the depletion layer so as not to be trapped on the surface or inside of a gate insulating film, by a method wherein second conductivity-type impurities contained in a second conductivity-type second buried layer are set lower in concentration than those contained in a first buried layer. SOLUTION: A semiconductor device is possessed of a field effect transistor equipped with a thick gate insulating film 25a as a high withstand voltage transistor, wherein buried layers 12 and 14 are formed below a P-type well 17 possessed of the channel forming region of the transistor, the upper buried layer 14 is lower in impurity concentration than the lower buried layer 12, so that an electric field generated in a depletion layer is relaxed when a potential is applied to a back gate and a gate electrode, electrons generated in the depletion layer are restrained from being accelerated by an electric field in the depletion layer do as not to be trapped on the surface or inside of the gate insulating film 25a, and a transistor can be restrained from shifting in characteristics such as a threshold value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a field effect transistor having a high driving voltage and high withstand voltage characteristics and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, flat panel displays (F)
The flat panel display (PD) market is rapidly expanding, and the plasma display panel (PDP) using a new method that uses plasma is expected to be the next-generation display that will replace the cathode ray tube (CRT; cathode ray tube). Have been.

Under the above circumstances, in the semiconductor field,
There is a need for a high-breakdown-voltage transistor that can be mounted on a high-breakdown-voltage driver used in the above-described plasma display panel and driven by applying a high voltage of several hundred volts for controlling plasma.

FIG. 9 is a cross-sectional view of a conventional semiconductor device having an n-channel MOS field-effect transistor as a conventional example of the high breakdown voltage transistor. For example, an n-type epitaxial layer 1 is formed on a p-type silicon semiconductor substrate 10.
1 and 15 are laminated, and a p-type buried layer 12 is formed from the lower n-type epitaxial layer 11 to the lower p-type silicon semiconductor substrate 10 and the upper n-type epitaxial layer 15. I have. A p-type well 17 is formed in the n-type epitaxial layer 15 in the upper part of the p-type buried layer 12, and serves as a channel formation region of the transistor. A gate insulating film 25a of silicon oxide having a thickness of, for example, 100 to 200 nm is formed in an upper layer of the p-type well 17, and a polysilicon containing an impurity in the upper layer and having a sheet resistance of about 10 to 40 Ω / □ is provided. Gate electrode 30a is formed. An n-type well 16 is formed in the n-type epitaxial layer 15 on both sides of the gate electrode 30a, and an n ⁺ -type source / drain diffusion layer 18 is formed in the vicinity of the surface. The n-channel MOS field-effect transistor is configured as described above, and the gate insulating film is formed to be much thicker than a normal low-voltage driving transistor in order to obtain a high withstand voltage characteristic.

In the above-described semiconductor device, the p-type buried layer 12a for element isolation, the p-type well 17a for element isolation, and the surface of the n-type epitaxial layer 15 formed in the n-type epitaxial layers 11 and 15, for example, L
Element isolation is performed by an element isolation insulating film 24 formed by the OCOS method. On both sides of the gate electrode 30a, a silicon oxide sidewall insulating film 26 is formed, and further, for example, a silicon oxide-based first insulating film 28 and a second insulating film 29 are formed on the entire surface to cover the transistor. Have been. In the first insulating film 28 and the second insulating film 29, a contact hole reaching the source / drain diffusion layer 18 is opened, and made of, for example, aluminum or the like, and an electrode 31 connected to the source / drain diffusion layer 18 is formed. I have.

A method for manufacturing the above semiconductor device will be described. First, as shown in FIG. 10A, an n-type epitaxial layer 11 containing an n-type impurity at a low concentration is formed on a p-type silicon semiconductor substrate 10 to a thickness of about 5 μm by an epitaxial growth method. Next, the silicon oxide layer 20 is formed to a thickness of about 100 nm by, for example, a thermal oxidation method. Next, a p-type buried layer serving as a back gate of the transistor and a resist film R1 opening an area for forming a p-type buried layer for element isolation by a photolithography process
Is formed, and using the resist film R1 as a mask, for example, a p-type impurity D such as boron (B) is formed by an existing ion implantation method.
1 is introduced at a dose of 1 × 10 ¹³ atoms / cm ² . In the drawing, a region into which a p-type impurity has been introduced is indicated by “+”.

Next, as shown in FIG. 10B, the resist film R1 is peeled off with, for example, a sulfated water (a mixed solution of sulfuric acid and hydrogen peroxide solution), and a heat treatment is performed at, for example, 1200 ° C. for 200 minutes. Then, the p-type impurity introduced above is diffused and activated to form a p-type buried layer 12 serving as a back gate of the transistor and a p-type buried layer 12a for element isolation.

Next, as shown in FIG. 11C, the silicon oxide layer 20 is removed by etching such as RIE (reactive ion etching), and then the n-type epitaxial layer 11 is removed in the same manner as described above. An n-type epitaxial layer 15 containing an n-type impurity at a low concentration is formed in a thickness of about 5 μm on the upper layer by an epitaxial growth method. Here, the p-type buried layer 12 and the p-type buried layer 1 for element isolation are used.
The p-type impurity in 2a is the upper n-type epitaxial layer 15
To form a diffusion layer having the shape shown in the drawing.

Next, as shown in FIG. 11D, a silicon oxide layer 22 having a thickness of about 100 nm is formed on the surface of the n-type epitaxial layer 15 by, for example, a thermal oxidation method. Next, a resist film R3 opening a region for forming an n-type well serving as a source / drain region of a transistor is formed by a photolithography process, and using the resist film R3 as a mask, for example, phosphorus (P) or the like is formed by an existing ion implantation method. 360 keV, 1 × 10 ¹³ atoms /
Introduce at a dose of cm ² . In the drawing, a region into which an n-type impurity has been introduced is indicated by "-".

Next, as shown in FIG. 12E, the resist film R3 is peeled off, and a p-type well for forming a transistor channel and a p-type well for element isolation are opened by a photolithography step. A resist film R4 to be formed, and using the resist film R4 as a mask,
For example, p of boron (B) or the like by the existing ion implantation method
A type impurity D4 is introduced at 360 keV and at a dose of 1 × 10 ¹³ atoms / cm ² . In the drawing, a region into which a p-type impurity has been introduced is indicated by “+”.

Next, as shown in FIG. 12 (f), the resist film R4 is peeled off and, for example, CVD (Chemical Vapor Dep.
silicon nitride (Si ₃ N ₄ ) by the osition method.
A silicon nitride layer 23 serving as a mask for forming an element isolation insulating film by a LOCOS method in a later step is formed. Next, for example, at 1200 ° C., 2
By performing a heat treatment under the condition of 00 minutes to diffuse and activate the p-type impurity and the n-type impurity introduced above, the n-type well 16 serving as a source / drain region, the p-type well 17 serving as a channel forming region, and the element isolation For p
Form the mold wells 17a.

Next, as shown in FIG. 13 (g), a resist film (not shown) is formed on the silicon nitride layer 23 by photolithography to open a region where an element isolation insulating film is to be formed by a LOCOS method. And RIE
The silicon nitride layer 23 is subjected to patterning by performing dry etching such as, for example, to form a silicon nitride layer 23a covering a region excluding a region where an element isolation insulating film is to be formed. After that, the resist film is peeled off.

Next, as shown in FIG. 13 (h), thermal oxidation is performed using the silicon nitride layer 23a as a mask.
A LOCOS element isolation insulating film 24 having a thickness of 00 nm is formed. Next, the silicon nitride layer 23a is removed by, for example, hot phosphoric acid wet etching, and further, for example, by steam oxidation at 900 to 1000 ° C. to 100 to 20 ° C.
The surface is oxidized to have a thickness of 0 nm to form a silicon oxide layer 25 serving as a gate insulating film of the high-breakdown-voltage transistor. Next, a resist film R5 that opens a region of the p-type well 17 is formed by a photolithography process, and using the resist film R5 as a mask, a p-type impurity D5 such as boron (B) is applied at 60 keV, 1 by an existing ion implantation method.
It is introduced at a dose of × 10 ¹² atoms / cm ² to adjust the threshold value of the transistor.

Next, as shown in FIG. 14I, the resist film R5 is peeled off, and a resist film (not shown) for protecting a gate electrode formation region is formed on the silicon oxide layer 25 by photolithography to form a pattern. Then, for example, a hydrofluoric acid-based wet etching is performed to
Is patterned to form a gate insulating film 25a of silicon oxide.
To form After that, the resist film is peeled off.

Next, as shown in FIG. 14 (j), polysilicon having a high impurity concentration and a sheet resistance of about 10 to 40 Ω / □ is entirely formed on the gate insulating film 25a by, eg, CVD. And a gate electrode layer 30
To form Next, a resist film R6 for protecting a gate electrode formation region is formed in a pattern on the gate electrode layer 30 by a photolithography process.

Next, as shown in FIG. 15 (k), etching such as RIE is performed using the resist film R6 as a mask to pattern the gate electrode 30a. Next, silicon oxide is deposited to a thickness of 300 nm by, for example, a CVD method, and is etched back by etching such as RIE to form a gate insulating film 25a and a gate electrode 30a.
The silicon oxide deposited as described above is removed except for the side wall portion, and a side wall insulating film 26 is formed.

Next, as shown in FIG. 15 (l), for example, C is formed from TEOS (tetraethylorthosilicate) as a raw material.
Silicon oxide layer 27 having a thickness of about 20 nm by VD method
Then, an n-type impurity D6 such as arsenic (As) is applied at 70 keV and 1 × 10
^The source / drain diffusion layer 18 is formed by passing through the silicon oxide layer 27 at a dose of ^{13 to} 5 × 10 ¹⁵ atoms / cm ² and introducing the same.

Next, silicon oxide is deposited to a thickness of about 150 nm by, for example, a CVD method to form a first insulating film 28, and then BPSG (silicon oxide containing boron and phosphorus) is deposited to a thickness of 500 nm by, for example, a CVD method. Then, the second insulating film 29 is formed by flattening by reflow, etch back, or the like. Next, the first insulating film 28
Then, a resist film for opening the source / drain diffusion layer region is formed on the upper layer of the second insulating film 29, and a contact hole reaching the source / drain diffusion layer 18 is opened by etching such as RIE. An electrode 31 connected to the source / drain diffusion layer 18 is formed by forming an aluminum layer on the entire surface by covering the above contact hole by sputtering and patterning the aluminum layer. Thus, the semiconductor device illustrated in FIG. 9 is obtained. In FIG. 9, illustration of the silicon oxide layer 27 is omitted.
In the subsequent steps, an upper wiring, a surface protection film, and the like are formed by, for example, a CVD method to obtain a desired semiconductor device.

[0019]

However, in the above-mentioned conventional semiconductor device, the following problems occur when, for example, the threshold of a high breakdown voltage transistor is measured by a circuit as shown in FIG. FIG.
In (b), a negative potential is applied to the back gate BG of the high breakdown voltage transistor Tr, and a positive potential is applied to the gate electrode G. When the potential applied to the gate electrode is equal to or higher than the threshold value (Vth) of the transistor, an inversion layer is formed in the surface layer portion of the channel formation region of the transistor, and a current flows between the source and drain diffusion layers as a channel. .

FIG. 16A shows a state in which a potential equal to or higher than the threshold value of the transistor is applied to the gate electrode as described above, and an inversion layer IL is formed on the surface of the p-type well 17 (channel formation region). I have. The inversion layer IL can be regarded as an n-type since a large number of electrons are present, and this n-type region spreads so as to be connected to the n-type source / drain diffusion layer 18 so that the source / drain diffusion layer 18
A current can be passed between them. In this case, by applying a potential to the back gate and the gate electrode, the depletion layer spreads to a region V sandwiched by a dotted line in FIG. The potential applied to the back gate is mainly applied to the depletion layer V,
Here, electrons are generated. At this time, the generated electrons are accelerated by the electric field in the depletion layer, and are captured on the surface of the gate insulating film 25a or injected into the gate insulating film 25a. When electrons are trapped on the surface or inside of the gate insulating film 25a in this manner, an electric field is generated by the trapped electrons, so that the threshold value of the transistor shifts and the transistor characteristics fluctuate.

The present invention has been made in view of the above-mentioned problems, and accordingly, the present invention provides that the electrons generated in the depletion layer when a potential is applied to the back gate and the gate electrode are accelerated by the electric field in the depletion layer. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which suppress the trapping of the gate insulating film on the surface or inside of the gate insulating film and suppress the fluctuation of the transistor characteristics such as the shift of the threshold value of the transistor.

[0022]

In order to achieve the above object, a semiconductor device of the present invention comprises a first conductive type semiconductor layer formed on a substrate and a channel formed on the first conductive type semiconductor layer. A second conductivity type semiconductor layer including a region, a gate insulating film formed above the channel forming region, a gate electrode formed above the gate insulating film, and the channel formation on both sides of the gate electrode. A first conductive type semiconductor layer formed in the first conductive type semiconductor layer so as to connect to the region;
A conductive type source / drain region, a first buried layer of a second conductive type formed in the first conductive type semiconductor layer spaced downward from the second conductive type semiconductor layer; Connecting the semiconductor layer and the first buried layer to form the first buried layer;
A second buried layer of a second conductivity type formed in the conductivity type semiconductor layer and containing a second conductivity type impurity at a lower concentration than the first buried layer.

In the above-described semiconductor device of the present invention, a field-effect transistor formed in a first conductivity type semiconductor layer on a substrate has a transistor channel formation region,
A second conductivity type semiconductor layer such as a well formed in the conductivity type semiconductor layer and a second conductivity type buried layer formed in the first conductivity type semiconductor layer below the second conductivity type semiconductor layer are formed. The buried layer functions as a back gate of the transistor. Here, the buried layer is
Lower part (the side opposite to the side connected to the second conductivity type semiconductor layer:
The impurity concentration is set lower in the upper portion (the side connected to the second conductivity type semiconductor layer: the second buried layer) than in the first buried layer.

When the above-described semiconductor device is applied to, for example, a high-breakdown-voltage transistor having a gate insulating film formed in a thick film, the second device having a channel forming region of the transistor may be used.
In the buried layer formed below the conductive semiconductor layer, the upper portion has a lower impurity concentration than the lower portion, so that the electric field in the depletion layer when a potential is applied to the back gate and the gate electrode is reduced. This makes it possible to suppress electrons generated in the depletion layer from being accelerated by the electric field in the depletion layer and trapped on the surface or inside of the gate insulating film, thereby making it possible to suppress transistor characteristics such as a shift in transistor threshold voltage. Can be suppressed.

The above semiconductor device of the present invention is preferably
The concentration of the impurity of the second conductivity type in the second buried layer is:
The concentration is lower than the concentration of the second conductivity type impurity in the second conductivity type semiconductor layer. In the second conductivity type semiconductor layer, an impurity concentration necessary for obtaining a predetermined threshold value of the transistor is secured as a channel formation region, and the electric field in the depletion layer when a potential is applied to the back gate and the gate electrode by the above structure And variations in transistor characteristics such as a shift in the threshold value of the transistor can be suppressed.

The above semiconductor device of the present invention is preferably
The first conductivity type semiconductor layer includes a first semiconductor layer formed on the substrate, a second semiconductor layer formed on the first semiconductor layer, and a third semiconductor layer formed on the second semiconductor layer. A semiconductor layer, wherein the first buried layer is formed in the first semiconductor layer, the second buried layer is formed in the second semiconductor layer, and the second conductive semiconductor layer Is formed in the third semiconductor layer. Thereby, for example, by forming the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer by an epitaxial growth method,
These forming steps are performed by a bipolar transistor and a CMO.
Manufacturing process of semiconductor device incorporating S transistor (Bi
CMOS process) and BiCMOS
It is easy to mix and form them on a system semiconductor device.

The semiconductor device of the present invention described above preferably comprises
The substrate is a semiconductor substrate of the second conductivity type. Thus, the potential of the semiconductor substrate can be applied as the back gate potential of the transistor.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first semiconductor layer of a first conductivity type on an upper layer of a substrate, and a step of forming a first semiconductor layer in the first semiconductor layer. Forming a two-conductivity-type first buried layer, forming a first conductivity-type second semiconductor layer on the first semiconductor layer, and forming the second buried layer so as to be connected to the first buried layer. Forming a second buried layer of the second conductivity type in the semiconductor layer by incorporating an impurity of the second conductivity type at a lower concentration than the first buried layer; and forming a first buried layer on the second semiconductor layer.
Forming a conductive type third semiconductor layer; forming a second conductive type semiconductor layer including a channel formation region in the third semiconductor layer so as to be connected to the second buried layer; Forming a gate insulating film over the formation region; forming a gate electrode over the gate insulation film; and connecting the third semiconductor layer to the channel formation region on both sides of the gate electrode.・
Forming a drain region.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Forming a first semiconductor layer of a first conductivity type on an upper layer of the substrate;
A first buried layer of the second conductivity type is formed in the semiconductor layer.
Next, a second semiconductor layer of the first conductivity type is formed on the first semiconductor layer, and the second semiconductor layer of the second conductivity type is formed in the second semiconductor layer so as to be connected to the first buried layer. Impurities are contained at a low concentration to form a second buried layer of the second conductivity type. Next, a first conductive type third semiconductor layer is formed on the second semiconductor layer, and the second conductive type semiconductor layer including the channel formation region is formed in the third semiconductor layer so as to be connected to the second buried layer. To form Next, a gate insulating film is formed above the channel forming region, a gate electrode is formed above the gate insulating film, and source / drain regions connected to the channel forming region are formed in the third semiconductor layer on both sides of the gate electrode. Form.

According to the method of manufacturing a semiconductor device, the second conductive type semiconductor layer is provided in the first conductive type semiconductor layer below the second conductive type semiconductor layer such as a well having a channel formation region of a transistor. A buried layer of the same second conductivity type as the inside can be formed. Here, the buried layer is
Lower part (the side opposite to the side connected to the second conductivity type semiconductor layer:
It can be formed with a lower impurity concentration in a portion above the first buried layer (the side connected to the second conductivity type semiconductor layer: the second buried layer). When the method for manufacturing a semiconductor device described above is applied to a method for forming a high breakdown voltage transistor, a buried layer having a lower impurity concentration can be formed in an upper portion than in a lower portion as described above. The electric field in the depletion layer when a potential is applied to the electrode is reduced, and the electrons generated in the depletion layer are suppressed from being accelerated by the electric field in the depletion layer and trapped on the surface or inside of the gate insulating film. A semiconductor device which can suppress a change in transistor characteristics such as a shift in threshold value can be formed.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, in the step of forming the second conductivity type semiconductor layer, the second conductivity type semiconductor layer is formed by incorporating a second conductivity type impurity at a higher concentration than the second buried layer. In the second conductivity type semiconductor layer, the channel formation region can be formed while securing an impurity concentration necessary for obtaining a predetermined threshold value of the transistor. In this case, the transistor characteristics such as the shift of the threshold value of the transistor can be obtained as described above. Can be formed while suppressing the fluctuation of

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, a step of forming the first semiconductor layer;
In the step of forming a semiconductor layer and the step of forming the third semiconductor layer, a semiconductor layer is formed by an epitaxial growth method. Thereby, in particular, BiCMO
The compatibility with the S process is improved, and it is easy to mix and form on the BiCMOS semiconductor device.

The above-described semiconductor device of the present invention is preferably
The substrate is a semiconductor substrate of the second conductivity type. Thus, the potential of the semiconductor substrate can be applied as the back gate potential of the transistor.

[0034]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of the semiconductor device according to the present embodiment. For example, as a high breakdown voltage transistor, in particular, n
A semiconductor device having a channel type MOS field effect transistor will be described. For example, a first n-type epitaxial layer 11, a second n-type epitaxial layer 13, and a third n-type epitaxial layer 15 are stacked on a p-type silicon semiconductor substrate 10 to form a first conductivity type semiconductor layer. A first p-type buried layer 12 is formed from the first n-type epitaxial layer 11 to the lower p-type silicon semiconductor substrate 10 and the upper second n-type epitaxial layer 13. A second p-type buried layer 14 is formed from the second n-type epitaxial layer 13 to the lower first n-type epitaxial layer 11 and the upper third n-type epitaxial layer 15. Here, the second p-type buried layer 14 is set to contain a lower concentration of p-type impurities than the first p-type buried layer 12. For example, the impurity concentration of the first p-type buried layer 12 is 1 × 10 ¹⁶ to 8 ×
10 ¹⁶ atoms / cm ³ or so, the impurity concentration of the 2p-type buried layer 14 is ^{3 × 10 15 ~8 × 10 15} atoms / cm 3 or so.

Further, a p-type well (second conductive type semiconductor layer) 17 is formed in the third n-type epitaxial layer 15 constituting the first conductive type semiconductor layer, and serves as a channel forming region of the transistor. Further, a gate insulating film 25a of silicon oxide having a thickness of, for example, 100 to 200 nm is formed in an upper layer of the p-type well 17, and the upper layer contains impurities and has a sheet resistance of about 10 to 40 Ω / □. A gate electrode 30a of polysilicon is formed. An n-type well 16 is formed in the n-type epitaxial layer 15 on both sides of the gate electrode 30a, and an n ⁺ -type source / drain diffusion layer 18 is formed in the vicinity of the surface. The MOS field effect transistor is configured as described above, and the gate insulating film is formed much thicker than a normal low voltage drive type MOS transistor in order to obtain high withstand voltage characteristics.

In the above semiconductor device, the first
a first element isolation p-type buried layer 12a formed in each of the n-type epitaxial layer 11, the second n-type epitaxial layer 13, and the third n-type epitaxial layer 15,
On the surfaces of the second p-type buried layer 14a for element isolation, the p-type well 17a for element isolation, and the n-type epitaxial layer 15, element isolation is performed by the element isolation insulating film 24 formed by, for example, the LOCOS method. Gate electrode 3
On both sides of Oa, a silicon oxide sidewall insulating film 26 is formed, and further, for example, a silicon oxide-based first insulating film 28 and a second insulating film 29 are formed on the entire surface to cover the transistor. I have. Further, a contact hole reaching the source / drain diffusion layer 18 is opened in the first insulating film 28 and the second insulating film 29 and is made of, for example, aluminum.
Is formed.

According to the semiconductor device of the present embodiment,
A field effect transistor having a gate insulating film formed as a thick film as a high breakdown voltage transistor, and a buried layer formed under a well (second conductivity type semiconductor layer) having a channel formation region of the transistor; Since the impurity concentration is lower in the upper part than in the lower part, the electric field in the depletion layer when a potential is applied to the back gate (buried layer) and the gate electrode can be reduced, and the electrons generated in the depletion layer Can be suppressed from being accelerated by the electric field in the depletion layer and trapped on the surface or inside of the gate insulating film, whereby fluctuations in transistor characteristics such as a shift in the threshold value of the transistor can be suppressed.

A method for manufacturing the above semiconductor device will be described. First, as shown in FIG. 2A, a first n-type epitaxial layer 11 containing an n-type impurity at a low concentration on a p-type silicon semiconductor substrate 10 by an epitaxial growth method.
Is formed to a thickness of about 5 μm. Next, the silicon oxide layer 20 is formed to a thickness of about 100 nm by, for example, a thermal oxidation method. Next, a first p-type buried layer serving as a back gate of the transistor and a resist film R1 opening a formation region of the first p-type buried layer for element isolation are formed by a photolithography process, and the resist film R1 is used as a mask.
For example, p of boron (B) or the like by the existing ion implantation method
The type impurity D1 is introduced at a dose of 1 × 10 ¹³ atoms / cm ² . In the drawing, a region into which a p-type impurity has been introduced is indicated by “+”.

Next, as shown in FIG. 2B, the resist film R1 is peeled off with, for example, sulfated water (a mixed solution of sulfuric acid and hydrogen peroxide), and heat treatment is performed at, for example, 1200 ° C. for 200 minutes. Then, the p-type impurity introduced above is diffused and activated to form a first p-type buried layer 12 serving as a back gate of the transistor and a first element isolation p-type buried layer 12a.

Next, as shown in FIG.
The silicon oxide layer 20 is removed by etching such as IE (reactive ion etching), and then the second n-type impurity containing a low concentration of n-type impurities is epitaxially grown on the first n-type epitaxial layer 11 in the same manner as described above. The epitaxial layer 13 is formed to a thickness of about 4 μm.
Here, the p-type impurities in the first p-type buried layer 12 and the first element isolation p-type buried layer 12a also diffuse into the upper second n-type epitaxial layer 13 to form a diffusion layer having the shape shown in the drawing.

Next, as shown in FIG. 3D, a silicon oxide layer 21 is formed to a thickness of about 100 nm by, for example, a thermal oxidation method. Next, the formation regions of the second p-type buried layer and the second p-type buried layer for element isolation are formed by a photolithography process so as to be connected to the first p-type buried layer and the first p-type buried layer for element isolation, respectively. A resist film R2 having an opening is formed, and the resist film R2 is used as a mask.
For example, p of boron (B) or the like by the existing ion implantation method
The type impurity D2 is introduced at a dose of 1 × 10 ¹² atoms / cm ² . In the drawing, a region into which a p-type impurity has been introduced is indicated by “+”.

Next, as shown in FIG. 4E, the resist film R2 is peeled off, and a heat treatment is performed, for example, at 1200 ° C. for 300 minutes to diffuse and activate the p-type impurity introduced above. A second p-type buried layer 14 and a second p-type buried layer 14a for element isolation are formed. Here, the second p-type buried layer 14 corresponds to the first p-type buried layer 12.
It is formed so as to contain p-type impurities at a lower concentration than that.
For example, the impurity concentration of the first p-type buried layer 12 is 1 × 1
0 ¹⁶ to 8 × 10 ¹⁶ atoms / cm ³ , and the impurity concentration of the second p-type buried layer 14 is 3 × 10 ¹⁵ to 8 × 10 ¹⁵ atoms / cm ^3.
Degree. Next, the silicon oxide layer 21 is removed by etching such as RIE, and then a third n-type epitaxial layer containing n-type impurities at a low concentration is epitaxially grown on the second n-type epitaxial layer 13 in the same manner as described above. The layer 15 is formed with a thickness of about 5 μm.
Thus, a first conductivity type semiconductor layer including the first n-type epitaxial layer 11, the second n-type epitaxial layer 13, and the third n-type epitaxial layer 15 is formed. Here, the p-type impurities in the second p-type buried layer 14 and the second p-type buried layer 14a for element isolation also diffuse into the upper third n-type epitaxial layer 15 to form a diffusion layer having the shape shown in the drawing.

Next, as shown in FIG. 4F, a silicon oxide layer 22 is formed to a thickness of about 100 nm on the surface of the third n-type epitaxial layer 15 by, for example, a thermal oxidation method.
Next, a resist film R3 opening a region for forming an n-type well serving as a source / drain region of the transistor is formed by a photolithography process, and phosphorus (P) is formed by using the resist film R3 as a mask, for example, by an existing ion implantation method.
360 keV, 1 × 10 ¹³ atom
It is introduced at a dose of s / cm ² . In the drawing, a region into which an n-type impurity has been introduced is indicated by "-".

Next, as shown in FIG. 5G, the resist film R3 is peeled off, and a photolithography step is performed to open a p-type well serving as a transistor channel formation region and a p-type well formation region for element isolation. A resist film R4 is formed, and using the resist film R4 as a mask, a p-type impurity D4 such as boron (B) is introduced at a dose of 1 × 10 ¹³ atoms / cm ² at 360 keV by an existing ion implantation method. In the drawing, a region into which a p-type impurity has been introduced is indicated by “+”.

Next, as shown in FIG. 5H, the resist film R4 is peeled off and, for example, a CVD (Chemical Vapor Depos)
silicon nitride (Si ₃ N ₄ ) by 100
A silicon nitride layer 23 serving as a mask for forming an element isolation insulating film by a LOCOS method in a later step is formed. Next, for example, at 1200 ° C., 20
A heat treatment of 0 minutes is performed to diffuse and activate the p-type impurity and the n-type impurity introduced above,
N-type well 16 serving as a source / drain region, p-type well (second conductivity type semiconductor layer) 17 serving as a channel formation region
Then, an element isolation p-type well 17a is formed.

Next, as shown in FIG. 6 (i), an L layer is formed on the silicon nitride layer 23 by a photolithography process.
A resist film (not shown) for opening a region where an element isolation insulating film is to be formed by the OCOS method is patterned, and dry etching such as RIE is performed to pattern the silicon nitride layer 23 to form an element isolation insulating film. Is formed as a silicon nitride layer 23a covering a region excluding. After that, the resist film is peeled off.

Next, as shown in FIG. 6J, thermal oxidation is performed using the silicon nitride
A LOCOS element isolation insulating film 24 having a thickness of 0 nm is formed. Next, the silicon nitride layer 23a is removed by, for example, hot phosphoric acid-based wet etching.
100-200 by steam oxidation at 00-1000 ° C
The surface is oxidized to a thickness of nm to form a silicon oxide layer 25 serving as a gate insulating film of the high breakdown voltage transistor. Next, a p-type well 1 is formed by a photolithography process.
A resist film R5 opening seven regions is formed, and using the resist film R5 as a mask, a p-type impurity D5 such as boron (B) is applied at 60 keV, 1 × by an existing ion implantation method.
At a dose of 10 ¹² atoms / cm ² , the threshold of the transistor is adjusted.

Next, as shown in FIG. 7 (k), the resist film R5 is peeled off, and a resist film (not shown) for protecting a gate electrode formation region is formed on the silicon oxide layer 25 by photolithography to form a pattern. Then, for example, hydrofluoric acid-based wet etching is performed to pattern the silicon oxide layer 25 to form a silicon oxide gate insulating film 25a. After that, the resist film is peeled off.

Next, as shown in FIG.
The gate electrode layer 30 is formed by depositing polysilicon on the entire surface of the gate insulating film 25a containing impurities at a high concentration and a sheet resistance of about 10 to 40 Ω / □ by the VD method. Next, a resist film R6 for protecting a gate electrode formation region is formed in a pattern on the gate electrode layer 30 by a photolithography process.

Next, as shown in FIG. 8 (m), etching such as RIE is performed using the resist film R6 as a mask to pattern the gate electrode 30a. next,
For example, silicon oxide is deposited to a thickness of 300 nm by a CVD method, and is etched back by etching such as RIE to remove the silicon oxide deposited as described above except for the gate insulating film 25a and the side wall of the gate electrode 30a.
A side wall insulating film 26 is formed.

Next, as shown in FIG.
CV made from EOS (tetraethylorthosilicate)
A silicon oxide layer 27 having a thickness of about 20 nm is formed by the method D, and then arsenic (A) is formed by, for example, an existing ion implantation method.
s) The n-type impurity D6 such as 70keV, 1 × 10 ¹³ ~
The source / drain diffusion layer 1 is introduced by passing through the silicon oxide layer 27 at a dose of 5 × 10 ¹⁵ atoms / cm ^2.
8 is formed.

Next, silicon oxide is deposited to a thickness of about 150 nm by, for example, a CVD method to form a first insulating film 28, and then BPSG (silicon oxide containing boron and phosphorus) is deposited to a thickness of 500 nm by, for example, a CVD method. Then, the second insulating film 29 is formed by flattening by reflow, etch back, or the like. Next, the first insulating film 28
Then, a resist film for opening the source / drain diffusion layer region is formed on the upper layer of the second insulating film 29, and a contact hole reaching the source / drain diffusion layer 18 is opened by etching such as RIE. An electrode 31 connected to the source / drain diffusion layer 18 is formed by forming an aluminum layer on the entire surface by covering the above contact hole by sputtering and patterning the aluminum layer. Thus, the semiconductor device illustrated in FIG. 1 is obtained. In FIG. 1, illustration of the silicon oxide layer 27 is omitted.
In the subsequent steps, an upper wiring, a surface protection film, and the like are formed by, for example, a CVD method to obtain a desired semiconductor device.

According to the method of manufacturing a semiconductor device of the present embodiment, a gate insulating film is formed to be a thick film to form a field-effect transistor having a high breakdown voltage, such as a well having a transistor channel formation region. In the first conductivity type semiconductor layer below the second conductivity type semiconductor layer, a buried layer of the same second conductivity type as in the second conductivity type semiconductor layer can be formed. Here, the above-mentioned buried layer has a portion above the lower portion (the side opposite to the side connected to the second conductivity type semiconductor layer: the first buried layer) (the side connected to the second conductivity type semiconductor layer: the second buried layer). Layer) with a low impurity concentration. This alleviates the electric field in the depletion layer when a potential is applied to the back gate (buried layer) and the gate electrode, and the electrons generated in the depletion layer are accelerated by the electric field in the depletion layer to form a surface or inside the gate insulating film. A semiconductor device can be formed in which trapping can be suppressed and variation in transistor characteristics such as a shift in threshold value of a transistor can be suppressed.

In the method of manufacturing a semiconductor device according to the present embodiment, the first p-type buried layer 12 and the second p-type buried layer 14 are grown by growing an n-type epitaxial layer, and thereafter ion-implanted. It is formed by stacking an n-type epitaxial layer thereover,
The iCMOS process can be formed on the BiCMOS-based semiconductor device with good compatibility, and can be easily mounted on the semiconductor device. The thickness of these epitaxial layers can be, for example, about 4 to 6 μm.

The semiconductor device of the present invention is not limited to the above embodiment. For example, although an n-channel transistor is described, a p-channel transistor may be used. In this case, it can be configured by exchanging the n-type impurity and the p-type impurity. The gate electrode may have a multi-layer structure, for example, a polycide structure that is a laminate of polysilicon and a refractory metal silicide layer such as tungsten silicide. In addition, various changes can be made without departing from the gist of the present invention.

[0057]

According to the semiconductor device of the present invention, in the buried layer formed below the second conductivity type semiconductor layer having the channel formation region of the field effect transistor, the upper part is more impurity than the lower part. Since the concentration is low, the electric field in the depletion layer when a potential is applied to the back gate and the gate electrode can be reduced, and the electrons generated in the depletion layer are accelerated by the electric field in the depletion layer, and the surface of the gate insulating film and It is possible to suppress trapping inside, thereby suppressing a change in transistor characteristics such as a shift in the threshold value of the transistor.

According to the method of manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention can be easily manufactured, and can be formed under a second conductive type semiconductor layer such as a well having a channel formation region of a field effect transistor. A buried layer of the same second conductivity type as in the second conductivity type semiconductor layer can be formed in the first conductivity type semiconductor layer on the side. Here, the above-mentioned buried layer has a portion above the lower portion (the side opposite to the side connected to the second conductivity type semiconductor layer: the first buried layer) (the side connected to the second conductivity type semiconductor layer: the second buried layer). Layer) with a low impurity concentration. This alleviates the electric field in the depletion layer when a potential is applied to the back gate (buried layer) and the gate electrode, and the electrons generated in the depletion layer are accelerated by the electric field in the depletion layer to form a surface or inside the gate insulating film. A semiconductor device can be formed in which trapping can be suppressed and variation in transistor characteristics such as a shift in threshold value of a transistor can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG.
Until the ion implantation step for forming the p-type buried layer,
(B) shows up to a heat treatment step for diffusing and activating the impurities.

FIG. 3 shows a step that follows the step shown in FIG. 2;
Until the step of forming an n-type epitaxial layer, FIG.
The process up to the ion implantation step for forming the mold buried layer is shown.

FIG. 4 shows a step that follows the step shown in FIG. 3;
(f) shows up to the step of forming an n-type epitaxial layer and up to the step of forming an n-type well.

5 shows a step subsequent to that of FIG. 4. FIG. 5 (g) shows a step of forming a p-type well, and FIG. 5 (h) shows a step of forming a silicon nitride layer serving as a mask for forming a LOCOS element isolation film. Up to

6 shows a step subsequent to that of FIG. 5; (i) shows up to a silicon nitride layer pattern processing step; and (j) shows an ion implantation step for threshold adjustment.

FIG. 7 shows a step subsequent to that of FIG. 6, in which (k) shows up to a step of forming a gate insulating film, and (l) shows up to a step of forming a resist film for forming a gate electrode.

FIG. 8 shows a step subsequent to that of FIG. 7, in which (m) shows up to a step of forming a sidewall insulating film, and (n) shows up to a step of forming a silicon oxide film.

FIG. 9 is a sectional view of a semiconductor device according to a conventional example.

FIGS. 10A and 10B are cross-sectional views illustrating a manufacturing process of a method of manufacturing a semiconductor device according to a conventional example, in which FIG. 10A illustrates an ion implantation process for forming a p-type buried layer, and FIG. The steps up to a heat treatment step for diffusion and activation are shown.

FIG. 11 shows a step that follows the step shown in FIG. 10 (c).
Shows the steps up to the step of forming the n-type epitaxial layer, and (d) shows the steps up to the step of forming the n-type well.

FIG. 12 shows a step that follows the step shown in FIG. 11;
FIG. 4A shows the process up to the step of forming the p-type well, and FIG.

FIG. 13 shows a step that follows the step shown in FIG. 12, and (g)
Shows the process up to the patterning process of the silicon nitride layer, and (h) shows the process up to the ion implantation process for adjusting the threshold.

FIG. 14 shows a step that follows the step of FIG. 13, and (i)
FIG. 4A shows up to the step of forming a gate insulating film, and FIG. 4J shows up to the step of forming a resist film for forming a gate electrode.

FIG. 15 shows a step that follows the step shown in FIG. 14 (k).
1 shows up to the step of forming the sidewall insulating film, and (l) shows the step up to the step of forming the silicon oxide film.

16A is a cross-sectional view illustrating a problem of a semiconductor device according to a conventional example, and FIG. 16B is a diagram for measuring a threshold value of a transistor formed in the semiconductor device according to the conventional example. Circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... p-type semiconductor substrate, 11 ... 1st n-type epitaxial layer, 12 ... 1st p-type buried layer, 12a ... 1st element isolation p-type buried layer, 13 ... 2nd n-type epitaxial layer,
14: second p-type buried layer, 14a: second element isolation type buried layer, 15: third n-type epitaxial layer, 16 ...
n-type well, 17 ... p-type well, 17a ... p for element isolation
Mold well, 18: source / drain diffusion layers, 20, 2
1, 22: silicon oxide layer, 23: silicon nitride layer, 2
4: Element isolation insulating film, 25, 25a: Gate insulating film, 2
6 ... sidewall insulating film, 27 ... silicon oxide film, 2
8 first insulating film, 29 second insulating film, 30 and 30a gate electrode, 31 electrode, D1 to D6 conductive impurities, R
1 to R6: resist film, V: depletion layer, IL: inversion layer, E
... Electronics.

Claims (9)

[Claims] A first conductive semiconductor layer formed on a substrate; a second conductive semiconductor layer including a channel forming region formed on the first conductive semiconductor layer; and a first conductive semiconductor layer formed on the channel forming region. A gate insulating film, a gate electrode formed on an upper layer of the gate insulating film, and a second electrode formed in the first conductivity type semiconductor layer to be connected to the channel forming region on both sides of the gate electrode. A source / drain region of one conductivity type; a first buried layer of a second conductivity type formed in the first conductivity type semiconductor layer to be spaced downward from the second conductivity type semiconductor layer; A second conductivity type formed in the first conductivity type semiconductor layer by connecting a first conductivity type semiconductor layer and the first buried layer, and containing a second conductivity type impurity at a lower concentration than the first buried layer. A half having a second buried layer Body apparatus. 2. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the second buried layer is lower than the concentration of the second conductivity type impurity in the second conductivity type semiconductor layer. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the first conductive type semiconductor layer includes a first semiconductor layer formed on the substrate, a second semiconductor layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second semiconductor layer. A third semiconductor layer formed, wherein the first buried layer is formed in the first semiconductor layer, the second buried layer is formed in the second semiconductor layer, 2. The semiconductor device according to claim 1, wherein a two-conductivity-type semiconductor layer is formed in said third semiconductor layer. 4. The semiconductor device according to claim 3, wherein said first semiconductor layer, said second semiconductor layer, and said third semiconductor layer are semiconductor layers formed by an epitaxial growth method, respectively. 5. The semiconductor device according to claim 1, wherein said substrate is a semiconductor substrate of a second conductivity type. 6. A step of forming a first semiconductor layer of a first conductivity type on an upper layer of a substrate; a step of forming a first buried layer of a second conductivity type in the first semiconductor layer; Forming a second semiconductor layer of a first conductivity type above the layer; and an impurity of a second conductivity type in the second semiconductor layer than the first buried layer in the second semiconductor layer so as to be connected to the first buried layer. Forming a second buried layer of the second conductivity type by containing a low concentration of the second buried layer; forming a third semiconductor layer of the first conductivity type on the second semiconductor layer; Forming a second conductivity type semiconductor layer including a channel forming region in the third semiconductor layer so as to be connected to the third semiconductor layer; forming a gate insulating film above the channel forming region; Forming a gate electrode in an upper layer of the gate electrode; The method of manufacturing a semiconductor device having a step of forming a source-drain region connected to said channel formation region in the third semiconductor layer in the side portions. 7. The step of forming the second conductivity type semiconductor layer, wherein the second conductivity type semiconductor layer is formed by incorporating a second conductivity type impurity at a higher concentration than the second buried layer. Item 7. A method for manufacturing a semiconductor device according to Item 6. 8. The semiconductor layer is formed by an epitaxial growth method in each of the step of forming the first semiconductor layer, the step of forming the second semiconductor layer, and the step of forming the third semiconductor layer. Of manufacturing a semiconductor device. 9. The method according to claim 6, wherein said substrate is a semiconductor substrate of a second conductivity type.