KR100402238B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR100402238B1 KR100402238B1 KR1019960076363A KR19960076363A KR100402238B1 KR 100402238 B1 KR100402238 B1 KR 100402238B1 KR 1019960076363 A KR1019960076363 A KR 1019960076363A KR 19960076363 A KR19960076363 A KR 19960076363A KR 100402238 B1 KR100402238 B1 KR 100402238B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- film
- buried contact
- amorphous silicon
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000002245 particle Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 230000004888 barrier function Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005324 grain boundary diffusion Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Description
본 발명은 반도체 장치 제조방법에 관한 것으로, 특히 베리드 콘택을 가진 게이트 전극을 형성하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a gate electrode having a buried contact.
이하, 종래 기술 및 그 문제점을 살펴본다.Hereinafter, the prior art and its problems will be described.
먼저, 실리콘 기판 상부에 게이트 산화막을 형성하고, 그 상부에 베리드 콘택 폴리 실리콘막을 증착한 후, 그 상부에 베리드 콘택 형성을 위한 포토레지스트 패턴을 형성한다.First, a gate oxide film is formed on a silicon substrate, a buried contact polysilicon film is deposited on the silicon oxide film, and a photoresist pattern for forming a buried contact is formed thereon.
다음으로, 포토레지스트 패턴을 식각 장벽으로하여 베리드 콘택 폴리 실리콘막 및 게이트 산화막을 선택적 식각하고, 포토레지스트 패턴을 제거한 다음, 전체 구조 상부에 폴리 실리콘막을 증착하고, 폴리 실리콘막 상에 실리사이드막 형성한다. 계속하여, 실리사이드막 상부에 게이트 전극 형성을 위한 포토레지스트 패턴을 형성한다.Next, the buried contact polysilicon film and the gate oxide film are selectively etched using the photoresist pattern as an etch barrier, the photoresist pattern is removed, a polysilicon film is deposited on the entire structure, and a silicide film is formed on the polysilicon film. do. Subsequently, a photoresist pattern for forming a gate electrode is formed on the silicide film.
끝으로, 포토레지스트 패턴을 식각 장벽으로하여 실리사이드막, 폴리 실리콘막, 베리드 콘택 폴리 실리콘막 및 게이트 산화막을 차례로 선택적 식각하고, 포토레지스트 패턴을 제거한다.Finally, the silicide film, the polysilicon film, the buried contact polysilicon film, and the gate oxide film are selectively etched sequentially, using the photoresist pattern as an etch barrier, and the photoresist pattern is removed.
상기와 같은 공정을 통해 형성된 종래의 베리드 콘택은 결정 입자의 크기가 작은 폴리 실리콘막에 도핑된 불순물이 쉽게 실리사이드막에 확산되어 게이트 공핍영역을 크게 형성하여 콘택의 접촉 저항이 커지는 문제점이 있었다.In the conventional buried contact formed through the above process, impurities doped in a polysilicon film having a small crystal grain size are easily diffused into the silicide film to form a gate depletion region to increase the contact resistance of the contact.
본 발명은 결정 입자 크기가 큰 비정질 실리콘막을 사용하여 폴리 실리콘막내의 불순물이 실리사이드막으로 확산되는 것을 방지하는 반도체 장치 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device which prevents diffusion of impurities in a polysilicon film into a silicide film using an amorphous silicon film having a large crystal grain size.
도 1A 내지 도 1C는 본 발명의 일실시예에 따른 반도체 장치의 게이트 전극 형성 공정 단면도.1A to 1C are cross-sectional views of a gate electrode forming process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판 11 : 게이트 산화막10 silicon substrate 11 gate oxide film
12 : 베리드 폴리 실리콘막 13,16 : 포토레지스트 패턴12: buried polysilicon film 13,16: photoresist pattern
14 : 비정질 실리콘막 15 : 실리사이드막14 amorphous silicon film 15 silicide film
상기와 같은 목적을 달성하기 위하여 본 발명은 반도체 기판 상부에 게이트 절연막을 형성하는 단계; 상기 게이트 절연막 상부에 베리드 콘택 폴리 실리콘막을 형성하는 단계; 상기 베리드 콘택 형성을 위한 제1 마스크를 사용하여 상기 베리드 콘택 폴리 실리콘막 및 상기 게이트 절연막을 선택 식각하는 단계; 전체구조 상부에 상기 반도체 기판 상에 콘택되는 비정질 실리콘막을 형성하는 단계; 상기 비정질 실리콘막 상에 실리사이드막을 형성하는 단계, 및 게이트 전극 형성을 위한 제2 마스크를 사용하여 상기 실리사이드막, 상기 비정질 실리콘막, 상기 베리드 콘택 폴리 실리콘막 및 상기 게이트 절연막을 차레로 선택적 식각하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention comprises the steps of forming a gate insulating film on the semiconductor substrate; Forming a buried contact polysilicon layer on the gate insulating layer; Selectively etching the buried contact polysilicon layer and the gate insulating layer using the first mask for forming the buried contact; Forming an amorphous silicon film on the semiconductor substrate over the entire structure; Forming a silicide layer on the amorphous silicon layer, and selectively etching the silicide layer, the amorphous silicon layer, the buried contact polysilicon layer, and the gate insulating layer using a second mask for forming a gate electrode A step is made.
이하, 첨부된 도면 도 1A 내지 도 1C를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 1A to 1C.
먼저, 도 1A에 도시된 바와 같이 실리콘 기판(10) 상부에 게이트 산화막(11)을 형성하고, 그 상부에 베리드 콘택 폴리 실리콘막(12)을 약 200Å 내지 약 500Å두께로 증착한 후, 그 상부에 베리드 콘택 형성을 위한 포토레지스트 패턴(13)을 형성한다.First, as shown in FIG. 1A, the gate oxide film 11 is formed on the silicon substrate 10, and the buried contact polysilicon film 12 is deposited on the silicon substrate 10 to a thickness of about 200 GPa to about 500 GPa. A photoresist pattern 13 is formed on the buried contact.
다음으로, 도 1B에 도시된 바와 같이 포토레지스트 패턴(13)을 식각 장벽으로하여 베리드 콘택 폴리 실리콘막(12) 및 게이트 산화막(11)을 선택적 식각하고, 포토레지스트 패턴(13)을 제거한 다음, 전체 구조 상부에 비정질 실리콘막(14)을 약 1000Å 내지 약 3000Å 두께로 증착하고, 비정질 실리콘막(14) 상에 약 2000Å 내지 약 4000Å 두께의 실리사이드막(15) 형성한다. 계속하여, 실리사이드막(15) 상부에 게이트 전극 형성을 위한 포토레지스트 패턴(16)을 형성한다.Next, as shown in FIG. 1B, the buried contact polysilicon layer 12 and the gate oxide layer 11 are selectively etched using the photoresist pattern 13 as an etch barrier, and the photoresist pattern 13 is removed. The amorphous silicon film 14 is deposited to a thickness of about 1000 kPa to about 3000 kPa over the entire structure, and the silicide film 15 of about 2000 kPa to about 4000 kPa is formed on the amorphous silicon film 14. Subsequently, a photoresist pattern 16 for forming a gate electrode is formed on the silicide layer 15.
이때, 비정질 실리콘막(14)은 베리드 콘택 폴리 실리콘막(12) 내의 불순물이 실리사이드막(15) 내로 침투하는 것을 방지하는 역할을 한다. 불순물의 실리사이드막(15) 내로의 확산은 폴리 실리콘막의 결정립계 확산에 의한 불순물의 큰 확산도에 기인한다. 그러므로, 전체적인 결정입계의 길이 즉, 입자 크기를 크게 늘림으로써 불순물의 실리사이드막(15) 내로의 확산을 감소시킬 수 있게 된다. 또한, 베리드 콘택 폴리 실리콘막(12)은 비정질 실리콘막(14)을 곧바로 게이트 산화막(22) 상부에 형성하면 게이트 산화막(11)의 환원(deoxidization)을 방지하기 위하여 필요하다. 베리드 콘택 폴리 실리콘막(12)은 이러한 환원을 방지할 수 있는 최소의 두께로 증착함으로써 베리드 콘택 폴리 실리콘막(12) 내의 불순물의 집중도를 극대화시킬 수 있다.At this time, the amorphous silicon film 14 serves to prevent impurities in the buried contact polysilicon film 12 from penetrating into the silicide film 15. The diffusion of impurities into the silicide film 15 is attributable to the large diffusion of impurities due to the grain boundary diffusion of the polysilicon film. Therefore, the diffusion of impurities into the silicide film 15 can be reduced by greatly increasing the overall grain boundary length, that is, the particle size. In addition, the buried contact polysilicon film 12 is necessary to prevent deoxidization of the gate oxide film 11 when the amorphous silicon film 14 is formed directly on the gate oxide film 22. The buried contact polysilicon film 12 may be deposited to a minimum thickness to prevent such reduction, thereby maximizing the concentration of impurities in the buried contact polysilicon film 12.
끝으로, 도 1C에 도시된 바와 같이 포토레지스트 패턴(15)을 식각 장벽으로 하여 실리사이드막(15), 폴리 실리콘막(14), 베리드 콘택 폴리 실리콘막(12) 및 게이트 산화막(11)을 차례로 선택적 식각하고, 포토레지스트 패턴(16)을 제기한다. 이때, 베리드 콘택 인터커넥션(interconnection)도 동시에 형성된다.Finally, as shown in FIG. 1C, the silicide layer 15, the polysilicon layer 14, the buried contact polysilicon layer 12, and the gate oxide layer 11 are formed using the photoresist pattern 15 as an etch barrier. Selective etching in turn and photoresist pattern 16 are raised. At this time, the buried contact interconnection is also formed.
상기한 본 발명의 일실시예에 나타난 바와 같이 본 발명에 따라 형성된 게이트 전극은 게이트 산화막 상부에 베리드 콘택 폴리 실리콘막, 비정질 실리콘막 및 실리사이드막 구조를 형성하여 반도체 장치의 신뢰도 및 동작 특성의 개선을 기대할 수 있다.As described above, the gate electrode formed according to the present invention forms a buried contact polysilicon layer, an amorphous silicon layer, and a silicide layer structure on the gate oxide layer, thereby improving reliability and operation characteristics of the semiconductor device. You can expect.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기한 바와 같이 본 발명은 게이트 산화막 상부에 베리드 콘택 폴리 실리콘막, 비정질 실리콘막 및 실리사이드막 구조를 형성함으로써 게이트 공핍을 방지하고, 이로 인하여 접촉 저항을 감소시켜 반도체 장치의 동작 특성 및 신뢰도를 향상시키는 효과가 있다.As described above, the present invention forms a buried contact polysilicon film, an amorphous silicon film, and a silicide film structure on the gate oxide layer, thereby preventing gate depletion, thereby reducing the contact resistance, thereby improving operation characteristics and reliability of the semiconductor device. It is effective to let.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076363A KR100402238B1 (en) | 1996-12-30 | 1996-12-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076363A KR100402238B1 (en) | 1996-12-30 | 1996-12-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980057093A KR19980057093A (en) | 1998-09-25 |
| KR100402238B1 true KR100402238B1 (en) | 2004-02-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960076363A KR100402238B1 (en) | 1996-12-30 | 1996-12-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100402238B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06104203A (en) * | 1992-09-18 | 1994-04-15 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH06140355A (en) * | 1992-10-26 | 1994-05-20 | Nippon Steel Corp | Semiconductor device and manufacture thereof |
| JPH06291307A (en) * | 1993-03-30 | 1994-10-18 | Nippon Steel Corp | Manufacture of semiconductor device |
| JPH07142422A (en) * | 1990-12-05 | 1995-06-02 | Oki Electric Ind Co Ltd | Fabrication of semiconductor element |
-
1996
- 1996-12-30 KR KR1019960076363A patent/KR100402238B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07142422A (en) * | 1990-12-05 | 1995-06-02 | Oki Electric Ind Co Ltd | Fabrication of semiconductor element |
| JPH06104203A (en) * | 1992-09-18 | 1994-04-15 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH06140355A (en) * | 1992-10-26 | 1994-05-20 | Nippon Steel Corp | Semiconductor device and manufacture thereof |
| JPH06291307A (en) * | 1993-03-30 | 1994-10-18 | Nippon Steel Corp | Manufacture of semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR19980057093A (en) | 1998-09-25 |
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