JPH0521796A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To reduce the thickness of a silicon thin film constituting a channel portion or a gate electrode by forming a barrier metal after the opening of a contact hole. CONSTITUTION:After the opening of contact holes 511, titanium 512 and titanium nitride 513 are, in order, deposited over the contact hole. An aluminum thin film 514 is then deposited over them. A resist pattern 515 is then formed. Using this pattern as a mask, the aluminum thin film 514, titanium nitride 513, and titanium 512 are selectively etched to form a source interconnection 516, a drain interconnection 517, and a gate interconnection. The resist pattern 515 is then removed to form a thin-film transistor. Thus, it is possible to reduce the thickness of a silicon thin film constituting a channel portion or a gate electrode without contact failures, the increase of process, and the failure due to insufficient breakdown voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor applied to an active matrix type liquid crystal display, an image sensor, a three-dimensional integrated circuit and the like.

[0002]

2. Description of the Related Art An example of the structure of a conventional thin film transistor will be described with reference to FIG. Although this figure is a process cross-sectional view in the channel direction, a pattern 102 made of a silicon thin film such as polycrystalline silicon or amorphous silicon is formed on an insulating substrate 101 such as glass, quartz, or sapphire. Next, a gate insulating film 103 made of an insulating film such as a silicon oxide film is formed, and a conductive film 104 to be a gate electrode is further formed thereon. (See FIG. 1A) Next, a resist pattern 105 is formed by using a light exposure technique, and the conductive film 104 is selectively etched using the resist pattern 105 as a mask to form the gate electrode 106.
To form. (See FIG. 1B) Subsequently, the resist pattern 105 is removed, and an impurity serving as a donor or an acceptor is added by ion implantation to form the source region 107 and the drain region 108 in a self-aligned manner. At this time, the region to which no impurity is added becomes the channel region 109. After that (see FIG. 1C), an interlayer insulating film 110 is formed and a contact hole 111 is formed according to a normal process, and then a source wiring 11 made of metal, a transparent conductive film, or the like is formed.
2. Similarly, connect the drain wiring 113 to the source region 1 respectively.
07, the thin film transistor is completed by connecting to the drain region 108. (See Fig. 1 (d))

[0003]

However, the above-mentioned prior art has the following problems.

FIG. 2 is a graph showing an example of the characteristics of the thin film transistor having the structure described with reference to FIG. 1, where the horizontal axis is the gate voltage Vgs and the vertical axis is the logarithmic value of the drain current Id. Here, the source when the transistor is off,
The current flowing between the drains is called the off current Ioff, and the current flowing between the source and the drain when the transistor is in the on state is called the on current Ion. The characteristic that the on current is large and the off current is small, in other words, the on / off ratio Ion.
A large characteristic of / Ioff is desirable.

FIG. 3 is a graph in which the horizontal axis represents the film thickness of the silicon thin film forming the channel region, and the vertical axis represents the on-current and off-current. The thinner the film thickness, the better the characteristics of the TFT. Is obtained.

As can be seen from FIG. 1, when the thickness of the channel portion is reduced, the thickness of the source / drain portion is automatically reduced. As a result, if the film thickness is made too thin, it becomes difficult to make contact between the source region and the source wiring or between the drain region and the drain wiring. This is because aluminum is generally used as the wiring material, but at this time, the reaction between aluminum and silicon causes the so-called silicon to be eaten. If the silicon film thickness is large, no particular inconvenience occurs. However, if the silicon film thickness is thin, the supply of silicon is small and contact defects are likely to occur.

In order to solve the above-mentioned problems, a T structure having a structure in which the film thickness of the source / drain regions is made larger than the film thickness of the channel portion.
An FT has been proposed and will be described with reference to process sectional views of FIGS. A source region 402 and a drain region 403 are formed on an insulating substrate 401 made of glass, quartz, sapphire, or the like, which is made of a silicon thin film made of polycrystalline silicon or amorphous silicon to which impurities have been added. A channel region 404 made of a silicon thin film such as polycrystalline silicon or amorphous silicon is provided so as to be in contact with the upper sides of both and to connect the both. Next, the whole is covered with a gate insulating film 405 made of an insulating film such as a silicon oxide film, and a gate electrode 406 made of a metal, a transparent conductive film, an impurity-doped polycrystalline silicon film or the like is formed thereon. (See FIG. 4A) Subsequently, an interlayer insulating film 407 made of an insulating film such as a silicon oxide film is formed on the entire surface, and a contact hole 408 is formed.
Make an opening. After that (see FIG. 4B), a source wiring 409 and a drain wiring 410 made of a metal, a transparent conductive film, or the like are also formed through a contact hole 408 through a source hole 402 and a drain area 40, respectively, according to a normal process.
3 is connected to complete the thin film transistor. (Fig. 4
(See (c)) However, with this method, the number of steps increases and the step near the end of the gate electrode becomes severe. As a result, for example, the gate insulating film is only thinly formed in the step portion, which causes a new problem such as a breakdown voltage failure.

In addition, the conventional TFT has the following problems. In order to improve the characteristics of TFT, M
A method of terminating dangling bonds in a silicon thin film forming an OS interface or a channel portion with hydrogen (so-called hydrogenation) has been studied. By the way, when a silicon thin film added with an impurity is used as a gate electrode material, hydrogenation is generally performed after the gate electrode is formed. At this time, it is known that the thinner the silicon thin film is, the better the hydrogenation efficiency is. However, when the film thickness is reduced, the same problem as when the channel portion is reduced occurs.

[0009]

The thin film transistor of the present invention is characterized by forming a so-called barrier metal, which prevents reaction between aluminum and silicon, after opening a contact hole.

[0010]

Function The barrier metal is a technique generally used in, for example, LSI. In the case of an LSI, this is performed in order to prevent the PN junction from becoming shallow with the miniaturization and aluminum from penetrating and short-circuiting with the substrate. By applying this technique to a thin film transistor, a significant improvement in the performance of the thin film transistor can be achieved. That is, the thickness of the silicon thin film forming the channel portion or the gate electrode can be reduced without causing contact failure, increase in the number of steps, or withstand voltage failure of the gate insulating film. This makes it possible to provide an excellent thin film transistor having a large on-current and a small off-current, in other words, a large on / off ratio Ion / Ioff.

[0011]

EXAMPLES Example 1 The present invention will be described in detail based on the following examples. FIG. 5 is a process cross-sectional view in the channel length direction of the thin film transistor according to the present invention, which is made of a silicon thin film such as polycrystalline silicon or amorphous silicon on an insulating substrate 501 such as glass, quartz or sapphire and has a film thickness of 250 Å A pattern 502 of degree is formed. Next, a gate insulating film 503 made of an insulating film such as a silicon oxide film is formed, and a conductive film 504 to be a gate electrode is further formed thereon. (See FIG. 5A) Next, a resist pattern 505 is formed by using a light exposure technique, and the conductive film 504 is selectively etched using this as a mask to form a gate electrode 506. (See FIG. 5B) Subsequently, the resist pattern 505 is removed, and impurities serving as donors or acceptors are added by ion implantation to self-align with the source region 5.
07 and drain region 508 are formed. At this time, the region to which no impurity is added becomes the channel region 509. (See FIG. 5C) Next, formation of the interlayer insulating film 510,
After opening the contact hole 511, 500 Å titanium 512 and titanium nitride 5 are formed on the entire surface.
13 is sequentially deposited by 500Å. Then, an aluminum thin film 514 is deposited on the order of 8000 Å. (See FIG. 5D.) Next, a resist pattern 515 is formed by using a light exposure technique, and using this as a mask, the aluminum thin film 514, titanium nitride 513, and titanium 512 are selectively formed.
Are etched to form a source wiring 516 and a drain wiring 517. Although not shown here,
At the same time, gate wiring is formed. Then, the resist pattern 515 is peeled off to complete the thin film transistor according to the present invention. (See FIG. 5E) (Example 2) Such a thin film transistor can be realized by the following steps, for example. FIG. 6 is a process cross-sectional view in the channel length direction of the thin film transistor according to the present invention. It is made of a silicon thin film such as polycrystalline silicon or amorphous silicon on an insulating substrate 601 such as glass, quartz, sapphire, etc. A pattern 602 of degree is formed.
Next, the gate insulating film 6 made of an insulating film such as a silicon oxide film
03 is formed, and 500 Å which becomes the gate electrode on this
A polycrystalline silicon film 604 to which impurities are added is formed. (See FIG. 6A.) Next, a resist pattern 605 is formed by using a light exposure technique, and using this as a mask, the polycrystalline silicon film 604 selectively doped with impurities is etched to form a gate electrode 606. . (See FIG. 6B) Subsequently, the resist pattern 605 is removed, and impurities serving as donors or acceptors are added by ion implantation to self-align with the source region 607 and the drain region 60.
8 is formed. At this time, the region to which no impurity is added becomes the channel region 609. (See FIG. 6C) Next, an interlayer insulating film 610 is formed and exposed to, for example, a hydrogen plasma atmosphere to perform a hydrogenation process for improving TFT characteristics. Next, contact holes 611 are opened, and titanium 612 and titanium nitride 613 are sequentially deposited on the entire surface in the order of 500 Å and 500 Å, respectively. Then, an aluminum thin film 614 is deposited on the order of 8000 Å. (See FIG. 6D) Next, a resist pattern 615 is formed by using a light exposure technique, and the aluminum thin film 614, the titanium nitride 613, and the titanium 612 are selectively etched using the resist pattern 615 as a mask to form a source wiring. Similarly, a drain wiring 617 is formed. Although not shown here, the gate wiring is also formed at the same time. Then, the resist pattern 615 is peeled off to complete the thin film transistor according to the present invention. (See FIG. 6 (e)) Although the embodiment for realizing the present invention has been described above, the present invention can be realized by using a material other than those described here and does not depart from the scope of the claims.

[0012]

As described above, according to the thin film transistor of the present invention, the channel portion can be formed without causing a contact failure, an increase in the number of steps, or a withstand voltage failure of the gate insulating film.
Alternatively, the thickness of the silicon thin film forming the gate electrode can be reduced. This makes it possible to provide an excellent TFT having a large on-current and a small off-current, in other words, a large on / off ratio Ion / Ioff.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a cross-sectional structure of a conventional thin film transistor.

FIG. 2 is a graph showing characteristics of thin film transistors.

FIG. 3 is a graph showing a relationship between an on-current and an off-current of a thin film transistor and a film thickness of a silicon thin film forming a channel region.

FIG. 4 is a process cross-sectional view of a thin film transistor having a structure in which the thickness of a silicon thin film forming a channel portion is smaller than the thickness of a source / drain portion.

FIG. 5 is a process sectional view showing an embodiment for realizing the thin film transistor according to the present invention.

FIG. 6 is a process sectional view showing an embodiment for realizing a thin film transistor according to the present invention.

[Explanation of symbols]

101, 401, 501, 601 substrate 102, 502, 602 resist pattern 103, 405, 503, 603 gate insulating film 104, 504, 604 conductive film 105, 505, 515 605, 615 ... Resist patterns 106, 406, 506, 606 ... Gate electrodes 107, 402, 507, 607 ... Source regions 108, 403, 508, 608 ... Drain regions 109, 404, 509, 609 ... Channel regions 110, 407, 510, 610 ... Inter-layer insulating films 111, 408, 511, 611 ... Contact holes 112, 409, 516, 616 ... Source wirings 113, 410, 517, 617 ... Drain wiring 512, 612 ... Titanium 513, 613 ... Tita Nitride 514, 614 ... aluminum

Claims (7)

[Claims] 1. A source region and a drain region formed of a silicon thin film to which an impurity serving as a donor or an acceptor is added, and silicon formed between the source region and the drain region and in contact with the source region and the drain region. A channel region formed of a thin film, a gate insulating film formed so as to cover the source region, the drain region, and the channel region, a gate electrode provided on the gate insulating film, and connected to the source region. In a thin film transistor having a source line, a drain line connected to the drain region, and a gate line connected to the gate electrode, at least one of the source line, the drain line, and the gate line Is a multi-layer structure consisting of barrier metal and aluminum Transistor. 2. The thin film transistor according to claim 1, wherein the source region, the drain region and the channel region are formed of the same silicon thin film. 3. A film thickness of a silicon thin film forming the source region, the drain region and the channel region is 50.
The thin film transistor according to claim 2, wherein the thin film transistor has a thickness of 0 Å or less. 4. The thin film transistor according to claim 1, wherein the gate electrode is composed of a silicon thin film to which an impurity serving as a donor or an acceptor is added, and the film thickness is 500 Å or less. 5. A MOS interface after forming the gate electrode,
5. The thin film transistor according to claim 4, further comprising the step of terminating dangling bonds in the silicon thin film forming the channel portion with hydrogen. 6. The thin film transistor according to claim 1, wherein at least titanium is used as the barrier metal. 7. The thin film transistor according to claim 1, wherein a multilayer film made of at least titanium and titanium nitride is used as the barrier metal.