KR100344827B1 - Method for manufacturing semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device suitable for improving the isolation characteristics between devices in a highly integrated semiconductor memory device, the current driving capability of a transistor, and increasing the contact area of a cell contact to improve device reliability. Defining a field region and an active region, forming dummy word lines on a substrate of the active region, forming a dummy source / drain region in the substrate on both sides of the dummy word line, and the substrate and the dummy. Forming an epitaxial layer surrounding the word line, forming main word lines on the epitaxial layer to be aligned with the dummy word line, and forming a main source / epitaxial layer in the epitaxial layers on both sides of the main word line. Forming a drain region and being connected to the main drain region Step of forming a comprises a step of forming a storage node electrode to be connected to the main source region and a step of forming a dielectric layer and a plate electrode on the storage node electrode.

Description

Method of manufacturing semiconductor memory device {METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor memory device suitable for improving the data retention capability of a cell by improving isolation characteristics between cells.

As the device becomes more integrated, the cell size is reduced and the area occupied by the cell is reduced.

Such a decrease in cell area serves as an important factor to deteriorate the inter-cell isolation characteristics, and due to the deterioration of the inter-cell isolation characteristics, the ability to maintain data stored in the cell is degraded, which greatly affects the reliability of the device.

Hereinafter, a method of manufacturing a semiconductor memory device according to the related art will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the prior art.

As shown in FIG. 1A, an isolation region 12 is formed on the semiconductor substrate 11 using a trench isolation process to define an active region.

A plurality of word lines 14 are formed on the active region and the isolation region 12 via the insulating film 13.

That is, after the insulating film 13 is formed on the substrate including the isolation region 12, and the polysilicon layer is formed on the insulating film 13, a plurality of word lines formed in one direction at a predetermined interval ( 14) form.

As shown in FIG. 1B, source / drain ion implantation is performed in active regions on both sides of the word line 14 to form impurity diffusion regions 16a, 16b, and 16c.

After forming the first interlayer insulating layer 17 on the entire substrate including the word lines 14, the first interlayer insulating layer 17 is selectively removed to form the bit line contact 18.

That is, the first interlayer insulating layer 17 is etched to electrically connect the bit line and the active region to form a contact hole.

Thereafter, as shown in FIG. 1C, the bit line 20 is formed in the direction crossing the word line and connected to the impurity diffusion region through the bit line contact 18, and includes the bit line 20. The second interlayer insulating film 21 is formed on the substrate.

Thereafter, the second interlayer dielectric layer 21 and the first interlayer dielectric layer 17 are selectively removed to form a storage node contact 22 through which the active region is exposed.

As shown in FIG. 1D, a plug 23 is formed in the storage node contact 22, and a storage electrode 24 electrically connected to the plug 23 is formed.

Subsequently, when the dielectric layer 25 and the plate electrode 26 are formed on the storage node electrode 24, the semiconductor memory device manufacturing process according to the related art is completed.

Such a conventional semiconductor memory device stores electric charge in the dielectric film 25 between the storage electrode 24 and the plate electrode 26 by turning on / off the current of the transistor in accordance with the voltage applied to the word line 14 or The stored charge is transferred to the sensing amplifier (not shown) through the bit line 20.

However, the conventional semiconductor memory device as described above has the following problems.

Isolation between devices is a trench isolation process, but isolation characteristics are deteriorated due to the integration dimension being limited by the degree of integration.In this case, leakage current at the source / drain junctions of the storage electrodes and transistors increases, causing Data retention capacity is reduced.

In addition, as the pitch of the word line decreases, the length of the active region decreases, thereby reducing the channel length, the dimension of the cell contact, and the like of the transistor divided within the region, thereby increasing the resistance of the cell contact. There was a problem of causing the deterioration of the reliability of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and improves the isolation characteristics between devices in the highly integrated semiconductor memory device, improves the current driving capability of the transistor, and increases the contact area of the cell contact, thereby improving the reliability of the device. It is an object of the present invention to provide a method for manufacturing a semiconductor memory device suitable for improvement.

1A to 1D are cross-sectional views illustrating a method of fabricating a semiconductor memory device according to the related art.

2 is a layout diagram according to a method of manufacturing a semiconductor memory device of the present invention;

3 is a structural cross-sectional view of a semiconductor memory device according to the present invention.

4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention.

Explanation of symbols for main parts of the drawings

41: semiconductor substrate 43a, 44a: dummy word line

46: epitaxial layer 48a, 48b, 48c, 48d: main word line

49a, 49b, 49c: main source / drain impurity diffusion region

51: bit line 52: storage node electrode

53 dielectric layer 54 plate electrode

A semiconductor memory device manufacturing method of the present invention for achieving the above object is a step of defining a semiconductor substrate as a field region and an active region, forming a dummy word line on the substrate of the active region, both sides of the dummy word line Forming a dummy source / drain region in the substrate, forming an epitaxial layer surrounding the substrate and the dummy wordline, and aligning the main wordlines with the dummy wordline on the epitaxial layer. Forming a process, forming a main source / drain region in the epitaxial layers on both sides of the main word line, forming a bit line to be connected to the main drain region, and a storage node to be connected to the main source region. Forming an electrode, and forming a dielectric layer and a plate electrode on the storage node electrode. It comprises the step of.

Hereinafter, a method of manufacturing a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a layout diagram illustrating a semiconductor memory device of the present invention, and FIG. 3 is a cross-sectional view of the semiconductor memory device of the present invention, and is taken along line II ′ of FIG. 2.

As shown in FIG. 2, the semiconductor memory device of the present invention has an epitaxial epitaxial layer 46 having an inverted T shape, and main word lines 48a, 48b, 48c, and 48d on the epitaxial layer 46. Is formed and has dummy word lines 43a and 44a formed in the same direction as the main word line under the epitaxial layer 46.

The epitaxial layer is used as a pad of a channel, a bit line contact, and a storage node contact of the transistor.

FIG. 3 is a cross-sectional view taken along line II ′ of FIG. 2, and includes a semiconductor word 41, dummy word lines 43a and 44a formed at regular intervals on the substrate 41, and the dummy word lines. Dummy source / drain impurity diffusion regions 45a, 45b, and 45c formed in the substrates on both sides of the substrate 43a and 44a, the epitaxial layer 46 formed on the dummy word lines 43a and 44a and the substrate, and the epitaxial layer. A plurality of main word lines 48a, 48b, 48c, and 48d formed on the tactical layer 46 and aligned with the dummy word lines 43a and 44a, and epitaxial layers 46 on both sides of the main word line. In the main source / drain impurity diffusion regions 49a, 49b and 49c, and bit lines 51 connected to the main drain impurity region 49a through contact holes, and the source impurity diffusion regions 49b and 49c. And the storage node electrode 52 connected through the contact hole, and the dielectric layer 53 and the plate formed on the storage node electrode 52. It is configured to include a byte electrode 54.

A method of manufacturing a semiconductor memory device of the present invention configured as described above will be described with reference to the accompanying drawings.

4A to 4E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device of the present invention.

As shown in FIG. 4A, the semiconductor substrate 41 is defined as a field region 42 and an active region. In this case, the field region is formed by a trench isolation process.

After the first insulating layer is formed on the entire surface of the substrate including the field region, it is selectively removed to form first and second insulating layer patterns 43 and 44 that maintain a predetermined distance on the substrate of the active region.

Here, the first and second insulating layer patterns 43 and 44 are dummy word lines, and are formed of silicon nitride.

Thereafter, dummy source / drain impurity diffusion regions 45a, 45b, and 45c are formed in the substrate on both sides of the first and second insulating layer patterns 43 and 44 by implanting and diffusing impurity ions.

As shown in FIG. 4B, an epitaxial layer 46 is formed through epitaxial growth using the substrate as a seed.

At this time, the epitaxial layer 46 has an inverted T shape, as shown in FIG. 2.

As shown in FIG. 4C, the first and second insulating layer patterns 43 and 44, which are the dummy word lines, are removed by a wet etching process to form the space regions 43a and 44a.

Subsequently, a plurality of main word lines 48a, 48b, 48c, and 48d are formed on the epitaxial layer 46 via the gate insulating layer 47.

In this case, the main word lines 48a, 48b, 48c, and 48d are formed to be aligned with the empty space areas 43a and 44a.

Thereafter, main source / drain impurity diffusion regions 49a, 49b, and 49c are formed in the epitaxial layer 46 on both sides of the main word lines 48a, 48b, 48c, and 48d through impurity ion implantation and diffusion.

As shown in FIG. 4D, an interlayer insulating film 50 is formed on the entire surface including the main word lines 48a, 48b, 48c, and 48d.

Thereafter, a bit line 51 electrically connected to the main drain region impurity diffusion region 49a is formed.

After the interlayer insulating layer 50a is formed on the entire surface including the bit line 51, the storage node contact is formed to expose the main source impurity diffusion regions 49b and 49c by using a photo process.

Subsequently, storage node electrodes 52 electrically connected to source impurity diffusion regions 49b and 49c are formed through the storage node contact.

When the dielectric layer 53 and the plate electrode 54 are sequentially formed on the storage node electrode 52, the semiconductor memory device manufacturing process of the present invention is completed.

Such a semiconductor memory device manufacturing method of the present invention has the following effects.

First, by using an epitaxial layer as a channel in addition to a channel using a substrate, the current driving capability of the transistor is more than doubled.

Second, the contact area of the storage node contacts in the longitudinal direction of the field region can be increased, and an impurity diffusion region exists at the boundary between the field region and the dummy word line, thereby reducing the electric field.

Third, the epitaxial layer can be patterned in a different form from the field region, so the layout design is free.

Claims (3)

Defining a semiconductor substrate as a field region and an active region; Forming dummy word lines on a substrate in the active region; Forming a dummy source / drain region in the substrate on both sides of the dummy word line; Forming an epitaxial layer to surround the substrate and the dummy word line; Forming main word lines on the epitaxial layer to align with the dummy word lines; Forming a main source / drain region in the epitaxial layers on both sides of the main word line; Forming a bit line to be connected to the main drain region; Forming a storage node electrode to be connected to the main source region; And forming a dielectric layer and a plate electrode on the storage node electrode. The method of claim 1, wherein the epitaxial layer is epitaxially grown using a substrate as a seed. The method of claim 1, wherein the forming of the dummy word line comprises: Forming a first insulating layer on the substrate; Patterning the first insulating layer to form first insulating layer patterns having a predetermined distance from each other on a substrate of the active region; Forming a dummy source / drain impurity region by implanting impurity ions using the first insulating layer patterns as a mask; Growing the epitaxial layer; And removing the first insulating layer pattern by wet etching.