KR0151192B1 - Manufacture of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and to forming a memory device capacitor in a large capacity semiconductor.

The present invention provides a process for forming a first oxide film on a semiconductor substrate, selectively etching the first oxide film to form a first oxide film pattern, forming a first epitaxial layer on the exposed substrate, Forming a second oxide layer on the first oxide pattern and the first epitaxial layer, selectively etching the second oxide layer to form a second oxide layer pattern, and exposing the second oxide layer to the second oxide layer. Forming a second epitaxial layer on the first epitaxial layer and the first oxide layer pattern, forming a third oxide layer on the second oxide pattern and the first epitaxial layer, and subjecting the third oxide layer to a photolithography process. Selectively etching to form a third oxide film pattern, forming a third epitaxial layer on the second epitaxial layer and the second oxide film pattern exposed by the etching of the third oxide film, and the second 1 oxide film A second oxide layer pattern and a provides a semiconductor memory device manufacturing method comprising the step of removing the third oxide film pattern.

Description

Semiconductor Memory Device Manufacturing Method

1 is a process flowchart showing a conventional method of manufacturing a semiconductor memory device.

2 is an equivalent circuit diagram of a memory cell of a semiconductor memory device.

3 is a view concurrent with the trench forming method according to the present invention.

4 is a process flowchart showing a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

100: semiconductor substrate 26: storage node

27 dielectric film 28 first conductive layer

29 gate insulating film 30 gate electrode

31: gate cap oxide film 32: small source and drain region

34: insulating layer 35: third conductive layer

36: interlayer insulating film 37: bit line

40: plate electrode

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a capacitor of a semiconductor memory device having a large capacity.

BACKGROUND With the development of semiconductor devices, the work of integrating many devices with a high degree of collecting on one semiconductor chip has been actively performed. In particular, in the memory cells of DRAM (Dynamic Random Access Memory), various various cell structures have been proposed to minimize the device size.

It is desirable to configure a memory cell with one transistor and one capacitor in view of minimizing the area occupied on a chip for high integration. As described above, in a memory cell including one transistor and one capacitor, signal charges are stored in a storage node of a capacitor connected to a transistor (switching transistor). Therefore, when the memory cell size is reduced due to the high integration of the semiconductor memory device, the capacitor size is also reduced, thereby reducing the number of signal charges that can be stored in the storage node. Therefore, in order to deliver the desired signal without malfunctioning, the capacitor storage node of the memory cell must have a surface area above a certain value in order to secure the capacitor capacity required for signal transmission.

Therefore, in order to reduce the memory cell size, the storage node of the capacitor must have a relatively large surface area in the proposed area on the semiconductor substrate.

The method of forming the trench capacitor structure disclosed in US Pat. No. 4,721,987, which is one of the three-dimensional capacitor structures, among the various memory cell structures proposed to increase the surface area of the capacitor storage node is described with reference to FIG. .

First, as shown in FIG. 1A, a thermal oxide film 1 and a nitride film 2 are sequentially formed on the semiconductor substrate 100 and then selectively etched by a photolithography process to form bit lines. After exposing the region 3 and the region 4 on which the capacitor is to be formed, N-type impurities are implanted into the N ⁺ region (5,6) in the semiconductor substrate of the bit line forming region 3 and the capacitor forming region 4. ) Respectively. The N ⁺ region 5 later becomes the N ⁺ bit line 10 and the N ⁺ region 6 becomes the N ⁺ region 11 of the capacitor.

Subsequently, an oxide film 7 is formed on the entire surface of the substrate as shown in FIG. 1 (b), and then selectively etched through the photolithography process to expose the substrate region where the trench is to be formed, and then the oxide film 7 is removed. The trench 8 is formed by anisotropically etching the substrate as a mask. In this case, the trench 8 is formed by a two-step process. First, the substrate is shallowly etched using the oxide film 7 as a mask, and at the same time, the bottom portion of the oxide film 7 is undercut to undercut the N ⁺ region ( Etch a part of 6). Subsequently, a thermal oxidation process is performed to form an oxide film 9 on the trench inner wall including the etched portion of the N ⁺ region 6, and then an oxide film formed on the etched portion of the oxide layer 7 and the N ⁺ region 6. Using the mask (9) as a mask, the trench 8 is etched to the desired predetermined depth to form the trench 8.

Next, as shown in FIG. 1C, the oxide film 7 is removed, and then thermal oxidation is performed to form the oxide films 12 and 13. At this time, the oxide films 12 and 13 is so much faster growth in the N ⁺ region (10, 11) than the impurities in the trench region is doped with a very low impurity concentration of the heavily doped N ⁺ region (10, 11) When the thickness of the oxide films 12 and 13 on the phase is about 4000 GPa, the thickness of the oxide film formed in the trench region is about 200 GPa. After removing the thin oxide film formed in the trench region, the oxide film 21 is grown again on the inner wall of the trench as shown in FIG. Subsequently, polysilicon is deposited on the entire surface of the substrate including the trench inner wall, and then the polysilicon layer is patterned by photolithography to form a plate electrode 14 to complete the capacitor.

The capacitor manufacturing method of the semiconductor memory device according to the related art is characterized by using a trench to increase the capacitor capacity and to use a doped substrate region with a high concentration by an ion implantation process as a bit line.

An equivalent circuit diagram of the semiconductor memory device according to the prior art is shown in FIG.

The gate of the transistor T is connected to the word line W / L, the fast transistor T is connected to the bit line B / L, and the storage capacitor C is connected to the fast transistor T and Vss. Connected between the operation is made.

However, in the above-described conventional technology, since the capacitor storage node region is formed only in the vertical direction of the substrate, there is a limit to increasing the capacitor capacity. When the substrate is etched to form the trench, a crack is generated at the corner of the trench to charge the charged charge. There is a risk of leakage, and there is a difficulty in forming the trench by etching the substrate to a uniform depth.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and an object thereof is to provide a method for increasing the capacitor capacity of a semiconductor memory device.

The semiconductor memory device manufacturing method of the present invention for achieving the above object is a step of repeating the step of forming an oxide film pattern on a semiconductor substrate and an epitaxial layer formed on the exposed substrate portion at least twice or more, and the oxide film pattern It characterized in that it comprises a step of removing.

The semiconductor memory device of the present invention comprises the steps of forming a first oxide film on the semiconductor substrate 100, selectively etching the first oxide film to form a first oxide film pattern 21A, on the exposed substrate Forming a first epitaxial layer 21, forming a second oxide film on the first oxide pattern 21A and the first epitaxial layer 21, and selectively etching the second oxide film Forming a second oxide layer pattern 22A, and forming a second epitaxial layer 22 on the first epitaxial layer 21 and the first oxide layer pattern 21A, which are exposed by etching the second oxide layer. Forming a third oxide film on the second oxide pattern 22A and the first epitaxial layer 22 and selectively etching the third oxide film by a photolithography process to form a third oxide pattern 23A. ), The second epitaxial layer 22 and the second oxide exposed by the etching of the third oxide film. Forming a third epitaxial layer 23 on the pattern 22A, and removing the first oxide film pattern 21A, the second oxide film pattern 22A, and the third oxide film pattern 23A. It is done by

As described above, a multilayer epitaxial layer and a multilayer oxide film pattern are sequentially formed, and then only the oxide film pattern is removed to form a trench. At this time, by varying the size of the oxide pattern of the multilayer, the trench side formed by removing the oxide layer pattern is irregular and not vertical, thereby increasing the effective area of the capacitor storage node formed in the trench to increase the capacitor capacity. Increase

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

A trench forming method for manufacturing a capacitor of a semiconductor memory device according to the present invention will be described with reference to FIG.

FIG. 3A illustrates a trench forming method according to an embodiment of the present invention. First, an oxide film is formed on a semiconductor substrate 100 by a chemical vapor deposition (CVD) method, and then a photolithography process is performed. The first epitaxial layer 21 is selectively etched to form the first oxide pattern 21A, and then the first epitaxial layer 21 is formed on the exposed substrate through a selective epitaxial layer forming process. Subsequently, an oxide film is formed on the first oxide pattern 21A and the first epitaxial layer 21 by CVD, and then selectively etched by a photolithography process to form a second oxide pattern 22A. Next, a second epitaxial layer 22 is formed on the exposed first epitaxial layer 21 through a selective epitaxial layer forming process. Subsequently, an oxide film is formed on the second oxide film pattern 22A and the first epitaxial layer 22 by CVD, and then selectively etched by a photolithography process to form a third oxide film pattern 23A. Next, a third epitaxial layer 23 is formed on the exposed second epitaxial layer 22 through a selective epitaxial layer forming process. When the first, second and third oxide film patterns 21A, 22A, and 23A formed as described above are removed, a trench having a “+” shape is formed.

Figure 3 (b) relates to the trench formation method according to another embodiment of the present invention, the same as the method of Figure 3 (a), but the letter "T" lying sideways instead of the "+" It is formed to form. Therefore, when the oxide film pattern is removed, a trench having a T-shape laid on its side is formed.

In addition to the case of FIGS. 3A and 3B, trenches having irregular sidewall shapes having various shapes may be formed by varying sizes of the oxide layer patterns.

Next, an embodiment of the present invention for manufacturing a capacitor by applying the trench forming method will be described with reference to FIG.

First, as shown in FIG. 4A, an oxide film embedded in the epitaxial layer 24 and the epitaxial layer 24 on the silicon substrate 100 by the method of FIG. 3B. After the patterns are formed, the oxide layer patterns are etched by wet etching to form a “T” shaped trench. Subsequently, a PSG (Phosphosilicate Glass) film 25 is formed on the epitaxial layer 24 including the trench. Next, impurity ions, ie, phosphorus (P), are diffused from the PSG film 25 into the substrate on the inner wall of the trench by the high temperature diffusion process to form the storage node 26.

Next, as shown in FIG. 4 (b), the constant PSG film is removed by wet etching, and then a capacitor dielectric film 27 is formed on the entire surface of the epitaxial layer 24 including trenches, and then the capacitor plate electrode is formed. As the first conductive layer, for example, an impurity doped polysilicon 28 is deposited to bury the trench. The polysilicon 28 and capacitor dielectric film 27 are then etched back so as to remain only in the trench.

Subsequently, as shown in FIG. 4 (c), a gate insulating film 29 is formed on the epitaxial layer 24 including the trench region, and polysilicon is formed as a second conductive layer for forming the gate electrode thereon. After the deposition, the gate cap oxide film 31 is formed thereon, the gate cap oxide film 31 and the polysilicon layer are patterned into a predetermined gate electrode pattern to form the gate electrode 30. Subsequently, an N-type impurity is implanted at low concentration to form an N-region in a predetermined region of the substrate, an insulating film is deposited on the entire surface of the substrate, and then etched back to form sidewall spacers 33 on the sidewalls of the gate electrode 30. Subsequently, the source and drain regions 32 having a lightly doped drain (LDD) structure are formed by ion implanting N-type impurities at a high concentration to form a N + region, thereby completing a transfer transistor of a semiconductor memory device.

Next, as shown in FIG. 4D, an insulating layer 34 is formed on the entire surface of the substrate including the trench region and the transistor, and then selectively etched to expose the trench region. Subsequently, as the third conductive layer 35 for forming the capacitor plate electrode, polysilicon is deposited so as to be connected to the polysilicon layer 28 embedded in the trench, and then the polysilicon layer 35 is connected to the capacitor plate electrode pattern. By patterning, the capacitor plate electrode 40 including the polysilicon layer 28 in the trench and the polysilicon layer 35 on the trench is formed. In this manner, a capacitor of the semiconductor memory device including the storage node 26, the dielectric film 27, and the plate electrode 40 is obtained. Subsequently, an interlayer insulating layer 36 is formed on the entire surface of the substrate on which the transfer transistor and the capacitor are formed, and then selectively etched to expose the source or drain region 32 of the transfer transistor uniaxial (opposite to the trench region), and then to the interlayer. By forming a fourth conductive layer 37 for forming a bit line on the insulating layer 36 and patterning the fourth conductive layer 37 in a predetermined bit line pattern, a bit line 37 connected to the transfer transistor is formed to complete a semiconductor memory device. .

As described above, according to the present invention, by increasing the number of epitaxial layers as needed, the capacitor capacity per unit area can be sufficiently obtained as desired.

Therefore, high integration of the semiconductor memory device can be achieved.

Claims (8)

Forming a first oxide film on the semiconductor engine (100), and selectively etching the first oxide film to form a first oxide film pattern (21A) having a first size. Forming a first epitaxial layer 21 on the exposed substrate, forming a second oxide film on the first oxide pattern 21A and the first epitaxial layer 21, and forming the second oxide film Selectively etching to form a second oxide film pattern 22A having a second size, on the first epitaxial layer 21 and the first oxide film pattern 21A exposing the second oxide film by etching. Forming a second epitaxial layer 22 on the substrate, forming a third oxide film on the second oxide film pattern 22A and the first epitaxial layer 22, and subjecting the third oxide film to a photolithography process. Selectively etching to form a third oxide film pattern 23A having a third size, on the second epitaxial layer 22 and the second oxide film pattern 22A exposed by the etching of the third oxide film. Forming a third epitaxial layer 23 and removing the first oxide layer pattern 21A, the second oxide layer pattern 22A, and the third oxide layer pattern 23A. Method of manufacturing a semiconductor memory device characterized in that it comprises a step. The method of claim 2, wherein at least one of the first oxide pattern, the second oxide pattern, and the third oxide pattern is formed to have a wider width than the remaining patterns. The method of claim 2, wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are formed by a selective epitaxial layer growth method, respectively. Forming an oxide film pattern on the semiconductor substrate and forming the epitaxial layer 24 on the exposed substrate portion at least twice; and removing the oxide film pattern from the oxide film pattern to form the epitaxial layer ( Forming a trench in 24, forming a storage node 26 by doping impurity ions to a substrate portion of the inner wall of the trench, and forming a capacitor dielectric layer 27 on the storage node 26. Filling the inside of the trench with a first conductive layer (28) and forming a gate insulating film (29) on the epitaxial layer (24) including the trench region. Forming a second conductive layer on the gate insulating film (29). Patterning the second conductive layer to form a gate electrode (30). Forming a source and drain region 32 in the substrate regions at both ends of the gate electrode, forming an insulating layer 34 on the entire surface of the substrate on which the trench region and the gate electrode and the source and drain regions are formed, and the insulating layer Selectively etching 34 to expose the trench region, forming a third conductive layer on the insulating layer 34, and patterning the third conductive layer 35 into a capacitor plate electrode pattern. A semiconductor memory device manufacturing method comprising the step of. The method of claim 6, wherein the oxide layer pattern is removed by wet etching. The method of claim 6, wherein the trench has an irregular side shape rather than a vertical shape. The method of claim 6, wherein the storage node 26 includes the impurities 25 on the epitaxial layer 24 including the trenches, and then includes only the impurities in the trench inner wall through an etch back process. And leaving impurity ions into the substrate on the inner wall of the trench from the film containing the impurity by a high temperature diffusion process. 7. The method of claim 6, wherein the capacitor plate electrode (40) is formed by a first conductive layer (28) embedded in the trench and a third conductive layer (35) on the trench.