CN106449759B - Isolated form LDMOS structure and its manufacturing method - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000002955 isolation Methods 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 239000000463 material Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008094 contradictory effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The present invention provides a kind of isolated form LDMOS structure and its manufacturing method, including the isolation moat structure being integrated on same P type substrate substrate and LDMOS structure；Isolation moat structure is located inside the P type substrate between the second p-type heavily doped region of LDMOS structure and p-type diffusion well region, isolation moat structure includes the first oxide layer of at least one slot, the filled media inside slot, the first area P of trench bottom, groove edge, and slot upper surface is the third oxide layer of LDMOS；The present invention injects semiconductor impurities identical with substrate material doping type in isolation trench bottom, it solves source surface and shifts to an earlier date breakdown problem, further increase breakdown voltage, meanwhile slot isolation helps to inhibit the horizontal expansion of LDMOS well region, reduces device area size, the present invention changes the field distribution close to source, drift doping concentration is improved, and then improves device pressure resistance and reduces than conducting resistance, has been advanced optimized than conducting resistance and breakdown voltage relationship.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of isolated form LDMOS structure and its manufacturing method.
Background technique
LDMOS (Lateral Double-Diffused MOSFET) is a kind of common semiconductor devices, has Gao Gong
The advantages that rate gain, high efficiency and low cost, in semiconductor technology using quite extensively.To improve LDMOS breakdown voltage, increase
Big output power generallys use the method for increasing drift region length and reducing drift doping concentration, this will lead to device ratio and leads
The resistance that is powered increases, and increases power consumption.Since RESURF technology and groove isolation technique propose, Single-RESURF LDMOS,
Double RESURF LDMOS、Triple RESURF LDMOS、Multiple RESURF LDMOS、3D RESURF
LDMOS, SJ LDMOS etc., which improve structure, has significant effect than conducting resistance to reduction.However this class formation can not change completely
The kind intracorporal field distribution problem of device, however it remains between device pressure resistance and conducting resistance the problem of contradiction.
Summary of the invention
The present invention proposes a kind of isolated form LDMOS knot for LDMOS breakdown voltage and the contradictory relation than conducting resistance
Structure and its manufacturing method.
For achieving the above object, technical solution of the present invention is as follows:
A kind of isolated form LDMOS structure is tied including the isolation moat structure being integrated on same P type substrate substrate and LDMOS
Structure；The isolation moat structure is located in the P type substrate between the second p-type heavily doped region of LDMOS structure and p-type diffusion well region
Portion, isolation moat structure include the first oxidation of at least one slot, the filled media inside slot, the first area P of trench bottom, groove edge
Layer, the filled media and the semiconductor silicon material outside slot, slot upper surface that first oxide layer is used for inside isolation channel are
The third oxide layer of LDMOS.
It is preferred that the LDMOS structure be Single-RESURF LDMOS, Double RESURF LDMOS,
Triple RESURF LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, SJ LDMOS are one such.
It is preferred that the LDMOS structure includes P type substrate, N-type diffusion well region, p-type diffusion well region, the 2nd P
Area, the first p-type heavily doped region, the second p-type heavily doped region, the first N-type heavily doped region, the second N-type heavily doped region, the second oxidation
Layer, third oxide layer, grid, source electrode, drain electrode, underlayer electrode, body electrode；N-type diffusion well region be located at P type substrate it is interior and
Its upper surface is concordant with P type substrate upper surface, and the p-type diffusion well region, the 2nd area P, the second N-type heavily doped region are all located at N-type
It spreads in well region and its upper surface is all concordant with the N-type diffusion upper surface of well region, the 2nd area P is located at p-type diffusion well region and the 2nd N
Between type heavily doped region, the first p-type heavily doped region, the first N-type heavily doped region are located in p-type diffusion well region and its upper surface
All concordant with p-type diffusion well region upper surface, the second p-type heavily doped region is located at P type substrate interior and its upper surface and P type substrate
Upper surface is concordant, and the third oxide layer is located between p-type diffusion well region and the second N-type heavily doped region and covers N-type diffusion trap
Area, the 2nd area P surface, second oxide layer between the first N-type heavily doped region and third oxide layer and cover p-type expansion
The surface of well region is dissipated, the grid is located at the second oxide layer upper surface, and the source electrode connects the first N-type heavily doped region current potential, institute
Drain electrode the second N-type heavily doped region current potential of connection is stated, the underlayer electrode connects the second p-type heavily doped region current potential, the body area electricity
Pole connects the first p-type heavily doped region current potential.
It is preferred that the depth of the slot is greater than the depth of N-type diffusion well region.
It is preferred that the depth of the slot is greater than 1 μm~3 μm of depth of N-type diffusion well region.In this way can preferably into
Row isolation, reduces substrate leakage, improves the electric field for leaning on source area.
It is preferred that the dosage of the trench bottom injecting p-type impurity is greater than 1012cm-2.It can preferably carry out in this way
Isolation reduces substrate leakage, improves the electric field for leaning on source area.
It is preferred that the shape of the slot is that bar shaped, trapezoidal, inverted trapezoidal, stairstepping are one such or a variety of.
It is preferred that side wall of the slot in LDMOS structure side passes through tiltedly note injection N-type impurity.
It is preferred that each doping type accordingly becomes opposite doping type in the device, i.e. p-type doping becomes
While n-type doping, n-type doping becomes p-type doping.
For achieving the above object, the present invention also provides a kind of manufacturing methods of above-mentioned isolated form LDMOS structure, including
Following steps:
Step 1: using P-type wafer as substrate；
Step 2: forming isolation channel, groove sidewall and bottom oxide；
Step 3: trench bottom injecting p-type impurity；
Step 4: filling slot medium；
Step 5: pre- oxygen, photoetching N-type spread well region window, carry out the injection of N-type diffusion well region, knot, etch extra oxygen
Change layer；
Step 6:LDMOS manufacturing process.
The present invention proposes a kind of isolated form LDMOS knot for LDMOS breakdown voltage and the contradictory relation than conducting resistance
Structure and its manufacturing method.Semiconductor devices of the present invention injects semiconductor identical with substrate material doping type in isolation trench bottom
Impurity solves source surface and shifts to an earlier date breakdown problem, further increases breakdown voltage.Meanwhile slot isolation helps to inhibit LDMOS trap
The horizontal expansion in area reduces device area size.The present invention changes the field distribution close to source, improves drift doping concentration, into
And improve device pressure resistance and reduce than conducting resistance, it has advanced optimized than conducting resistance and breakdown voltage relationship.
The invention has the benefit that
1, a kind of isolated form LDMOS structure of the present invention injects semiconductor identical with substrate doping type in isolation trench bottom
Material, auxiliary drift region exhaust, and reduce the surface field close to source, prevent from puncturing in advance close to source surface, and with tradition
Slot isolation LDMOS structure is compared, and groove depth is more shallow, and process implementing difficulty reduces and cost reduces；
2, a kind of isolation channel of isolated form LDMOS structure of the present invention can inhibit the horizontal expansion of N-type well region, reduce sgare chain
It is very little, meanwhile, N-type well region side is improved close to isolation channel boundary concentration, is promoted by the longitudinal pressure resistance of source area；
3, a kind of isolation channel of isolated form LDMOS structure of the present invention can prevent from mutually going here and there between high voltage integrated circuit device
It disturbs, semiconductor material identical with substrate doping type is injected in bottom reduces substrate leakage.
4, a kind of isolation channel of isolated form LDMOS structure of the present invention can be integrated with the LDMOS of different structure, further excellent
Change breakdown voltage and the relationship than conducting resistance.
5, a kind of isolation channel of isolated form LDMOS structure of the present invention is tiltedly injecting N-type close to LDMOS structure side side wall
Impurity can optimize well region close to slot boundary concentration, improve pressure resistance.
Detailed description of the invention
Fig. 1 is a kind of isolated form LDMOS structure schematic diagram provided by the invention.
Fig. 2 is the process simulation schematic diagram of the embodiment of the present invention.
Fig. 3 (1)~Fig. 3 (6) is a kind of technique of the manufacturing method of isolated form LDMOS structure provided in an embodiment of the present invention
Flow diagram.
Fig. 4 (1)~Fig. 4 (6) is corresponding process simulation figure in Fig. 3 (1)~Fig. 3 (6) device manufacturing processes.
Fig. 5 is the various shape schematic diagram of slot 2.
Fig. 6 is that the side wall of LDMOS structure side passes through the schematic diagram of tiltedly note injection N-type impurity.
Wherein, 1 is the first area P, and 2 be slot, 3 be the first oxide layer, 4 be the 2nd area P, 5 be P type substrate, 6 be N-type diffusion
Well region, 7 be p-type diffusion well region, 8 be the first p-type heavily doped region, 9 be the first N-type heavily doped region, 10 be the second N-type heavy doping
Area, 11 be the second p-type heavily doped region, 12 be the second oxide layer, 13 be grid, 14 be third oxide layer, 15 be source electrode, 16 be leakage
Pole, 17 are underlayer electrode, and 18 be body electrode, and 20 be Xie Zhu N-type impurity area.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
A kind of isolated form LDMOS structure is tied including the isolation moat structure being integrated on same 5 substrate of P type substrate and LDMOS
Structure；The isolation moat structure is located at the P type substrate 5 between the second p-type heavily doped region 11 of LDMOS structure and p-type diffusion well region 7
Inside, isolation moat structure include at least one slot 2, the filled media inside slot 2, the first area P 1 of 2 bottom of slot, 2 edge of slot
First oxide layer 3, first oxide layer 3 are used for the filled media inside isolation channel 2 and the semiconductor silicon material outside slot 2,
2 upper surface of slot is the third oxide layer 14 of LDMOS.
The LDMOS structure is Single-RESURF LDMOS, Double RESURF LDMOS, Triple RESURF
LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, SJ LDMOS are one such.
Preferably, the LDMOS structure include P type substrate 5, N-type diffusion well region 6, p-type diffusion well region 7, the 2nd area P 4,
First p-type heavily doped region 8, the second p-type heavily doped region 11, the first N-type heavily doped region 9, the second N-type heavily doped region 10, the second oxygen
Change layer 12, third oxide layer 14, grid 13, source electrode 15, drain electrode 16, underlayer electrode 17, body electrode 18；The N-type spreads trap
Area 6 is located in P type substrate 5 and its upper surface is concordant with 5 upper surface of P type substrate, and the p-type spreads well region 7, the 2nd area P 4, the
Two N-type heavily doped regions 10 are all located in N-type diffusion well region 6 and its upper surface is all concordant with the N-type diffusion upper surface of well region 6, the
Two areas P 4 are located between p-type diffusion well region 7 and the second N-type heavily doped region 10, the first p-type heavily doped region 8, the first N-type weight
Doped region 9 is located in p-type diffusion well region 7 and its upper surface is all concordant with p-type diffusion 7 upper surface of well region, and second p-type is heavily doped
Miscellaneous area 11 is located in P type substrate 5 and its upper surface is concordant with 5 upper surface of P type substrate, and the third oxide layer 14 is located at p-type expansion
Dissipate between well region 7 and the second N-type heavily doped region 10 and cover the surface of N-type diffusion well region 6, the 2nd area P 4, second oxidation
Layer 12 is between the first N-type heavily doped region 9 and third oxide layer 14 and covers the surface that p-type spreads well region 7, the grid 13
Positioned at 12 upper surface of the second oxide layer, the source electrode 15 connects 9 current potential of the first N-type heavily doped region, 16 the 2nd N of connection of drain electrode
10 current potential of type heavily doped region, the underlayer electrode 17 connect 11 current potential of the second p-type heavily doped region, the connection of body electrode 18 the
One p-type heavily doped region, 8 current potential.
Preferably, the depth of the slot 2 is greater than 1 μm~3 μm of depth of N-type diffusion well region 6.Can preferably carry out in this way every
From reduction substrate leakage improves the electric field for leaning on source area.
The dosage of the 2 bottom injecting p-type impurity of slot is greater than 1012cm-2.It can be preferably isolated in this way, reduce substrate
Electric leakage improves the electric field for leaning on source area.
As shown in figure 5, the shape of the slot 2 is bar shaped, inverted trapezoidal, trapezoidal, stairstepping is one such or a variety of.
Preferably, as shown in fig. 6, side wall of the slot 2 in LDMOS structure side passes through tiltedly note injection N-type impurity, formation
Xie Zhu N-type impurity area 20.
The manufacturing method of above-mentioned isolated form LDMOS structure, comprising the following steps:
Step 1: using P-type wafer as substrate；
Step 2: forming isolation channel, groove sidewall and bottom oxide；
Step 3: trench bottom injecting p-type impurity；Groove sidewall injects N-type impurity and forms Xie Zhu N-type impurity area 20；
Step 4: filling slot medium；
Step 5: pre- oxygen, photoetching N-type spread well region window, carry out the injection of N-type diffusion well region, knot, etch extra oxygen
Change layer；
Step 6:LDMOS manufacturing process.
As mode of texturing, each doping type accordingly becomes opposite doping type in the device, i.e. p-type doping becomes
While n-type doping, n-type doping becomes p-type doping.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed without departing from the spirit and technical ideas disclosed in the present invention
All equivalent modifications or change, should be covered by the claims of the present invention.
Claims (9)
1. a kind of isolated form LDMOS structure, it is characterised in that: including the isolation channel knot being integrated on same P type substrate (5) substrate
Structure and LDMOS structure；
The isolation moat structure is located at the p-type between the second p-type heavily doped region (11) of LDMOS structure and p-type diffusion well region (7)
Substrate (5) is internal, and isolation moat structure includes the first P of the internal filled media of at least one slot (2), slot (2), slot (2) bottom
Area (1), slot (2) edge the first oxide layer (3), first oxide layer (3) filled media internal for isolation channel (2) with
The external semiconductor silicon material of slot (2), slot (2) upper surface are the third oxide layer (14) of LDMOS；
The LDMOS structure includes P type substrate (5), N-type diffusion well region (6), p-type diffusion well region (7), the 2nd area P (4), first
P-type heavily doped region (8), the second p-type heavily doped region (11), the first N-type heavily doped region (9), the second N-type heavily doped region (10),
Dioxide layer (12), third oxide layer (14), grid (13), source electrode (15), drain electrode (16), underlayer electrode (17), body electrode
(18)；N-type diffusion well region (6) is located in P type substrate (5) and its upper surface is concordant with P type substrate (5) upper surface, the P
Type diffusion well region (7), the 2nd area P (4), the second N-type heavily doped region (10) is all located in N-type diffusion well region (6) and its upper surface
All concordant with the N-type diffusion upper surface of well region (6), the 2nd area P (4) is located at p-type diffusion well region (7) and the second N-type heavily doped region
(10) between, the first p-type heavily doped region (8), the first N-type heavily doped region (9) be located at p-type diffusion well region (7) in and thereon
Surface is all concordant with p-type diffusion well region (7) upper surface, and the second p-type heavily doped region (11) is located in P type substrate (5) and it
Upper surface is concordant with P type substrate (5) upper surface, and the third oxide layer (14) is located at p-type diffusion well region (7) and the second N-type weight
Between doped region (10) and the surface of N-type diffusion well region (6), the 2nd area P (4) is covered, second oxide layer (12) is located at the
Between one N-type heavily doped region (9) and third oxide layer (14) and cover the surface that p-type spreads well region (7), grid (13) position
In the second oxide layer (12) upper surface, the source electrode (15) connects first N-type heavily doped region (9) current potential, and the drain electrode (16) is even
Second N-type heavily doped region (10) current potential is connect, the underlayer electrode (17) connects second p-type heavily doped region (11) current potential, the body
Area's electrode (18) connects first p-type heavily doped region (8) current potential.
2. isolated form LDMOS structure according to claim 1, it is characterised in that: the LDMOS structure is Single-
RESURF LDMOS、Double RESURF LDMOS、Triple RESURF LDMOS、Multiple RESURF LDMOS、3D
RESURF LDMOS, SJ LDMOS are one such.
3. isolated form LDMOS structure according to claim 1, it is characterised in that: the depth of the slot (2) expands greater than N-type
Dissipate the depth of well region (6).
4. isolated form LDMOS structure according to claim 3, it is characterised in that: the depth of the slot (2) expands greater than N-type
Dissipate 1 μm~3 μm of depth of well region (6).
5. isolated form LDMOS structure according to claim 1, it is characterised in that: slot (2) bottom injecting p-type impurity
Dosage be greater than 1012cm-2。
6. isolated form LDMOS structure according to claim 1, it is characterised in that: the shape of the slot (2) is bar shaped, ladder
Shape, inverted trapezoidal, stairstepping are one such or a variety of.
7. isolated form LDMOS structure according to claim 1, it is characterised in that: the slot (2) is in LDMOS structure side
Side wall by tiltedly note injection N-type impurity.
8. isolated form LDMOS structure according to claim 1, it is characterised in that: each doping type accordingly becomes opposite
While the doping of doping type, i.e. p-type becomes n-type doping, n-type doping becomes p-type doping.
9. according to claim 1 to the manufacturing method of isolated form LDMOS structure described in 8 any one, it is characterised in that including
Following steps:
Step 1: using P-type wafer as substrate；
Step 2: forming isolation channel, groove sidewall and bottom oxide；
Step 3: trench bottom injecting p-type impurity；
Step 4: filling slot medium；
Step 5: pre- oxygen, photoetching N-type spread well region window, carry out the injection of N-type diffusion well region, knot, etch extra oxide layer；
Step 6:LDMOS manufacturing process.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789769A (en) * | 1995-01-24 | 1998-08-04 | Nec Corporation | Semiconductor device having an improved trench isolation |
| US20110127615A1 (en) * | 2009-12-01 | 2011-06-02 | Mitsuo Tanaka | Semiconductor apparatus and manufacturing method thereof |
| CN102097327A (en) * | 2009-12-02 | 2011-06-15 | 万国半导体股份有限公司 | Dual channel trench LDMOS transistors and BCD process with deep trench isolation |
| JP5570743B2 (en) * | 2009-03-09 | 2014-08-13 | 株式会社東芝 | Semiconductor device |
-
2016
- 2016-11-11 CN CN201610995571.2A patent/CN106449759B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789769A (en) * | 1995-01-24 | 1998-08-04 | Nec Corporation | Semiconductor device having an improved trench isolation |
| JP5570743B2 (en) * | 2009-03-09 | 2014-08-13 | 株式会社東芝 | Semiconductor device |
| US20110127615A1 (en) * | 2009-12-01 | 2011-06-02 | Mitsuo Tanaka | Semiconductor apparatus and manufacturing method thereof |
| CN102097327A (en) * | 2009-12-02 | 2011-06-15 | 万国半导体股份有限公司 | Dual channel trench LDMOS transistors and BCD process with deep trench isolation |
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