CN106409914B - Isolated form LDMOS structure and its manufacturing method - Google Patents
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- CN106409914B CN106409914B CN201611039667.8A CN201611039667A CN106409914B CN 106409914 B CN106409914 B CN 106409914B CN 201611039667 A CN201611039667 A CN 201611039667A CN 106409914 B CN106409914 B CN 106409914B
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- 238000009792 diffusion process Methods 0.000 claims abstract description 30
- 238000000407 epitaxy Methods 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 8
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- 230000015572 biosynthetic process Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The present invention provides a kind of isolated form LDMOS structure and its manufacturing method, including the isolation moat structure being integrated on same P type substrate substrate and LDMOS structure；Isolation moat structure is located in P type substrate and its N-type epitaxy layer of top, between the second p-type heavily doped region of LDMOS structure and the first p-type diffusion well region, isolation moat structure includes at least one slot, the filled media inside slot, the first area P, the first oxide layer, and slot upper surface is the third oxide layer of LDMOS；The present invention passes through in such a way that section substrate injects semiconductor impurities identical with substrate material doping type, so that the isolation trench bottom formed has a p type island region, change the field distribution close to source, improve drift doping concentration, and then conducting resistance is compared in raising device pressure resistance and reduction, it is more excellent the N-type epitaxy layer uniform concentration distribution being epitaxially formed than conducting resistance and breakdown voltage relationship has been advanced optimized.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of isolated form LDMOS structure and its manufacturing method.
Background technique
LDMOS (Lateral Double-Diffused MOSFET) is a kind of common semiconductor devices, has Gao Gong
The advantages that rate gain, high efficiency and low cost, in semiconductor technology using quite extensively.To improve LDMOS breakdown voltage, increase
Big output power generallys use the method for increasing drift region length and reducing drift doping concentration, this will lead to device ratio and leads
The resistance that is powered increases, and increases power consumption.Since RESURF technology and groove isolation technique propose, Single-RESURF LDMOS,
Double RESURF LDMOS、Triple RESURF LDMOS、Multiple RESURF LDMOS、3D RESURF
LDMOS, SJ LDMOS etc., which improve structure, has significant effect than conducting resistance to reduction.However this class formation can not change completely
The kind intracorporal field distribution problem of device, however it remains between device pressure resistance and conducting resistance the problem of contradiction.
Summary of the invention
The present invention proposes a kind of isolated form LDMOS knot for LDMOS breakdown voltage and the contradictory relation than conducting resistance
Structure and its manufacturing method.
For achieving the above object, technical solution of the present invention is as follows:
A kind of isolated form LDMOS structure is tied including the isolation moat structure being integrated on same P type substrate substrate and LDMOS
Structure；The isolation moat structure is located in the N-type epitaxy layer of P type substrate and its top, the second p-type heavily doped region of LDMOS structure
And first between p-type diffusion well region, isolation moat structure includes the first P of at least one slot, the filled media inside slot, trench bottom
Area, groove edge the first oxide layer, first oxide layer is for the filled media inside isolation channel and the semiconductor outside slot
Silicon materials, slot upper surface are the third oxide layer of LDMOS.
It is preferred that the LDMOS structure be Single-RESURF LDMOS, Double RESURF LDMOS,
Triple RESURF LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, SJ LDMOS are one such.
It is preferred that the LDMOS structure includes P type substrate, N-type epitaxy layer, the first p-type diffusion well region, the 2nd P
Type spreads well region, the 2nd area P, the first p-type heavily doped region, the second p-type heavily doped region, the first N-type heavily doped region, the second N-type weight
Doped region, the second oxide layer, third oxide layer, grid, source electrode, drain electrode, underlayer electrode, body electrode；
The N-type epitaxy layer, the second p-type diffusion well region are located at P type substrate top and respectively in the two sides of isolation moat structure,
First p-type diffusion well region, the 2nd area P, the second N-type heavily doped region be all located in N-type epitaxy layer and its upper surface all with N-type
The upper surface of epitaxial layer is concordant, and the 2nd area P is located between p-type diffusion well region and the second N-type heavily doped region, the first p-type weight
Doped region, the first N-type heavily doped region are located in the first p-type diffusion well region and its upper surface is all flat with p-type diffusion well region upper surface
Together；The second p-type heavily doped region is located in the second p-type diffusion well region and its upper surface and the second p-type spread well region upper surface
Concordantly, the third oxide layer is located between the first p-type diffusion well region and the second N-type heavily doped region and covers N-type epitaxy layer, the
The surface in two areas P, second oxide layer is between the first N-type heavily doped region and third oxide layer and covers the expansion of the first p-type
The surface of well region is dissipated, the grid is located at the second oxide layer upper surface, and the source electrode connects the first N-type heavily doped region current potential, institute
Drain electrode the second N-type heavily doped region current potential of connection is stated, the underlayer electrode connects the second p-type heavily doped region current potential, the body area electricity
Pole connects the first p-type heavily doped region current potential.
It is preferred that the depth of the slot is greater than the thickness of N-type epitaxy layer.
It is preferred that the depth of the slot is greater than 1 μm~3 μm of thickness of N-type epitaxy layer.It can preferably carry out in this way
Isolation reduces substrate leakage, improves the electric field for leaning on source area.
It is preferred that the dosage of the trench bottom injecting p-type impurity is greater than 1012cm-2.It can preferably carry out in this way
Isolation reduces substrate leakage, improves the electric field for leaning on source area.
It is preferred that the shape of the slot is that bar shaped, trapezoidal, inverted trapezoidal, stairstepping are one such or a variety of.
It is preferred that the lateral length in the first area P is identical with the lateral length of P type substrate.It can stop extension in this way
Reversed diffusion of the layer to P type substrate.
It is preferred that each doping type accordingly becomes opposite doping type in the device, i.e. p-type doping becomes
While n-type doping, n-type doping becomes p-type doping.
For achieving the above object, the present invention also provides a kind of manufacturing methods of above-mentioned isolated form LDMOS structure, including
Following steps:
Step 1: using P-type wafer as substrate；
Step 2: on substrate portions surface, injecting p-type impurity forms the first area P or the first area P and is forming isolation channel, slot
After side wall and bottom oxide, inject to be formed before filling slot medium；
Step 3: being epitaxially formed N-type epitaxy layer；
Step 4: forming isolation channel, groove sidewall and bottom oxide；
Step 5: filling slot medium；
Step 6:LDMOS manufacturing process.
The present invention proposes a kind of isolated form LDMOS knot for LDMOS breakdown voltage and the contradictory relation than conducting resistance
Structure and its manufacturing method.Making in such a way that section substrate injects semiconductor impurities identical with substrate material doping type
The isolation trench bottom that must be formed has a p type island region, changes the field distribution close to source, improves drift doping concentration, in turn
It improves device pressure resistance and reduces than conducting resistance, advanced optimized than conducting resistance and breakdown voltage relationship.Solve source table
Face shifts to an earlier date breakdown problem, further increases breakdown voltage.Meanwhile the N-type epitaxy layer uniform concentration distribution being epitaxially formed is more excellent.
The invention has the benefit that
1, a kind of isolated form LDMOS structure of the present invention is formed in isolation trench bottom and identical with substrate doping type partly leads
The region of body material type, auxiliary drift region exhaust, and reduce the surface field close to source, prevent from hitting in advance close to source surface
It wears, and compared with LDMOS structure is isolated in traditional slot, groove depth is more shallow, process implementing difficulty reduces and cost reduces；
2, a kind of isolation channel of isolated form LDMOS structure of the present invention can prevent from mutually going here and there between high voltage integrated circuit device
It disturbs, semiconductor material identical with substrate doping type is injected in bottom reduces substrate leakage.
3, a kind of isolation channel of isolated form LDMOS structure of the present invention can be integrated with the LDMOS of different structure, further excellent
Change breakdown voltage and the relationship than conducting resistance.
4, a kind of isolation channel of isolated form LDMOS structure of the present invention is tiltedly injecting N-type close to LDMOS structure side side wall
Impurity can optimize well region close to slot boundary concentration, improve pressure resistance.
Detailed description of the invention
Fig. 1 is a kind of isolated form LDMOS structure schematic diagram provided by the invention.
Fig. 2 is the process simulation schematic diagram of the embodiment of the present invention.
Fig. 3 (1)~Fig. 3 (6) is a kind of technique of the manufacturing method of isolated form LDMOS structure provided in an embodiment of the present invention
Flow diagram.
Fig. 4 (1)~Fig. 4 (6) is corresponding process simulation figure in Fig. 3 (1)~Fig. 3 (6) device manufacturing processes.
Fig. 5 is the various shape schematic diagram of slot 2.
Fig. 6 is that the side wall of LDMOS structure side passes through the schematic diagram of tiltedly note injection N-type impurity.
Wherein, 1 is the first area P, and 2 be slot, 3 be the first oxide layer, 4 be the 2nd area P, 5 be P type substrate, 6 be N-type extension
Layer, 7 for the first p-type spread well region, 8 be the first p-type heavily doped region, 9 be the first N-type heavily doped region, 10 be the second N-type heavy doping
Area, 11 be the second p-type heavily doped region, 12 be the second oxide layer, 13 be grid, 14 be third oxide layer, 15 be source electrode, 16 be leakage
Pole, 17 are underlayer electrode, and 18 spread well region for the second p-type, and 19 be body electrode, and 20 be Xie Zhu N-type impurity area.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
A kind of isolated form LDMOS structure is tied including the isolation moat structure being integrated on same 5 substrate of P type substrate and LDMOS
Structure；The isolation moat structure is located in the N-type epitaxy layer 6 of P type substrate 5 and its top, the second p-type heavy doping of LDMOS structure
Between area 11 and the first p-type diffusion well region 7, isolation moat structure includes at least one slot 2, the filled media inside slot 2,2 bottom of slot
First area P 1 in portion, 2 edge of slot the first oxide layer 3, first oxide layer 3 for inside isolation channel 2 filled media and
Semiconductor silicon material outside slot 2,2 upper surface of slot are the third oxide layer 14 of LDMOS.
The LDMOS structure is Single-RESURF LDMOS, Double RESURF LDMOS, Triple RESURF
LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, SJ LDMOS are one such.
Preferably, the LDMOS structure includes P type substrate 5, N-type epitaxy layer 6, the first p-type diffusion well region 7, the second p-type
Spread well region 18, the 2nd area P 4, the first p-type heavily doped region 8, the second p-type heavily doped region 11, the first N-type heavily doped region 9, the 2nd N
Type heavily doped region 10, the second oxide layer 12, third oxide layer 14, grid 13, source electrode 15, drain electrode 16, underlayer electrode 17, body area electricity
Pole 19；
The N-type epitaxy layer 6, the second p-type diffusion well region 18 are located at 5 top of P type substrate and respectively in isolation moat structures
Two sides, first p-type diffusion well region 7, the 2nd area P 4, the second N-type heavily doped region 10 are all located in N-type epitaxy layer 6 and thereon
Surface is all concordant with the upper surface of N-type epitaxy layer 6, the 2nd area P 4 be located at p-type diffusion well region 7 and the second N-type heavily doped region 10 it
Between, the first p-type heavily doped region 8, the first N-type heavily doped region 9 be located at the first p-type diffusion well region 7 in and its upper surface all with P
It is concordant that type spreads 7 upper surface of well region；The second p-type heavily doped region 11 is located in the second p-type diffusion well region 18 and its upper surface
Concordant with the second p-type diffusion 18 upper surface of well region, the third oxide layer 14 is located at the first p-type diffusion well region 7 and the second N-type weight
Between doped region 10 and the surface of N-type epitaxy layer 6, the 2nd area P 4 is covered, second oxide layer 12 is located at the first N-type heavy doping
Between area 9 and third oxide layer 14 and the surface that the first p-type spreads well region 7 is covered, the grid 13 is located at the second oxide layer 12
Upper surface, the source electrode 15 connect 9 current potential of the first N-type heavily doped region, 16 the second N-type heavily doped region of connection of drain electrode, 10 electricity
Position, the underlayer electrode 17 connect 11 current potential of the second p-type heavily doped region, and the body electrode 19 connects the first p-type heavily doped region 8
Current potential.
Preferably, the depth of the slot 2 is greater than 1 μm~3 μm of thickness of N-type diffusion well region 6.Can preferably carry out in this way every
From reduction substrate leakage improves the electric field for leaning on source area.
The dosage of the 2 bottom injecting p-type impurity of slot is greater than 1012cm-2.It can be preferably isolated in this way, reduce substrate
Electric leakage improves the electric field for leaning on source area.
As shown in figure 5, the shape of the slot 2 is bar shaped, inverted trapezoidal, trapezoidal, stairstepping is one such or a variety of.
Preferably, the lateral length in the first area P 1 is identical with the lateral length of P type substrate 5.Epitaxial layer can be stopped to P in this way
The reversed diffusion of type substrate 5.
Preferably, as shown in fig. 6, side wall of the slot 2 in LDMOS structure side passes through tiltedly note injection N-type impurity, formation
Xie Zhu N-type impurity area 20.
The manufacturing method of above-mentioned isolated form LDMOS structure, comprising the following steps:
Step 1: using P-type wafer as substrate；
Step 2: on substrate portions surface, injecting p-type impurity forms the first area P or the first area P and is forming isolation channel, slot
After side wall and bottom oxide, inject to be formed before filling slot medium；
Step 3: being epitaxially formed N-type epitaxy layer；
Step 4: forming isolation channel, groove sidewall and bottom oxide；
Step 5: filling slot medium；
Step 6:LDMOS manufacturing process.
As mode of texturing, each doping type accordingly becomes opposite doping type in the device, i.e. p-type doping becomes
While n-type doping, n-type doping becomes p-type doping.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed without departing from the spirit and technical ideas disclosed in the present invention
All equivalent modifications or change, should be covered by the claims of the present invention.
Claims (9)
1. a kind of isolated form LDMOS structure, it is characterised in that: including the isolation channel knot being integrated on same P type substrate (5) substrate
Structure and LDMOS structure；
The isolation moat structure is located in the N-type epitaxy layer (6) of P type substrate (5) and its top, the second p-type weight of LDMOS structure
Between doped region (11) and the first p-type diffusion well region (7), isolation moat structure includes at least one slot (2), slot (2) is internal fills out
Filling medium, the first area P (1) of slot (2) bottom, slot (2) edge the first oxide layer (3), first oxide layer (3) be used for every
The external semiconductor silicon material of the filled media and slot (2) internal from slot (2), slot (2) upper surface is the third oxide layer of LDMOS
(14)；
The LDMOS structure includes P type substrate (5), N-type epitaxy layer (6), the first p-type diffusion well region (7), the second p-type diffusion trap
Area (18), the 2nd area P (4), the first p-type heavily doped region (8), the second p-type heavily doped region (11), the first N-type heavily doped region (9),
Second N-type heavily doped region (10), the second oxide layer (12), third oxide layer (14), grid (13), source electrode (15), drain electrode (16),
Underlayer electrode (17), body electrode (19)；
The N-type epitaxy layer (6), the second p-type diffusion well region (18) are located above P type substrate (5) and respectively in isolation moat structure
Two sides, first p-type diffusion well region (7), the 2nd area P (4), the second N-type heavily doped region (10) are all located at N-type epitaxy layer
(6) in and its upper surface is all concordant with the upper surface of N-type epitaxy layer (6), and the 2nd area P (4) is located at p-type and spreads well region (7) and the
Between two N-type heavily doped regions (10), the first p-type heavily doped region (8), the first N-type heavily doped region (9) are located at the expansion of the first p-type
It dissipates in well region (7) and its upper surface is all concordant with p-type diffusion well region (7) upper surface；The second p-type heavily doped region (11) is located at
Second p-type is spread in well region (18) and its upper surface is concordant with the second p-type diffusion well region (18) upper surface, the third oxide layer
(14) it is located between the first p-type diffusion well region (7) and the second N-type heavily doped region (10) and covers N-type epitaxy layer (6), the 2nd area P
(4) surface, second oxide layer (12) is between the first N-type heavily doped region (9) and third oxide layer (14) and covers
First p-type spreads the surface of well region (7), and the grid (13) is located at the second oxide layer (12) upper surface, and the source electrode (15) is even
First N-type heavily doped region (9) current potential is connect, the drain electrode (16) connects second N-type heavily doped region (10) current potential, the underlayer electrode
(17) second p-type heavily doped region (11) current potential is connected, the body electrode (19) connects first p-type heavily doped region (8) current potential.
2. isolated form LDMOS structure according to claim 1, it is characterised in that: the LDMOS structure is Single-
RESURF LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, SJ LDMOS are one such.
3. isolated form LDMOS structure according to claim 1, it is characterised in that: the depth of the slot (2) is greater than outside N-type
Prolong the thickness of layer (6).
4. isolated form LDMOS structure according to claim 3, it is characterised in that: the depth of the slot (2) is greater than outside N-type
1 μm~3 μm of thickness for prolonging layer (6).
5. isolated form LDMOS structure according to claim 1, it is characterised in that: slot (2) bottom injecting p-type impurity
Dosage be greater than 1012cm-2。
6. isolated form LDMOS structure according to claim 1, it is characterised in that: the shape of the slot (2) is bar shaped, ladder
Shape, inverted trapezoidal, stairstepping are one such or a variety of.
7. isolated form LDMOS structure according to claim 1, it is characterised in that: the lateral length and p-type in the first area P (1)
The lateral length of substrate (5) is identical.
8. isolated form LDMOS structure according to claim 1, it is characterised in that: respectively mixed in the isolated form LDMOS structure
Miscellany type accordingly becomes opposite doping type, i.e., while p-type doping becomes n-type doping, n-type doping becomes p-type doping.
9. according to claim 1 to the manufacturing method of isolated form LDMOS structure described in 7 any one, it is characterised in that including
Following steps:
Step 1: using P-type wafer as substrate；
Step 2: on substrate portions surface, injecting p-type impurity forms the first area P or the first area P and is forming isolation channel, groove sidewall
And after bottom oxide, inject to be formed before filling slot medium；
Step 3: being epitaxially formed N-type epitaxy layer；
Step 4: forming isolation channel, groove sidewall and bottom oxide；
Step 5: filling slot medium；
Step 6:LDMOS manufacturing process.
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| JP5570743B2 (en) * | 2009-03-09 | 2014-08-13 | 株式会社東芝 | Semiconductor device |
| CN106024897A (en) * | 2016-07-14 | 2016-10-12 | 电子科技大学 | Three-gate power LDMOS |
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| US5789769A (en) * | 1995-01-24 | 1998-08-04 | Nec Corporation | Semiconductor device having an improved trench isolation |
| US20040046226A1 (en) * | 2002-09-09 | 2004-03-11 | Hiroaki Himi | Semiconductor device and method for manufacturing the same |
| JP5570743B2 (en) * | 2009-03-09 | 2014-08-13 | 株式会社東芝 | Semiconductor device |
| CN106024897A (en) * | 2016-07-14 | 2016-10-12 | 电子科技大学 | Three-gate power LDMOS |
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