CN106409914A - Isolated LDMOS structure and manufacturing method thereof - Google Patents
Isolated LDMOS structure and manufacturing method thereof Download PDFInfo
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- CN106409914A CN106409914A CN201611039667.8A CN201611039667A CN106409914A CN 106409914 A CN106409914 A CN 106409914A CN 201611039667 A CN201611039667 A CN 201611039667A CN 106409914 A CN106409914 A CN 106409914A
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- 238000002955 isolation Methods 0.000 claims description 29
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- 238000000034 method Methods 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
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- 230000008094 contradictory effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention provides an isolated LDMOS structure and manufacturing method thereof. The isolated LDMOS structure includes an isolated slot structure and an LDMOS structure which are integrated on a same P type substrate; the isolated slot structure is located on the P type substrate and an N type epitaxial layer on the P type substrate and between a second P type heavily-doped region and a first P type diffusion well region of the LDMOS structure, the isolated slot structure includes at least one slot, filling media inside the slots, a first P region and a first oxide layer, and an upper surface of the slots is a third oxide layer of the LDMOS. According to the isolated LDMOS structure provided by the invention, semiconductor impurities of the same doping type as a substrate material is injected to part of the substrate, so that the bottoms of the isolated slots that are formed have a P type region, electric field distribution close to a source end is changed, the doping concentration of a drift region is improved, withstand voltage of a device is improved and specific on-resistance is reduced, a relation between the specific on-resistance and breakdown voltage is further optimized, and concentration distribution uniformity of an epitaxially formed N type epitaxial layer is relatively good.
Description
Technical field
The invention belongs to technical field of semiconductors is and in particular to a kind of isolated form LDMOS structure and its manufacture method.
Background technology
LDMOS (Lateral Double-Diffused MOSFET) is a kind of conventional semiconductor devices, has Gao Gong
The advantages of rate gain, high efficiency and low cost, in semiconductor technology using quite extensive.For improving LDMOS breakdown voltage, increase
Big power output, generally using increasing drift region length and the method reducing drift doping concentration, this will lead to device ratio to be led
Energising resistance increases, and increases power consumption.Since RESURF technology and groove isolation technique propose, Single-RESURF LDMOS,
Double RESURF LDMOS、Triple RESURF LDMOS、Multiple RESURF LDMOS、3D RESURF
The improved structures such as LDMOS, SJ LDMOS have significant effect to reducing than conducting resistance.But this class formation can not change completely
Electric Field Distribution problem in kind device body, however it remains the problem of contradiction that device is pressure and conducting resistance between.
Content of the invention
The present invention is directed to LDMOS breakdown voltage with the contradictory relation than conducting resistance it is proposed that a kind of isolated form LDMOS ties
Structure and its manufacture method.
For achieving the above object, technical solution of the present invention is as follows：
A kind of isolated form LDMOS structure, including the isolation moat structure being integrated on same P type substrate substrate and LDMOS knot
Structure；Described isolation moat structure is located in P type substrate and its N-type epitaxy layer of top, the second p-type heavily doped region of LDMOS structure
With first between p-type diffusion well region, isolation moat structure includes filled media within least one groove, groove, a P of trench bottom
Area, the first oxide layer of groove edge, described first oxide layer is used for the filled media within isolation channel and the semiconductor outside groove
Silicon materials, groove upper surface is the 3rd oxide layer of LDMOS.
It is preferred that, described LDMOS structure be Single-RESURF LDMOS, Double RESURF LDMOS,
Triple RESURF LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, SJ LDMOS one kind therein.
It is preferred that, described LDMOS structure includes P type substrate, N-type epitaxy layer, the first p-type diffusion well region, the 2nd P
Type diffusion well region, the 2nd P area, the first p-type heavily doped region, the second p-type heavily doped region, the first N-type heavily doped region, the second N-type weight
Doped region, the second oxide layer, the 3rd oxide layer, grid, source electrode, drain electrode, underlayer electrode, body electrode；
Described N-type epitaxy layer, the second p-type diffusion well region are located above P type substrate and respectively in the both sides of isolation moat structure,
Described first p-type diffusion well region, the 2nd P area, the second N-type heavily doped region be all located in N-type epitaxy layer and its upper surface all with N-type
The upper surface of epitaxial layer is concordant, and the 2nd P area is located between p-type diffusion well region and the second N-type heavily doped region, described first p-type weight
Doped region, the first N-type heavily doped region are located in the first p-type diffusion well region and its upper surface is all put down with p-type diffusion well region upper surface
Together；Described second p-type heavily doped region is located in the second p-type diffusion well region and its upper surface and the second p-type diffusion well region upper surface
Concordantly, described 3rd oxide layer be located between the first p-type diffusion well region and the second N-type heavily doped region and cover N-type epitaxy layer, the
The surface in two P areas, described second oxide layer is located between the first N-type heavily doped region and the 3rd oxide layer and covers the first p-type and expands
The surface of scattered well region, described grid is located at the second oxide layer upper surface, and described source electrode connects the first N-type heavily doped region current potential, institute
State drain electrode and connect the second N-type heavily doped region current potential, described underlayer electrode connects the second p-type heavily doped region current potential, described body area electricity
Pole connects the first p-type heavily doped region current potential.
It is preferred that, the depth of described groove is more than the thickness of N-type epitaxy layer.
It is preferred that, the depth of described groove is more than 1 μm～3 μm of the thickness of N-type epitaxy layer.So can preferably carry out
Isolation, reduces substrate leakage, improves the electric field near source region.
It is preferred that, the dosage of described trench bottom implanting p-type impurity is more than 1012cm-2.So can preferably carry out
Isolation, reduces substrate leakage, improves the electric field near source region.
It is preferred that, the shape of described groove is one or more therein of bar shaped, trapezoidal, inverted trapezoidal, stairstepping.
It is preferred that, the lateral length in a P area is identical with the lateral length of P type substrate.Extension so can be stopped
Layer is to the reverse diffusion of P type substrate.
It is preferred that, in described device, each doping type is accordingly changed into contrary doping type, i.e. p-type doping is changed into
While n-type doping, n-type doping is changed into p-type doping.
For achieving the above object, the present invention also provides a kind of manufacture method of above-mentioned isolated form LDMOS structure, including
Following steps：
Step 1：Using P-type silicon piece as substrate；
Step 2：Form a P area in substrate portions surface implanting p-type impurity, or a P area is forming isolation channel, groove
After side wall and bottom oxide, injection before filling slot medium is formed；
Step 3：It is epitaxially formed N-type epitaxy layer；
Step 4：Form isolation channel, groove sidewall and bottom oxide；
Step 5：Filling slot medium；
Step 6：LDMOS manufacturing process.
The present invention is directed to LDMOS breakdown voltage with the contradictory relation than conducting resistance it is proposed that a kind of isolated form LDMOS ties
Structure and its manufacture method.By way of in section substrate injection with backing material doping type identical semiconductor impurities, make
The isolation trench bottom that must be formed has a p type island region, changes the Electric Field Distribution near source, improves drift doping concentration, and then
Raising device is pressure and reduces ratio conducting resistance, optimizes further than conducting resistance and breakdown voltage relation.Solve source table
Face shifts to an earlier date breakdown problem, improves breakdown voltage further.Meanwhile, the N-type epitaxy layer uniform concentration distribution being epitaxially formed is more excellent.
Beneficial effects of the present invention are：
1st, a kind of isolated form of present invention LDMOS structure is formed with isolation trench bottom and is partly led with substrate doping type identical
The region of body material type, auxiliary drift region exhausts, and reduces the surface field near source, prevents from hitting in advance near source surface
Wear, and compared with traditional slot isolation LDMOS structure, groove depth is more shallow, process implementing difficulty reduces and cost reduces；
2nd, a kind of isolation channel of isolated form of present invention LDMOS structure can prevent from mutually going here and there between high voltage integrated circuit device
Disturb, bottom injection and substrate doping type identical semi-conducting material reduce substrate leakage.
3rd, a kind of isolation channel of isolated form of present invention LDMOS structure can be integrated with the LDMOS of different structure, excellent further
Change breakdown voltage and the relation than conducting resistance.
4th, a kind of isolation channel of isolated form of present invention LDMOS structure is near LDMOS structure side side wall tiltedly injection N-type
Impurity, can optimize well region near groove boundary concentration, improve pressure.
Brief description
A kind of isolated form LDMOS structure schematic diagram that Fig. 1 provides for the present invention.
Fig. 2 is the process simulation schematic diagram of the embodiment of the present invention.
Fig. 3 (1)～Fig. 3 (6) is a kind of technique of the manufacture method of isolated form LDMOS structure provided in an embodiment of the present invention
Schematic flow sheet.
Fig. 4 (1)～Fig. 4 (6) is corresponding process simulation figure in Fig. 3 device manufacturing processes.
Fig. 5 is the variously-shaped schematic diagram of groove 2.
Fig. 6 is that the side wall of LDMOS structure side passes through the schematic diagram that oblique note injects N-type impurity.
Wherein, 1 is a P area, and 2 is groove, and 3 is the first oxide layer, 4 is the 2nd P area, 5 is P type substrate, 6 is N-type extension
Layer, 7 be first p-type diffusion well region, 8 be the first p-type heavily doped region, 9 be the first N-type heavily doped region, 10 be the second N-type heavy doping
Area, 11 be the second p-type heavily doped region, 12 be the second oxide layer, 13 be grid, 14 be the 3rd oxide layer, 15 be source electrode, 16 be leakage
Pole, 17 be underlayer electrode, 18 be second p-type diffusion well region, 19 be body electrode, 20 be Xie Zhu N-type impurity area.
Specific embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by addition different concrete realities
The mode of applying is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without departing from
Carry out various modifications and changes under the spirit of the present invention.
A kind of isolated form LDMOS structure, including the isolation moat structure being integrated on same P type substrate 5 substrate and LDMOS knot
Structure；Described isolation moat structure is located in P type substrate 5 and its N-type epitaxy layer 6 of top, the second p-type heavy doping of LDMOS structure
Between area 11 and the first p-type diffusion well region 7, isolation moat structure includes filled media within least one groove 2, groove 2, groove 2 bottom
The first P area 1 in portion, first oxide layer 3 at groove 2 edge, described first oxide layer 3 be used for the internal filled media of isolation channel 2 and
Semiconductor silicon material outside groove 2, groove 2 upper surface is the 3rd oxide layer 14 of LDMOS.
Described LDMOS structure is Single-RESURF LDMOS, Double RESURF LDMOS, Triple RESURF
LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, SJ LDMOS one kind therein.
Preferably, described LDMOS structure includes P type substrate 5, N-type epitaxy layer 6, the first p-type diffusion well region 7, the second p-type
Diffusion well region 18, the 2nd P area 4, the first p-type heavily doped region 8, the second p-type heavily doped region 11, the first N-type heavily doped region 9, the 2nd N
Type heavily doped region 10, the second oxide layer 12, the 3rd oxide layer 14, grid 13, source electrode 15, drain electrode 16, underlayer electrode 17, body area electricity
Pole 19；
Described N-type epitaxy layer 6, the second p-type diffusion well region 18 are located at P type substrate 5 top and respectively in isolation moat structure
Both sides, described first p-type diffusion well region 7, the 2nd P area 4, the second N-type heavily doped region 10 are all located in N-type epitaxy layer 6 and thereon
Surface is all concordant with the upper surface of N-type epitaxy layer 6, the 2nd P area 4 be located at p-type diffusion well region 7 and the second N-type heavily doped region 10 it
Between, described first p-type heavily doped region 8, the first N-type heavily doped region 9 be located in the first p-type diffusion well region 7 and its upper surface all with P
Type diffusion well region 7 upper surface is concordant；Described second p-type heavily doped region 11 is located in the second p-type diffusion well region 18 and its upper surface
Concordant with the second p-type diffusion well region 18 upper surface, described 3rd oxide layer 14 is located at the first p-type diffusion well region 7 and the second N-type weight
Between doped region 10 and cover N-type epitaxy layer 6, the surface in the 2nd P area 4, described second oxide layer 12 is located at the first N-type heavy doping
Between area 9 and the 3rd oxide layer 14 and cover first p-type spread well region 7 surface, described grid 13 be located at the second oxide layer 12
Upper surface, described source electrode 15 connects the first N-type heavily doped region 9 current potential, and described drain electrode 16 connects the second N-type heavily doped region 10 electricity
Position, described underlayer electrode 17 connects the second p-type heavily doped region 11 current potential, and described body electrode 19 connects the first p-type heavily doped region 8
Current potential.
Preferably, the depth of described groove 2 is more than 1 μm～3 μm of the thickness that N-type spreads well region 6.So can preferably carry out every
From, reduction substrate leakage, improves the electric field near source region.
The dosage of described groove 2 bottom implanting p-type impurity is more than 1012cm-2.So can preferably be isolated, be reduced substrate
Electric leakage, improves the electric field near source region.
As shown in figure 5, the shape of described groove 2 is bar shaped, inverted trapezoidal, one or more therein of trapezoidal, stairstepping.
Preferably, the lateral length in a P area 1 is identical with the lateral length of P type substrate 5.Epitaxial layer so can be stopped to P
The reverse diffusion of type substrate 5.
Preferably, as shown in fig. 6, the side wall in LDMOS structure side for the described groove 2 passes through oblique note injection N-type impurity, formed
Xie Zhu N-type impurity area 20.
The manufacture method of above-mentioned isolated form LDMOS structure, comprises the following steps：
Step 1：Using P-type silicon piece as substrate；
Step 2：Form a P area in substrate portions surface implanting p-type impurity, or a P area is forming isolation channel, groove
After side wall and bottom oxide, injection before filling slot medium is formed；
Step 3：It is epitaxially formed N-type epitaxy layer；
Step 4：Form isolation channel, groove sidewall and bottom oxide；
Step 5：Filling slot medium；
Step 6：LDMOS manufacturing process.
As mode of texturing, in described device, each doping type is accordingly changed into contrary doping type, i.e. p-type doping is changed into
While n-type doping, n-type doping is changed into p-type doping.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed under without departing from disclosed spirit and technological thought
All equivalent modifications or change, must be covered by the claim of the present invention.
Claims (10)
1. a kind of isolated form LDMOS structure it is characterised in that：Including the isolation channel knot being integrated on same P type substrate (5) substrate
Structure and LDMOS structure；
Described isolation moat structure is located in P type substrate (5) and its N-type epitaxy layer (6) of top, the second p-type weight of LDMOS structure
Between doped region (11) and the first p-type diffusion well region (7), isolation moat structure includes at least one groove (2), internal the filling out of groove (2)
Filling medium, a P area (1) of groove (2) bottom, first oxide layer (3) at groove (2) edge, described first oxide layer (3) be used for every
From the internal filled media of groove (2) semiconductor silicon material outside with groove (2), groove (2) upper surface is the 3rd oxide layer of LDMOS
(14).
2. isolated form LDMOS structure according to claim 1 it is characterised in that：Described LDMOS structure is Single-
RESURF LDMOS、Double RESURF LDMOS、Triple RESURF LDMOS、Multiple RESURF LDMOS、3D
RESURF LDMOS, SJ LDMOS one kind therein.
3. isolated form LDMOS structure according to claim 2 it is characterised in that：Described LDMOS structure includes P type substrate
(5), N-type epitaxy layer (6), the first p-type diffusion well region (7), the second p-type diffusion well region (18), the 2nd P area (4), the first p-type weight
Doped region (8), the second p-type heavily doped region (11), the first N-type heavily doped region (9), the second N-type heavily doped region (10), the second oxidation
Layer (12), the 3rd oxide layer (14), grid (13), source electrode (15), drain electrode (16), underlayer electrode (17), body electrode (19)；
Described N-type epitaxy layer (6), the second p-type diffusion well region (18) are located above P type substrate (5) and respectively in isolation moat structure
Both sides, described first p-type diffusion well region (7), the 2nd P area (4), the second N-type heavily doped region (10) are all located at N-type epitaxy layer
(6) in and its upper surface is all concordant with the upper surface of N-type epitaxy layer (6), the 2nd P area (4) is located at p-type and spreads well region (7) and the
Between two N-type heavily doped regions (10), described first p-type heavily doped region (8), the first N-type heavily doped region (9) are located at the first p-type and expand
In scattered well region (7) and its upper surface is all concordant with p-type diffusion well region (7) upper surface；Described second p-type heavily doped region (11) is located at
In second p-type diffusion well region (18) and its upper surface is concordant with the second p-type diffusion well region (18) upper surface, described 3rd oxide layer
(14) it is located between the first p-type diffusion well region (7) and the second N-type heavily doped region (10) and cover N-type epitaxy layer (6), the 2nd P area
(4) surface, described second oxide layer (12) is located between the first N-type heavily doped region (9) and the 3rd oxide layer (14) and covers
First p-type spreads the surface of well region (7), and described grid (13) is located at the second oxide layer (12) upper surface, and described source electrode (15) is even
Connect the first N-type heavily doped region (9) current potential, described drain electrode (16) connects the second N-type heavily doped region (10) current potential, described underlayer electrode
(17) connect the second p-type heavily doped region (11) current potential, described body electrode (19) connects the first p-type heavily doped region (8) current potential.
4. isolated form LDMOS structure according to claim 1 it is characterised in that：The depth of described groove (2) is more than outside N-type
Prolong the thickness of layer (6).
5. isolated form LDMOS structure according to claim 4 it is characterised in that：The depth of described groove (2) is more than outside N-type
Prolong 1 μm～3 μm of the thickness of layer (6).
6. isolated form LDMOS structure according to claim 1 it is characterised in that：Described groove (2) bottom implanting p-type impurity
Dosage be more than 1012cm-2.
7. isolated form LDMOS structure according to claim 1 it is characterised in that：The shape of described groove (2) is bar shaped, ladder
One or more therein of shape, inverted trapezoidal, stairstepping.
8. isolated form LDMOS structure according to claim 1 it is characterised in that：The lateral length in the first P area (1) and p-type
The lateral length of substrate (5) is identical.
9. isolated form LDMOS structure according to claim 1 it is characterised in that：In described device, each doping type is corresponding
It is changed into contrary doping type, while that is, p-type doping is changed into n-type doping, n-type doping is changed into p-type doping.
10. the manufacture method of the isolated form LDMOS structure according to claim 1 to 9 any one is it is characterised in that include
Following steps：
Step 1：Using P-type silicon piece as substrate；
Step 2：Form a P area in substrate portions surface implanting p-type impurity, or a P area is forming isolation channel, groove sidewall
And after bottom oxide, injection before filling slot medium is formed；
Step 3：It is epitaxially formed N-type epitaxy layer；
Step 4：Form isolation channel, groove sidewall and bottom oxide；
Step 5：Filling slot medium；
Step 6：LDMOS manufacturing process.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112510095A (en) * | 2020-12-01 | 2021-03-16 | 无锡先瞳半导体科技有限公司 | Method for producing NLDMOS device and NLDMOS device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789769A (en) * | 1995-01-24 | 1998-08-04 | Nec Corporation | Semiconductor device having an improved trench isolation |
| US20040046226A1 (en) * | 2002-09-09 | 2004-03-11 | Hiroaki Himi | Semiconductor device and method for manufacturing the same |
| JP5570743B2 (en) * | 2009-03-09 | 2014-08-13 | 株式会社東芝 | Semiconductor device |
| CN106024897A (en) * | 2016-07-14 | 2016-10-12 | 电子科技大学 | Three-gate power LDMOS |
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2016
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5789769A (en) * | 1995-01-24 | 1998-08-04 | Nec Corporation | Semiconductor device having an improved trench isolation |
| US20040046226A1 (en) * | 2002-09-09 | 2004-03-11 | Hiroaki Himi | Semiconductor device and method for manufacturing the same |
| JP5570743B2 (en) * | 2009-03-09 | 2014-08-13 | 株式会社東芝 | Semiconductor device |
| CN106024897A (en) * | 2016-07-14 | 2016-10-12 | 电子科技大学 | Three-gate power LDMOS |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112510095A (en) * | 2020-12-01 | 2021-03-16 | 无锡先瞳半导体科技有限公司 | Method for producing NLDMOS device and NLDMOS device |
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| CN106409914B (en) | 2019-08-23 |
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