CN106684136A - SOI (Silicon On Insulator) lateral insulated gate bipolar transistor - Google Patents
SOI (Silicon On Insulator) lateral insulated gate bipolar transistor Download PDFInfo
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- CN106684136A CN106684136A CN201710110260.8A CN201710110260A CN106684136A CN 106684136 A CN106684136 A CN 106684136A CN 201710110260 A CN201710110260 A CN 201710110260A CN 106684136 A CN106684136 A CN 106684136A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 68
- 239000010703 silicon Substances 0.000 title claims abstract description 68
- 239000012212 insulator Substances 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 23
- 229910052760 oxygen Inorganic materials 0.000 claims description 23
- 239000001301 oxygen Substances 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 11
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 210000003850 cellular structure Anatomy 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Abstract
The invention provides an SOI (Silicon On Insulator) lateral insulated gate bipolar transistor. A cellular structure comprises a substrate, a buried oxide layer, a thick medium layer, a thick-silicon-layer N-type drift region, a P well region, a P-type heavily-doped emitter region, an N-type heavily-doped region, an ultrathin top-silicon N-type drift region, an N-type buffer region, a P-type heavily-doped collector region, an emitter contact electrode, a collector contact electrode, a gate oxidation layer, a polycrystalline silicon gate, a P strip and an N strip. According to the SOI lateral insulated gate bipolar transistor provided by the invention, an electric field of a buried layer is enhanced by utilizing the medium-field enhancement theory, so that the longitudinal breakdown voltage of an SOI device is improved; the specific on-state resistance of the device is reduced by adopting the thick-silicon-layer N-type drift region at an emitter region close to a source end, the distribution of the electric field on the surface is adjusted by respectively adopting lateral linear variable doping for the ultrathin top-silicon N-type drift region and the thick-silicon-layer N-type drift region, so that the high breakdown voltage of the device is maintained and simultaneously, the specific on-state resistance is greatly reduced.
Description
Technical field
The invention belongs to semiconductor power device technology field, and in particular to a kind of SOI lateral insulated gate bipolar transistors.
Background technology
Compared to conventional bulk silicon technology, SOI technology has high speed, low-power consumption, high integration, ghost effect is little, isolate
Characteristic is good, latch up effect is little and the advantages of strong capability of resistance to radiation, makes the reliability of integrated circuit and resists soft error ability big
It is big to improve, so as to be increasingly becoming the main flow skill of the integrated circuit of manufacture high speed, low-power consumption, high integration and high reliability
Art.
Lateral insulated gate bipolar transistor (LIGBT：Lateral Insulated Gate Bipolar Transistor)
There is high input impedance, voltage control and low on-resistance, and with being easily integrated that longitudinal device does not have
Advantage.Therefore, lateral insulated gate bipolar transistor increasingly receives publicity and praises highly, rapid all the more so as to develop, using neck
Domain is extensive all the more.However, the relatively low longitudinal direction of lateral high-voltage device is pressure to limit its application in HVIC, according to SOI media
Field strengthens (ENhanced DIelectric layer Field, abbreviation ENDIF) Universal Theory, can be carried using ultra-thin top layer silicon
The longitudinal direction of high SOI device is pressure, but while also results in larger ratio conducting resistance, the phase that device is pressure and conducting resistance between
Mutually restricting relation limits the SOI-LIGBT i.e. further development of SOI lateral insulated gate bipolar transistors.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to propose a kind of high breakdown potential of retainer member
SOI lateral insulated gate bipolar transistor of the device than conducting resistance is reduced while pressure.
For achieving the above object, technical solution of the present invention is as follows：
A kind of SOI lateral insulated gate bipolar transistors, its structure cell includes：Substrate, it is arranged on burying for substrate top surface
Thick dielectric layer, the thick silicon layer N-type drift region of thick dielectric layer left side, thick silicon layer N-type drift region inside above oxygen layer, oxygen buried layer is left
Separate p-type heavy doping emitter region and N-type heavily doped region that the p-well region at end, p-well region inside are arranged；Respectively with
The tangent ultra-thin top layer silicon N-type drift region of thick dielectric layer lower surface and oxygen buried layer upper surface, along the longitudinal direction through being arranged on thickness
P-type heavy doping collector area, the transmitting of p-well region upper surface inside the N-type buffer area of dielectric layer right-hand member, N-type buffer area
Pole contacts electrode, is arranged on the emitter contact electrode of p-type heavy doping emitter region upper surface, is arranged at p-well region upper surface
Gate oxide, the polysilicon gate for being arranged at gate oxide upper surface；Also include P bars, N bars, the N bars are handed in the vertical with P bars
It is the oxygen buried layer and thickness silicon layer N-type drift region, ultra-thin in the thick silicon layer drift region being arranged between p-well region and thick dielectric layer
The lower surface in top layer silicon N-type drift region and N-type buffer area is connected；The thick dielectric layer is positioned close to N-type buffer
The one end in area, its lower surface contacts with the upper surface of ultra-thin top layer silicon N-type drift region, the p-type heavy doping emitter region and N
The upper surface of type heavily doped region contacts electrode and is connected with the emitter stage for being arranged on p-well region upper surface, the left margin and N of gate oxide
The right end portion of type heavily doped region is overlapped, and the right margin of gate oxide extends to the right-hand member of p-well region.
Specifically, in the structure cell, the N bars that are arranged alternately and P bars, order of its arrangement can be exchanged with position.
For example can be N-P-N-P ..., alternatively P-N-P-N ... are arranged.
It is preferred that, the substrate is P-type silicon or for N-type silicon, and soi layer is p-type or for N-type.
It is preferred that, the ultra-thin top layer silicon N-type drift region and thick silicon layer N-type drift region are become by piece-wise linear
The doping way of doping or Uniform Doped or Doping is formed.
It is preferred that, the right-hand member of thick dielectric layer is tangent with N-type buffer area.
Relative distance between the thick dielectric layer and N-type buffer area can be adjusted according to different resistance to pressure requests
It is whole, wherein thick dielectric layer right-hand member can further reduce the high electric field of colelctor electrode with N-type buffer area when tangent, so that device
Stability it is more preferable.
It is preferred that, in the structure cell, the N bars being arranged alternately in thick silicon layer N-type drift region and P bars not with bury
The upper surface of oxygen layer contacts.
It is preferred that, in the structure cell, the N bars that are arranged alternately in thick silicon layer N-type drift region and P bars with bury oxygen
The upper surface of layer contacts.
It is preferred that, in the structure cell, the N bars being arranged alternately in thick silicon layer N-type drift region are located at device with P bars
Part is internal.
It is preferred that, the width of P bars is more than the width of N bars.So allowing for the actual boron row's phosphorus of inhaling of device causes
The assisted depletion of P bars is acted on, therefore can suitably adjust the width of P bars so that P bars are wider than N bars.
It is preferred that, in the structure cell, the upper end difference of emitter stage contact electrode and emitter contact electrode
By first through hole, the second through hole, second layer metal is introduced respectively as source electrode field plate, drain electrode field plate.
Technical scheme is super using part near collector region first in the N-type drift region of SOI LIGBT
Thin top layer silicon N-type drift region, theoretical according to ENDIF when colelctor electrode plus malleation, the side of the critical breakdown electric field by improving silicon
Method strengthens buried regions electric field, so as to improve longitudinal breakdown voltage of SOI device, secondly, for the ultra-thin top layer silicon N-type of drift region is floated
Move area and adopt horizontal linear varying doping, improve the transverse electric field distribution near collector drift region so as to be more evenly distributed, so as to
Improve the lateral breakdown voltage of device；Then thick silicon layer N-type drift region is being adopted near emitter region, for thick silicon layer N-type
Drift region is also adopted by the mode of horizontal linear varying doping and adjusts its surface electric field distribution, while thick silicon layer N-type drift region can be used to
The ratio conducting resistance of device is reduced, and by adding alternate N bars and P bars in thick silicon layer drift region so as in retainer member
While high breakdown voltage, significantly reduce than conducting resistance, there is relatively low conduction loss, be finally reached and effectively reduce
Device area, the purpose for reducing device cost.
Beneficial effects of the present invention are：By the close current collection in the N-type drift region of SOI lateral insulated gate bipolar transistors
Polar region domain adopts part ultra-thin top layer silicon N-type drift region, strengthens theoretical enhancing buried regions electric field using medium field, so as to improve SOI
Longitudinal breakdown voltage of device；Compare electric conduction device is reduced using thick silicon layer N-type drift region near source emitter region
Resistance, secondly, for ultra-thin top layer silicon N-type drift region and thick silicon layer N-type drift region are respectively adopted horizontal linear varying doping, adjusts table
Face Electric Field Distribution so as to while work(device high breakdown voltage is kept, significantly reduces than conducting resistance, further
, add low-resistance conductive channel that device is reduced again than conducting resistance in thick silicon layer N-type drift region, so that device
There is relatively low conduction loss, the purpose for be finally reached and effectively reduce device area, reducing device cost.
Description of the drawings
Fig. 1 is traditional lateral insulated gate bipolar transistor device architecture schematic diagram；
Fig. 2 is a kind of SOI lateral insulated gate bipolar transistors device architecture schematic diagram of the present invention；
Fig. 3 is device architecture schematic diagram of the thick dielectric layer right-hand member with N-type buffer area when tangent in the present invention；
Fig. 4 is that the N bars being arranged alternately in thick silicon layer drift region in the present invention contact with P bars with the upper surface of oxygen buried layer
A kind of exemplary construction schematic diagram；
Fig. 5 is a kind of example that the N bars being arranged alternately in thick silicon layer drift region in the present invention are arranged in device body with P bars
Structural representation；
Fig. 6 is a kind of exemplary construction schematic diagram that P bars are wider than N bars in the present invention；
Fig. 7 is that P bars are with N bars location swap and one kind for not contacting with oxygen buried layer upper surface is shown in structure cell of the present invention
Example structural representation；
Fig. 8 is a kind of example that P bars contact with N bars location swap and with oxygen buried layer upper surface in structure cell of the present invention
Structural representation；
Fig. 9 is that P bars with N bars location swap and are arranged at a kind of exemplary construction in device body and show in structure cell of the present invention
It is intended to；
Figure 10 is that P bars are with N bars location swap and P bars are wider than a kind of exemplary construction signal of N bars in structure cell of the present invention
Figure；
Figure 11 is a kind of exemplary construction schematic diagram without N bars Yu P bars in the present invention；
Figure 12 is that the device architecture in the present invention without N bars and P bars and thick dielectric layer with N-type buffer area when tangent is illustrated
Figure；
Figure 13 is the device cross-section structural representation that Metal field plate is introduced in the present invention；
Figure 14 is a kind of concentration point of SOI lateral insulated gate bipolar transistors drift region piecewise linearity varying doping of the present invention
Butut.
Wherein, 1 is substrate, and 2 is oxygen buried layer, and 3 are thick dielectric layer, and 4 are thick silicon layer N-type drift region, and 5 is emitter stage contact electricity
Pole, 6 is emitter contact electrode, and 7 is polysilicon gate, and 8 is gate oxide, and 9 is first through hole, and 91 is the second through hole, and 10 is layer
Between medium, 11 is p-type heavy doping emitter region, and 12 is p-well region, and 13 is p-type heavy doping collector area, and 14 is P bars, and 41 is N-type
Buffer areas, 42 is N-type heavily doped region, and 43 is ultra-thin top layer silicon N-type drift region, and 44 is N bars, and 51 is source electrode field plate, and 61 are leakage
Pole field plate.
Specific embodiment
Embodiments of the present invention are illustrated below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands easily other advantages and effect of the present invention.The present invention can also pass through concrete realities different in addition
The mode of applying is carried out or applies, the every details in this specification can also based on different viewpoints with application, without departing from
Various modifications and changes are carried out under the spirit of the present invention.
Figure 14 is the concentration distribution of the SOI lateral insulated gate bipolar transistors drift region piecewise linearity varying doping of the present invention
Figure.As can be seen from Figure 14, the linear varying doping change rate of concentration in thick silicon layer drift region 4 linearly becomes less than ultra-thin top layer silicon drift region 43
Doping content rate of change, so as to realize the piece-wise linear varying doping of drift region.
Embodiment 1
As shown in Fig. 2 a kind of SOI lateral insulated gate bipolar transistors, its structure cell includes：Substrate 1, it is arranged on substrate
The oxygen buried layer 2 of 1 upper surface, the thick dielectric layer 3 of the top of oxygen buried layer 2, the thick silicon layer N-type drift region 4 in the thick left side of dielectric layer 3, thick silicon
The separate p-type heavy doping emitter stage that the p-well region 12 of the layer inside left end of N-type drift region 4, the inside of the p-well region 12 are arranged
Area 11 and N-type heavily doped region 42；Ultra-thin top layer silicon N-type drift tangent with the lower surface of thick dielectric layer 3 and the upper surface of oxygen buried layer 2 respectively
Move area 43, along the longitudinal direction through being arranged on the N-type buffer area 41 of the right-hand member of thick dielectric layer 3, the P inside N-type buffer area 41
Type heavy doping collector area 13, the emitter stage of the upper surface of p-well region 12 contact electrode 5, are arranged on p-type heavy doping emitter region 13
The emitter contact electrode 6 on surface, the gate oxide 8 for being arranged at the upper surface of p-well region 12, it is arranged at the upper surface of gate oxide 8
Polysilicon gate 7；Also include P bars 14, N bars 44, the N bars 44 are alternately disposed in the vertical p-well region 12 and thick medium with P bars 14
In thick silicon layer drift region 4 between layer 3, the oxygen buried layer 2 and thick silicon layer N-type drift region 4, ultra-thin top layer silicon N-type drift region 43
And the lower surface in N-type buffer area 41 is connected；The thick dielectric layer 3 is positioned close to the one end in N-type buffer area 41, its
Lower surface contacts with the upper surface of ultra-thin top layer silicon N-type drift region 43, and the p-type heavy doping emitter region 11 and N-type are heavily doped
The upper surface in miscellaneous area 42 contacts electrode 5 and is connected with the emitter stage for being arranged on the upper surface of p-well region 12, the left margin and N of gate oxide 8
The right end portion of type heavily doped region 42 is overlapped, and the right margin of gate oxide 8 extends to the right-hand member of p-well region 12.
In the structure cell, the N bars 44 that are arranged alternately in thick silicon layer N-type drift region 4 and P bars 14 not with oxygen buried layer 2
Upper surface contacts.
It is preferred that, the substrate 1 is P-type silicon or for N-type silicon, and soi layer is p-type or for N-type.
It is preferred that, the ultra-thin top layer silicon N-type drift region 43 and thick silicon layer N-type drift region 4 pass through stagewise line
The doping way of property varying doping or Uniform Doped or Doping is formed.
Embodiment 2
As shown in figure 3, the present embodiment and embodiment 1 are essentially identical, difference is：The right-hand member and N-type of thick dielectric layer 3
Buffer areas 41 are tangent.Relative distance between the thick dielectric layer 3 and N-type buffer area 41 can according to it is different it is pressure will
Ask and be adjusted, wherein the thick right-hand member of dielectric layer 3 can further reduce the high electric field of colelctor electrode with N-type buffer area 41 when tangent,
So that the stability of device is more preferable.
Embodiment 3
As shown in figure 4, the present embodiment and embodiment 1 are essentially identical, difference is：In the structure cell, thick silicon layer N-type
The N bars 44 being arranged alternately in drift region 4 contact with P bars 14 with the upper surface of oxygen buried layer 2.
Embodiment 4
As shown in figure 5, the present embodiment and embodiment 1 are essentially identical, difference is：In the structure cell, thick silicon layer N-type
The N bars 44 being arranged alternately in drift region 4 are located in device body with P bars 14.
Embodiment 5
As shown in fig. 6, the present embodiment and embodiment 1 are essentially identical, difference is：Width of the width of P bars 14 more than N bars 44
Degree.So allow for device actual suction act on the assisted depletion of P bars 14 caused by boron row's phosphorus, therefore can suitably adjust P
The width of bar 14 so that P bars 14 are wider than N bars 44.
Embodiment 6
As shown in fig. 7, the present embodiment and embodiment 1 are essentially identical, difference is：P bars in structure cell in the present embodiment
14 orders being alternately arranged with N bars 44 and location swap.The N bars 44 that are arranged alternately and P bars 14, the order of its arrangement can for N-
P-N-P ..., alternatively P-N-P-N ... are arranged.
Embodiment 7
As shown in figure 8, the present embodiment and embodiment 6 are essentially identical, difference is：Alternately set in thick silicon layer N-type drift region 4
The N bars 44 put contact with P bars 14 with the upper surface of oxygen buried layer 2.
Embodiment 8
As shown in figure 9, the present embodiment and embodiment 6 are essentially identical, difference is：Alternately set in thick silicon layer N-type drift region 4
The N bars 44 put are located in device body with P bars 14.
Embodiment 9
As shown in Figure 10, the present embodiment and embodiment 6 are essentially identical, and difference is：The width of P bars 14 is more than N bars 44
Width.So allow for device actual suction act on the assisted depletion of P bars 14 caused by boron row's phosphorus, therefore can suitably adjust
The width of P bars 14 so that P bars 14 are wider than N bars 44.
Embodiment 10
As shown in figure 11, the present embodiment and embodiment 1 are essentially identical, and difference is：Structure cell is without N bars and P bars.
Embodiment 11
As shown in figure 12, the present embodiment and embodiment 10 are essentially identical, and difference is：The right-hand member and N-type of thick dielectric layer 3
Buffer areas 41 are tangent.Relative distance between the thick dielectric layer 3 and N-type buffer area 41 can according to it is different it is pressure will
Ask and be adjusted, wherein the thick right-hand member of dielectric layer 3 can further reduce the high electric field of colelctor electrode with N-type buffer area 41 when tangent,
So that the stability of device is more preferable.
Embodiment 12
As shown in figure 13, the present embodiment and embodiment 10 are essentially identical, and difference is：In structure cell, emitter stage contact
The upper end of electrode 5 and emitter contact electrode 6 introduces second layer metal and makees respectively respectively by first through hole 9, the second through hole 91
For source electrode field plate 51, drain electrode field plate 61.
The principle and its effect of above-described embodiment only illustrative present invention, it is of the invention not for limiting.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and the scope without prejudice to the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed under without departing from disclosed spirit and technological thought
All equivalent modifications or change, should by the present invention claim be covered.
Claims (9)
1. a kind of SOI lateral insulated gate bipolar transistors, it is characterised in that its structure cell includes：Substrate (1), it is arranged on substrate
(1) the thick silicon layer N-type drift on the left of thick dielectric layer (3) above the oxygen buried layer (2) of upper surface, oxygen buried layer (2), thick dielectric layer (3)
Move area (4), the p-well region (12) of the internal left end of thick silicon layer N-type drift region (4), arrange inside the p-well region (12) it is separate
P-type heavy doping emitter region (11) and N-type heavily doped region (42)；Respectively with thick dielectric layer (3) lower surface and oxygen buried layer (2) on
Ultra-thin top layer silicon N-type drift region (43) of plane tangent, along the longitudinal direction through being arranged on the N-type of thick dielectric layer (3) right-hand member
Buffer areas (41), N-type buffer area (41) internal p-type heavy doping collector area (13), the transmitting of p-well region (12) upper surface
Pole contacts electrode (5), is arranged on the emitter contact electrode (6) of p-type heavy doping emitter region (13) upper surface, is arranged at p-well
The gate oxide (8) of area (12) upper surface, the polysilicon gate (7) for being arranged at gate oxide (8) upper surface；Also include P bars (14),
N bars (44), the N bars (44) and P bars (14) are alternately disposed in the vertical the thickness between p-well region (12) and thick dielectric layer (3)
In silicon layer drift region (4), the oxygen buried layer (2) and thick silicon layer N-type drift region (4), ultra-thin top layer silicon N-type drift region (43) and
The lower surface in N-type buffer area (41) is connected；The thick dielectric layer (3) is positioned close to one end of N-type buffer area (41),
Its lower surface contacts with the upper surface of ultra-thin top layer silicon N-type drift region (43), the p-type heavy doping emitter region (11) and N
The upper surface of type heavily doped region (42) contacts electrode (5) and is connected with the emitter stage for being arranged on p-well region (12) upper surface, gate oxide
(8) left margin is Chong Die with the right end portion of N-type heavily doped region (42), and the right margin of gate oxide (8) extends to p-well region (12)
Right-hand member.
2. a kind of SOI lateral insulated gate bipolar transistors according to claim 1, it is characterised in that：The substrate (1) is
P-type silicon or for N-type silicon, soi layer is p-type or for N-type.
3. a kind of SOI lateral insulated gate bipolar transistors according to claim 1, it is characterised in that：The ultra-thin top layer
Silicon N-type drift region (43) and thick silicon layer N-type drift region (4) are by piece-wise linear varying doping or Uniform Doped or Doping
Doping way is formed.
4. a kind of SOI lateral insulated gate bipolar transistors according to claim 1, it is characterised in that：Thick dielectric layer (3)
Right-hand member is tangent with N-type buffer area (41).
5. a kind of SOI lateral insulated gate bipolar transistors according to claim 1, it is characterised in that：The structure cell
In, the N bars (44) being arranged alternately in thick silicon layer N-type drift region (4) do not contact with P bars (14) with the upper surface of oxygen buried layer (2).
6. a kind of SOI lateral insulated gate bipolar transistors according to claim 1, it is characterised in that：The structure cell
In, the N bars (44) being arranged alternately in thick silicon layer N-type drift region (4) contact with P bars (14) with the upper surface of oxygen buried layer (2).
7. a kind of SOI lateral insulated gate bipolar transistors according to claim 1, it is characterised in that：The structure cell
In, the N bars (44) being arranged alternately in thick silicon layer N-type drift region (4) are with P bars (14) in device body.
8. a kind of SOI lateral insulated gate bipolar transistors according to claim 1, it is characterised in that：The width of P bars (14)
More than the width of N bars (44).
9. a kind of SOI lateral insulated gate bipolar transistors according to claim 1, it is characterised in that：The structure cell
In, the upper end of emitter stage contact electrode (5) and emitter contact electrode (6) passes through respectively first through hole (9), the second through hole
(91) second layer metal, is introduced respectively as source electrode field plate (51), drain electrode field plate (61).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710110260.8A CN106684136A (en) | 2017-02-27 | 2017-02-27 | SOI (Silicon On Insulator) lateral insulated gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710110260.8A CN106684136A (en) | 2017-02-27 | 2017-02-27 | SOI (Silicon On Insulator) lateral insulated gate bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106684136A true CN106684136A (en) | 2017-05-17 |
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| CN201710110260.8A Pending CN106684136A (en) | 2017-02-27 | 2017-02-27 | SOI (Silicon On Insulator) lateral insulated gate bipolar transistor |
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| CN107785415A (en) * | 2017-10-27 | 2018-03-09 | 电子科技大学 | A kind of SOI RC LIGBT devices and preparation method thereof |
| CN110190121A (en) * | 2019-05-29 | 2019-08-30 | 电子科技大学 | Lateral SOI high tension apparatus with prompt dose rate radiation hardened structure |
| CN110473917A (en) * | 2019-08-22 | 2019-11-19 | 电子科技大学 | A kind of transversal I GBT and preparation method thereof |
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| CN107785415B (en) * | 2017-10-27 | 2021-03-16 | 电子科技大学 | SOI-RC-LIGBT device and preparation method thereof |
| CN110190121A (en) * | 2019-05-29 | 2019-08-30 | 电子科技大学 | Lateral SOI high tension apparatus with prompt dose rate radiation hardened structure |
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| CN110473917B (en) * | 2019-08-22 | 2020-09-29 | 电子科技大学 | Transverse IGBT and manufacturing method thereof |
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