CN115832052A - Silicon carbide MOSFET device of intracellular integrated diode and preparation method thereof - Google Patents
Silicon carbide MOSFET device of intracellular integrated diode and preparation method thereof Download PDFInfo
- Publication number
- CN115832052A CN115832052A CN202211475391.3A CN202211475391A CN115832052A CN 115832052 A CN115832052 A CN 115832052A CN 202211475391 A CN202211475391 A CN 202211475391A CN 115832052 A CN115832052 A CN 115832052A
- Authority
- CN
- China
- Prior art keywords
- silicon carbide
- mosfet device
- carbide mosfet
- metal
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a silicon carbide MOSFET device of an intracellular integrated diode and a preparation method thereof, wherein the device comprises: the smooth sculpture recess that the surface setting of substrate was kept away from to carborundum MOSFET device and drift layer, the inside schottky contact metal that is filled of recess, and the lateral wall of sculpture recess is equipped with the ion implantation area, and ohmic contact metal is filled at ion implantation area top. By implementing the invention, the junction barrier Schottky diode is formed in the cell, the area of a chip is saved, the third quadrant characteristic of the device is obviously improved, the low third quadrant starting voltage is realized, and the bipolar degradation effect is avoided; the smooth etched groove structure can avoid electric field concentration, the ion injection can avoid gate breakdown, and meanwhile, under the condition that a current path is not changed, the split gate is wrapped and protected through the junction barrier Schottky diode structure, the electric field of a gate oxide layer is reduced, and the reliability of a device is enhanced.
Description
Technical Field
The invention relates to the technical field of power semiconductor structures, in particular to a silicon carbide MOSFET device of an intracellular integrated diode and a preparation method thereof.
Background
As one of the representatives of the third-generation wide-bandgap semiconductor material, the silicon carbide material has the characteristics of large forbidden band width, high critical breakdown electric field, high thermal conductivity, high electron saturation drift velocity and the like, and has wide application prospect in the fields of high power, high temperature and high frequency power electronics.
Silicon carbide MOSFETs have low switching loss and high switching frequency, are more suitable for high-frequency operation, and have extremely low on-resistance and excellent high-temperature characteristics, and gradually become a mainstream low-loss power device of the next generation. The silicon carbide has a large forbidden band width, and the turn-on voltage of the body diode is very high (2.5 eV at room temperature), so that the loss of the body diode of the silicon carbide MOSFET is large when the body diode is used as a freewheeling diode. Due to the existence of the Basic Plane Dislocation (BPD) of the silicon carbide crystal itself, when the silicon carbide MOSFET works in the third quadrant and the body diode PiN thereof is turned on, the energy released by the long-term electron and hole recombination will cause the stacking fault to spread at the BPD, thereby causing the bipolar degradation effect, causing the bipolar degradation effect of the MOSFET, and bringing a serious challenge to the long-term reliability of the silicon carbide MOSFET.
In the current power device module, an antiparallel silicon carbide Schottky Diode (SBD) is generally used as a freewheeling Diode to ensure that current flows through the silicon carbide Diode when the system is in a dead zone state, thereby avoiding a bipolar degradation effect and improving the reliability of the device. However, the external diode introduces extra parasitic inductance and the packaging area is enlarged by more than one time, which restricts the integration development of the silicon carbide device.
Disclosure of Invention
In view of this, embodiments of the present invention provide a silicon carbide MOSFET device with an intra-cell integrated diode and a method for manufacturing the same, so as to solve the technical problem that the anti-parallel silicon carbide schottky diode in the prior art restricts the integration development of the silicon carbide device.
The technical scheme provided by the embodiment of the invention is as follows:
in a first aspect, an embodiment of the present invention provides a silicon carbide MOSFET device with an integrated diode in a cell, including: the silicon carbide MOSFET device is of a planar gate structure, a smooth etching groove is formed in the surface, far away from the substrate, of the drift layer of the silicon carbide MOSFET device, schottky metal is filled in the etching groove, an ion injection area is arranged on the side wall of the etching groove, and ohmic contact metal is filled at the top of the ion injection area.
Optionally, the etching morphology of the etching groove is an inclined groove or an arc groove, the etching depth of the etching groove is 0.1-0.8 μm, the etching width is 0.2-10 μm, and the etching angle is 10-85 °.
Optionally, the implantation area of the ion implantation area is side implantation of an etched groove, and the implantation morphology is an inclination angle or an arc morphology.
Optionally, a schottky contact is formed between the schottky metal and the drift layer, an ohmic contact is formed between the ion implantation region and the schottky metal, the schottky contact metal and the ohmic contact metal are formed simultaneously or by separate processes, and the schottky contact metal and the ohmic contact metal are the same metal or different metals.
Optionally, the silicon carbide MOSFET device comprises: a drain metal; the upper surface of the drain metal is sequentially provided with a substrate, a buffer layer, a drift layer and a base region in a stacked mode from bottom to top; the upper surface of the base region is provided with a first source region and a second source region in parallel; the upper surface of the first source region is sequentially provided with a gate oxide layer and a polysilicon gate in a stacked mode from bottom to top, and field oxygen is filled around the polysilicon gate; and the source electrode metal is arranged on the upper surfaces of the field oxide, the first source region and the second source region.
Optionally, the thickness of the base region is greater than the thickness of the first source region and the thickness of the second source region, and the doping types of the first source region and the second source region are different.
Optionally, ohmic contacts are formed between the source metal and the first source region and between the source metal and the second source region, and ohmic contacts are formed between the substrate and the drain metal.
Optionally, the first source region and the second source region are both highly doped, and the concentration of the high doping is 1E18cm -3 ～1E20cm -3 The base region is low-doped, and the concentration of the low-doped region is 1E16cm -3 ～8E18cm -3 。
Optionally, the silicon carbide MOSFET devices are N-channel MOSFETs and P-channel MOSFETs.
A second aspect of the embodiments of the present invention provides a method for manufacturing a silicon carbide MOSFET device with an integrated diode in a cell, including: when a planar gate silicon carbide MOSFET device is prepared, a smooth etching groove is formed on the surface, away from a substrate, of a drift layer of the silicon carbide MOSFET device; filling schottky metal in the etching groove; and carrying out ion implantation on the side wall of the etching groove, wherein ohmic contact metal is filled at the top of the ion implantation area.
The technical scheme of the invention has the following advantages:
according to the silicon carbide MOSFET device with the intracellular integrated diode and the preparation method thereof, provided by the embodiment of the invention, the integration of the Schottky diode in the silicon carbide MOSFET device is realized in a mode of forming the etching groove on the surface of the drift layer and filling the Schottky metal in the groove, namely, the junction barrier Schottky diode is formed in a grid splitting mode in the cell, so that the area of a chip is saved, the characteristics of the third quadrant of the device can be obviously improved, the low turn-on voltage of the third quadrant is realized, and the bipolar degradation effect is avoided; meanwhile, under the condition that a current path is not changed, the groove structure is etched, and ion injection is carried out on the edge of the groove, wherein the smooth etched groove structure can avoid electric field concentration, and the ion injection can avoid grid breakdown, so that the device structure realizes the wrapping and protection of a split grid through the junction barrier Schottky diode structure, the electric field of a grid oxide layer is reduced, and the reliability of the device is enhanced. In addition, the device also realizes the integration of the diode in a planar gate structure, and compared with a trench gate structure, the device has a simple process.
According to the silicon carbide MOSFET device of the intracellular integrated diode provided by the embodiment of the invention, the area of a chip is greatly saved through the intracellular integrated diode. When the device works in a reverse blocking state, the ion implantation region with high doping concentration at the split gate can effectively reduce the peak electric field of the device and improve the reliability of the oxide layer of the device by protecting the gate groove while keeping the good blocking characteristic of the device; when the device works in a forward conduction state, the N-type channel region is used as a current path, and the conduction current channel is not influenced by the inclination angle etching treatment; when the device works in the third quadrant, the starting voltage of the integrated SBD is 0.9eV and is far smaller than that of the body diode, the conduction voltage is obviously reduced, and only electrons participate in the conduction when the intracellular integrated diode is started, so that the bipolar degradation effect is avoided, and the characteristics of the third quadrant of the device are effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a structure of a silicon carbide MOSFET device with an intracellularly integrated diode in accordance with an embodiment of the invention;
fig. 2 is a schematic diagram of a silicon carbide MOSFET device with an intracellularly integrated diode according to another embodiment of the invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present invention provides a silicon carbide MOSFET device with an integrated diode in a cell, as shown in fig. 1, including: the silicon carbide MOSFET device adopts a planar gate structure, a smooth etching groove 14 is formed in the surface, far away from the substrate 2, of the drift layer 4 of the silicon carbide MOSFET device, the etching groove 14 is filled with Schottky metal 11, an ion injection area 12 is formed in the side wall of the etching groove, and ohmic contact metal is filled in the top of the ion injection area. Wherein a schottky contact is formed between the schottky metal 11 and the drift layer 4, and an ohmic contact is formed between the ion implantation region 12 and the schottky metal 11. The schottky metal 11 is made of noble metal, such as gold, silver, aluminum, platinum, and the like. The Schottky contact metal and the ohmic contact metal are formed simultaneously or by adopting a separate process, and the Schottky contact metal and the ohmic contact metal are the same metal or different metals.
According to the silicon carbide MOSFET device of the intracellular integrated diode, provided by the embodiment of the invention, the integration of the Schottky diode in the silicon carbide MOSFET device is realized in a mode that the etching groove is formed on the surface of the drift layer and the Schottky metal is filled in the groove, namely, the junction barrier Schottky diode is formed in a mode that the gate is cracked in the cell, the area of a chip is saved, the characteristics of the third quadrant of the device can be obviously improved, the low third quadrant starting voltage is realized, and the bipolar degradation effect is avoided; meanwhile, under the condition that a current path is not changed, the groove structure is etched, and ion injection is carried out on the edge of the groove, wherein the electric field concentration can be avoided through the smooth etched groove structure, and the grid breakdown can be avoided through the ion injection, so that the device structure realizes the wrapping and protection of the split grid through the junction barrier Schottky diode structure, the electric field of a grid oxide layer is reduced, and the reliability of the device is enhanced. In addition, the device also realizes the integration of the diode in a planar gate structure, and compared with a trench gate structure, the device has a simple process.
In an embodiment, the etching morphology of the etching groove is an inclination angle groove or an arc groove, the etching depth of the etching groove is 0.1 μm to 0.8 μm, the etching width is 0.2 μm to 10 μm, the etching angle is 10 degrees to 85 degrees, the implantation area of the ion implantation area is the side implantation of the etching groove, and the implantation morphology is an inclination angle or an arc morphology. Specifically, since the hardness of the silicon carbide material is high, and the trench with a large etching depth is difficult, the process difficulty can be reduced by adopting the etching depth, the etching width and the etching angle, and the performance of the integrated diode is not influenced.
In one embodiment, as shown in fig. 1, the silicon carbide MOSFET device includes: a drain metal 1; the substrate 2, the buffer layer 3, the drift layer 4 and the base region 5 are sequentially stacked on the upper surface of the drain metal 1 from bottom to top; a first source region 6 and a second source region 13 which are arranged in parallel on the upper surface of the base region 5; the upper surface of the first source region 6 is sequentially provided with a gate oxide layer 7 and a polysilicon gate 8 in a stacked mode from bottom to top, and field oxide 9 is filled around the polysilicon gate 8; and the source metal 10 is arranged on the upper surfaces of the field oxide 9, the first source region 6 and the second source region 13. The gate oxide layer 7 is formed by using materials such as Si02, alN and K media.
Specifically, the silicon carbide MOSFET devices are N-channel MOSFETs and P-channel MOSFETs. For example, when the silicon carbide MOSFET device is an N-channel MOSFET, as shown in fig. 2, in the structure, the substrate 2 specifically adopts a SiC substrate, the buffer layer 3 adopts an N + buffer layer, the drift layer 4 adopts an N-drift layer, the base region 5 adopts a P-type base region, the first source region 6 adopts an N + source region, the second source region 13 adopts a P + source region, and the ion implantation region 12 in the etched groove is a P + ion implantation region. Wherein the N + source region is highly doped with a doping concentration of 1E18cm -3 ～1E20 cm -3 (ii) a The P + source region is highly doped with a doping concentration of 1E17cm -3 ～1E20 cm -3 (ii) a The P-type base region is low doped and has a doping concentration of 1E16cm -3 ～8E18 cm -3 . The first source region, the second source region, the base region and the ion implantation region can be formed in an ion implantation mode. Because the ion implantation area and the second source area are both doped with P +, the ion implantation area and the second source area can be formed by adopting the same step process, thereby simplifying the preparation method of the ion implantation area and the second source area.
When the silicon carbide MOSFET device is a P-channel MOSFET, the doping types of the substrate, the buffer layer, the drift region, the first source region, the second source region, the base region and the ion implantation region are converted from a P type to an N type or from an N type to a P type, namely the doping types of all layers in the P-channel MOSFET and the N-channel MOSFET are different. The preparation methods of the first source region, the second source region, the base region and the ion implantation region in the P-channel MOSFET are the same as those in the N-channel MOSFET, and are not described herein again.
In one embodiment, the base region has a thickness greater than a thickness of each of the first and second source regions. Ohmic contacts are formed between the source metal and the first source region and between the source metal and the second source region, and ohmic contacts are formed between the substrate and the drain metal.
According to the silicon carbide MOSFET device of the intracellular integrated diode provided by the embodiment of the invention, the area of a chip is greatly saved through the intracellular integrated diode. When the device works in a reverse blocking state, the ion implantation region with high doping concentration at the split gate can effectively reduce the peak electric field of the device and improve the reliability of the oxide layer of the device by protecting the gate groove while keeping the good blocking characteristic of the device; when the device works in a forward conduction state, the N-type channel region is used as a current path, and the conduction current channel is not influenced by the inclination angle etching treatment; when the device works in the third quadrant, the starting voltage of the integrated SBD is 0.9eV and is far smaller than that of the body diode, the conduction voltage is obviously reduced, and only electrons participate in the conduction when the intracellular integrated diode is started, so that the bipolar degradation effect is avoided, and the characteristics of the third quadrant of the device are effectively improved.
The embodiment of the invention also provides a preparation method of the silicon carbide MOSFET device of the intracellular integrated diode, which comprises the following steps: when a planar gate silicon carbide MOSFET device is prepared, an etching groove is formed on the surface, away from a substrate, of a drift layer of the silicon carbide MOSFET device, and the etching appearance of the etching groove is an inclined angle groove or an arc groove; filling schottky metal in the etching groove; and carrying out ion implantation on the side wall of the etching groove, wherein ohmic contact metal is filled at the top of the ion implantation area.
According to the silicon carbide MOSFET device of the intracellular integrated diode, provided by the embodiment of the invention, the integration of the Schottky diode in the silicon carbide MOSFET device is realized in a mode that the etching groove is formed on the surface of the drift layer and the Schottky metal is filled in the groove, namely, the junction barrier Schottky diode is formed in a mode that the gate is cracked in the cell, the area of a chip is saved, the characteristics of the third quadrant of the device can be obviously improved, the low third quadrant starting voltage is realized, and the bipolar degradation effect is avoided; meanwhile, under the condition that a current path is not changed, the groove structure is etched, and ion injection is carried out on the edge of the groove, wherein the electric field concentration can be avoided through the smooth etched groove structure, and the grid breakdown can be avoided through the ion injection, so that the device structure realizes the wrapping and protection of the split grid through the junction barrier Schottky diode structure, the electric field of a grid oxide layer is reduced, and the reliability of the device is enhanced. In addition, the device also realizes the integration of the diode in a plane gate structure, and compared with a trench gate structure, the device has a simple process.
In one embodiment, when the prepared planar gate silicon carbide MOSFET device is an N-channel MOSFET, the preparation method of the device is realized by adopting the following steps:
s1: and sequentially forming a stacked N + buffer layer and an N-drift layer on the silicon carbide substrate by adopting an epitaxial process.
S2: and cleaning the epitaxial wafer and testing the defects of the epitaxial wafer.
S3: and after the test is passed, making a photoetching mark and etching a groove on the upper surface of the N-drift layer far away from the N + buffer layer by etching, wherein the etching groove is formed in the middle of the upper surface of the N-drift layer.
S4: forming a P-type base region: and depositing an injection mask layer on the upper surface of the N-drift layer, which is far away from the N + buffer layer, photoetching to obtain a P-type base region injection pattern, and performing P-type ion injection, wherein the formed P-type base region is outside the etching groove and is not in contact with the etching groove.
S5: forming an N + source region: and depositing a mask layer on the upper surface of the P-type base region far away from the N & lt- & gt drift layer, and obtaining an N & lt + & gt source region injection pattern through photoetching to perform ion injection.
S6: forming a P + source region and a P + ion implantation region: depositing a mask layer on the upper surface of the P-type base region, which is far away from the N-drift layer, and the side wall of the etching groove, obtaining a P + source region and a P + ion implantation region implantation pattern through photoetching, and performing ion implantation; the P + source region is positioned outside the N + source region, the P + ion implantation region is positioned on the side wall of the etching groove, and the implantation morphology is an inclination angle or an arc morphology.
S7: then annealing treatment and sacrificial oxidation treatment are carried out, and the growth of a gate oxide layer is carried out on the upper surface of the P-type base region away from the N-drift layer; the formed gate oxide layer is contacted with the N + source region, wherein the surface appearance after etching and the electrical characteristics of the Schottky contact can be improved through sacrificial oxidation treatment, and the performance of the device is improved.
S8: and depositing polysilicon on the upper surface of the gate oxide layer, which is far away from the N-drift layer, so as to form a polysilicon gate structure.
S9: and depositing a Schottky metal in the etching groove, forming Schottky contact between the Schottky metal and the N-drift layer, and forming ohmic contact between the Schottky metal and the P + ion injection region.
S10: and forming field oxygen on the upper surface of the polysilicon gate, which is far away from the gate oxide layer, wherein the formed field oxygen covers the polysilicon gate, the gate oxide layer and the N-drift layer, and simultaneously the field oxygen is contacted with the N + source region. The formed field oxygen can realize isolation and prevent the appearance of parasitic tubes.
S10: depositing source metal on the upper surface of the field oxide layer far away from the N-drift layer to form a source electrode; depositing drain metal on the lower surface of the substrate far away from the N + buffer layer to form a drain electrode; wherein the formed source electrode is in contact with the N + source region and the P + source region.
S11: thickening the formed metal electrode, and carrying out passivation treatment and metal opening.
Although the present invention has been described in detail with respect to the exemplary embodiments and the advantages thereof, those skilled in the art will appreciate that various changes, substitutions and alterations can be made to the embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while maintaining the scope of the present invention.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (10)
1. A silicon carbide MOSFET device with an integrated diode in a cell, comprising: the silicon carbide MOSFET device is of a planar gate structure, a smooth etching groove is formed in the surface, far away from the substrate, of the drift layer of the silicon carbide MOSFET device, schottky metal is filled in the etching groove, an ion injection area is arranged on the side wall of the etching groove, and ohmic contact metal is filled at the top of the ion injection area.
2. The silicon carbide MOSFET device of claim 1, wherein the etched trench is a dip trench or a circular arc trench, the etched trench has an etched depth of 0.1 μm to 0.8 μm, an etched width of 0.2 μm to 10 μm, and an etched angle of 10 ° to 85 °.
3. The silicon carbide MOSFET device with integrated diode in cell as claimed in claim 1, wherein the implantation region of the ion implantation region is a side implantation of an etched groove, and the implantation profile is an inclination angle or a circular arc profile.
4. The silicon carbide MOSFET device of claim 1, wherein a schottky contact is formed between the schottky metal and the drift layer, an ohmic contact is formed between the ion-implanted region and the schottky metal, the schottky contact metal and the ohmic contact metal are formed simultaneously or in separate processes, and the schottky contact metal and the ohmic contact metal are the same metal or different metals.
5. The intracellular diode integrated silicon carbide MOSFET device of claim 1, wherein the silicon carbide MOSFET device comprises:
a drain metal;
the upper surface of the drain metal is sequentially laminated with the substrate, the buffer layer, the drift layer and the base region from bottom to top;
the upper surface of the base region is provided with a first source region and a second source region in parallel;
the upper surface of the first source region is sequentially provided with a gate oxide layer and a polysilicon gate in a stacked mode from bottom to top, and field oxygen is filled around the polysilicon gate;
and the source electrode metal is arranged on the upper surfaces of the field oxide, the first source region and the second source region.
6. The silicon carbide MOSFET device of claim 5, wherein the base region has a thickness greater than a thickness of the first and second source regions, respectively, and wherein the first and second source regions have different doping types.
7. The intracellular diode integrated silicon carbide MOSFET device of claim 5, wherein ohmic contacts are formed between the source metal and the first source region and between the source metal and the second source region, and ohmic contacts are formed between the substrate and the drain metal.
8. The silicon carbide MOSFET device with integrated intracellular diode of claim 5, wherein the first source region and the second source region are both highly doped with a concentration of 1E18cm -3 ～1E20cm -3 The base region is low-doped, and the concentration of the low-doped region is 1E16cm -3 ～8E18cm -3 。
9. The intracellular diode integrated silicon carbide MOSFET device of claim 5, wherein the silicon carbide MOSFET device is an N-channel MOSFET and a P-channel MOSFET.
10. A method for manufacturing a silicon carbide MOSFET device of an intracellular integrated diode is characterized by comprising the following steps:
when a planar gate silicon carbide MOSFET device is prepared, a smooth etched groove is formed on the surface, away from a substrate, of a drift layer of the silicon carbide MOSFET device;
filling schottky metal in the etching groove;
and carrying out ion implantation on the side wall of the etching groove, wherein ohmic contact metal is filled at the top of the ion implantation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211475391.3A CN115832052A (en) | 2022-11-23 | 2022-11-23 | Silicon carbide MOSFET device of intracellular integrated diode and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211475391.3A CN115832052A (en) | 2022-11-23 | 2022-11-23 | Silicon carbide MOSFET device of intracellular integrated diode and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115832052A true CN115832052A (en) | 2023-03-21 |
Family
ID=85530736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211475391.3A Pending CN115832052A (en) | 2022-11-23 | 2022-11-23 | Silicon carbide MOSFET device of intracellular integrated diode and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115832052A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116344593A (en) * | 2023-05-29 | 2023-06-27 | 深圳市威兆半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN117497601A (en) * | 2023-12-28 | 2024-02-02 | 深圳天狼芯半导体有限公司 | Structure, manufacturing method and electronic equipment of planar silicon carbide transistor |
-
2022
- 2022-11-23 CN CN202211475391.3A patent/CN115832052A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116344593A (en) * | 2023-05-29 | 2023-06-27 | 深圳市威兆半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN116344593B (en) * | 2023-05-29 | 2023-08-22 | 深圳市威兆半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN117497601A (en) * | 2023-12-28 | 2024-02-02 | 深圳天狼芯半导体有限公司 | Structure, manufacturing method and electronic equipment of planar silicon carbide transistor |
| CN117497601B (en) * | 2023-12-28 | 2024-05-07 | 深圳天狼芯半导体有限公司 | Structure, manufacturing method and electronic equipment of planar silicon carbide transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5617175B2 (en) | Wide band gap semiconductor device and manufacturing method thereof | |
| US10347735B2 (en) | Semiconductor device with lifetime killers and method of manufacturing the same | |
| US9627486B2 (en) | Semiconductor device | |
| JP6766889B2 (en) | Semiconductor devices and methods for manufacturing semiconductor devices | |
| US9362392B2 (en) | Vertical high-voltage semiconductor device and fabrication method thereof | |
| KR101396611B1 (en) | Semiconductor device | |
| JP6074787B2 (en) | Silicon carbide semiconductor device and manufacturing method thereof | |
| CN115832052A (en) | Silicon carbide MOSFET device of intracellular integrated diode and preparation method thereof | |
| TW201242034A (en) | New approach to integrate schottky in MOSFET | |
| JP2010206002A (en) | P-channel silicon carbide mosfet | |
| JP5358926B2 (en) | Silicon carbide trench MOS type semiconductor device | |
| CN213459736U (en) | SiC IGBT device | |
| JPWO2015019797A1 (en) | High voltage semiconductor device and manufacturing method thereof | |
| JP2019102554A (en) | Semiconductor device | |
| JPWO2013147276A1 (en) | Vertical high voltage semiconductor device and method for manufacturing vertical high voltage semiconductor device | |
| WO2013146329A1 (en) | High-voltage-resistant semiconductor | |
| JP2010258327A (en) | Vertical gallium nitride semiconductor device having reverse withstand voltage | |
| JP5402220B2 (en) | Silicon carbide semiconductor device manufacturing method and silicon carbide semiconductor device | |
| JP7310184B2 (en) | Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device | |
| JP2022060802A (en) | Silicon carbide semiconductor device | |
| JP2018082056A (en) | Semiconductor device and method of manufacturing the same | |
| JP2012238887A (en) | Manufacturing method of trench mos type silicon carbide semiconductor device | |
| JP7074173B2 (en) | Semiconductor devices and methods for manufacturing semiconductor devices | |
| KR101463078B1 (en) | Schottky barrier diode and fabricating method thereof | |
| JP6953876B2 (en) | Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |