JP6074787B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Silicon carbide semiconductor device and manufacturing method thereof Download PDF

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JP6074787B2
JP6074787B2 JP2012120263A JP2012120263A JP6074787B2 JP 6074787 B2 JP6074787 B2 JP 6074787B2 JP 2012120263 A JP2012120263 A JP 2012120263A JP 2012120263 A JP2012120263 A JP 2012120263A JP 6074787 B2 JP6074787 B2 JP 6074787B2
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敦之 田中
敦之 田中
憲幸 岩室
憲幸 岩室
原田　信介
信介 原田
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Fuji Electric Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
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Description

本発明は、ワイドバンドギャップ材料のひとつである炭化珪素を半導体として用い高耐圧大電流を制御する炭化珪素半導体装置およびその製造方法に関する。   The present invention relates to a silicon carbide semiconductor device that uses silicon carbide, which is one of wide band gap materials, as a semiconductor to control a high breakdown voltage and large current and a method for manufacturing the same.

高耐圧、大電流を制御するパワー半導体素子の材料として、従来はシリコン（Ｓｉ）単結晶が用いられていた。パワー半導体素子はいくつかの種類があり、用途に合わせてそれらが使い分けられている。例えば、バイポーラトランジスタやＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）は、電流密度は多く取れるものの高速でのスイッチングができず、バイポーラトランジスタでは、数ｋＨｚ、ＩＧＢＴでは２０ｋＨｚ程度の周波数がその使用限界である。一方、パワーＭＯＳＦＥＴは、大電流は取れないものの、数ＭＨｚと高速に使用できる。しかしながら、市場では大電流と高速性を兼ね備えたパワーデバイスへの要求が強く、ＩＧＢＴやパワーＭＯＳＦＥＴの改良に力が注がれてきており、現在では、ほぼ材料限界に近いところまで開発が進んできた。   Conventionally, a silicon (Si) single crystal has been used as a material of a power semiconductor element that controls a high breakdown voltage and a large current. There are several types of power semiconductor elements, and they are properly used according to the application. For example, although bipolar transistors and IGBTs (insulated gate bipolar transistors) have a high current density, they cannot be switched at a high speed, and the use limit is a frequency of several kHz for bipolar transistors and 20 kHz for IGBTs. On the other hand, a power MOSFET cannot be used with a large current, but can be used at a high speed of several MHz. However, there is a strong demand for power devices that have both high current and high speed in the market, and efforts are being made to improve IGBTs and power MOSFETs. At present, development has progressed almost to the limit of materials. It was.

図１２は、一般的なＭＯＳＦＥＴの断面図である。ｎ+基板１０１上にｎ-ドリフト層１０２を積層形成し、このｎ-ドリフト層１０２上に、ｐベース層１０３を形成し、このｐベース層１０３の表面層に選択的にｎ+ソース層１０４を形成している。そして、ｎ-ドリフト層１０２と、ｐベース層１０３、ならびにｎ+ソース層１０４の上に、ゲート絶縁膜１０６を介してゲート電極１０７が形成されている。 FIG. 12 is a cross-sectional view of a general MOSFET. An n − drift layer 102 is stacked on the n + substrate 101, a p base layer 103 is formed on the n − drift layer 102, and an n + source layer 104 is selectively formed on the surface layer of the p base layer 103. Is forming. A gate electrode 107 is formed on the n − drift layer 102, the p base layer 103, and the n + source layer 104 with a gate insulating film 106 interposed therebetween.

さらに、近年では超接合型ＭＯＳＦＥＴが注目を浴びている。図１３〜１５に代表的な素子の断面構造を示す。超接合型ＭＯＳＦＥＴは、例えば下記非特許文献１が開示され、ＣｏｏｌＭＯＳＦＥＴとして下記非特許文献２が開示されている。これらの技術では、ｎ-ドリフト層に縦方向にｐ層１１０を柱状構造に形成することで、ソース・ドレイン間の耐圧特性を劣化させることなく、オン抵抗を格段に向上できる。 In recent years, super-junction MOSFETs have attracted attention. 13 to 15 show typical element cross-sectional structures. For example, the following non-patent document 1 is disclosed as a super junction type MOSFET, and the following non-patent document 2 is disclosed as a cool MOSFET. In these techniques, by forming the p layer 110 in the columnar structure in the vertical direction in the n − drift layer, the on-resistance can be remarkably improved without deteriorating the breakdown voltage characteristics between the source and the drain.

また、パワー半導体素子の観点からの材料検討も行われ、下記非特許文献３に開示されているように、炭化珪素（ＳｉＣ）が次世代のパワー半導体素子として、低オン電圧、高速・高温特性に優れた素子として最近注目を集めている。このＳｉＣは、化学的に非常に安定な材料であり、バンドギャップが３ｅＶと広く、高温でも半導体として極めて安定的に使用できる。また、最大電界強度もシリコンより１桁以上大きい。ＳｉＣは、シリコンにおける材料限界を超える可能性が大きいことから、パワー半導体用途、例えば、ＭＯＳＦＥＴのおける今後の伸長が大きく期待される。そして、そのオン抵抗が小さいことにより、高耐圧特性を維持したまま、より一層の低オン抵抗を有する縦型ＳｉＣ−ＭＯＳＦＥＴが期待されている。   In addition, materials have been studied from the viewpoint of power semiconductor elements, and as disclosed in Non-Patent Document 3 below, silicon carbide (SiC) is a next-generation power semiconductor element that has low on-voltage, high-speed and high-temperature characteristics. Recently, it has attracted attention as an excellent device. This SiC is a chemically very stable material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Also, the maximum electric field strength is one digit or more larger than that of silicon. Since SiC is likely to exceed the material limit in silicon, future growth in power semiconductor applications such as MOSFETs is greatly expected. And since the on-resistance is small, a vertical SiC-MOSFET having a further low on-resistance while maintaining high withstand voltage characteristics is expected.

一般的なＳｉＣ−ＭＯＳＦＥＴの断面構造についても、シリコンと同様（図１２）に示すものである。ｎ-ドリフト層１０２の上に積層されたｐベース層１０３の表面層に、選択的にｎ+ソース層１０４を形成し、ｎ-ドリフト層１０２とｐベース層１０３、ならびにｎ+ソース層１０４の上に、ゲート絶縁膜１０６を介してゲート電極１０７が形成されて、基板１０１の裏面にドレイン電極１０８が形成される。 The cross-sectional structure of a general SiC-MOSFET is also the same as that of silicon (FIG. 12). the n - surface layer of the p base layer 103 which is stacked on the drift layer 102, to form a selectively n + source layer 104, n - drift layer 102 and the p base layer 103 and n + source layer 104, A gate electrode 107 is formed thereon via a gate insulating film 106, and a drain electrode 108 is formed on the back surface of the substrate 101.

このように形成されたＳｉＣ−ＭＯＳＦＥＴは、スイッチングデバイスとして、低オン抵抗で高速スイッチングが可能な素子である。例えば、モータコントロール用インバータや無停電電源装置（ＵＰＳ）などの電力変換装置に活用されることが期待されている。ＳｉＣは、ワイドバンドギャップ半導体材料であるために、上述したように、破壊電界強度がシリコンの約１０倍と高く、オン抵抗が十分小さくなることが期待される。   The SiC-MOSFET formed in this way is an element capable of high-speed switching with a low on-resistance as a switching device. For example, it is expected to be used in power conversion devices such as an inverter for motor control and an uninterruptible power supply (UPS). Since SiC is a wide band gap semiconductor material, as described above, the breakdown electric field strength is about 10 times higher than that of silicon, and the on-resistance is expected to be sufficiently small.

また、さらなる低オン抵抗化についての施策について、有効素子面積を広げる上でゲートパッド下の領域にも素子構造を作り込む方法が開示されている（例えば、下記特許文献１〜５参照。）。   As a measure for further lowering the on-resistance, a method is disclosed in which an element structure is also formed in a region under a gate pad in order to increase the effective element area (see, for example, Patent Documents 1 to 5 below).

特開２０１０−１７７４５４号公報JP 2010-177454 A 特開２０１０−８７１２６号公報JP 2010-87126 A 特開２００９−１０５１７７号公報JP 2009-105177 A 特開平８−１０２４９５号公報JP-A-8-102495 特開平４−２３９１３７号公報JP-A-4-239137

Ｆｕｊｉｈｉｒａ ｅｔ ａｌ，ＪＪＡＰ ｖｏｌ．３６ ｐａｒｔ１ ｎｏ．１０，ｐｐ．６２５４，１９９７Fujihira et al, JJ vol vol. 36 part1 no. 10, pp. 6254, 1997 Ｄｅｂｏｙ ｅｔ ａｌ，ＩＥＥＥ ＩＥＤＭ １９９８，ｐｐ．６８３Deboy et al, IEEE IEDM 1998, pp. 683 ＩＥＥＥ Ｔｒａｎｓａｃｔｉｏｎ ｏｎ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅｓ Ｖｏｌ．３６，ｐ．１８１１，１９８９IEEE Transaction on Electron Devices Vol. 36, p. 1811, 1989

しかしながら、ＳｉＣは、半導体の破壊電界強度がシリコン素子に比べて１０倍高くなることから、特に、高電圧印加時の酸化膜への電界の負荷もシリコン素子に比べて大きくなる。このため、シリコンパワーデバイスでは酸化膜に大きな電界が加わる前にシリコンの破壊電界強度に達するために問題にならなかったことがＳｉＣでは新たに生じる。すなわち、ＳｉＣでは大きな電界が加わることにより、酸化膜が破壊されることが問題となる。図１２に示すＳｉＣ−ＭＯＳＦＥＴのゲート酸化膜１０６に大きな電界強度が印加されることとなり、ゲート酸化膜１０６が破壊されると信頼性に大きな問題が生じる。これは、ＳｉＣ−ＭＯＳＦＥＴだけでなく、ＳｉＣ−ＩＧＢＴでも同様である。   However, since SiC has a breakdown electric field strength of a semiconductor 10 times higher than that of a silicon element, the load of an electric field on an oxide film when a high voltage is applied is particularly higher than that of a silicon element. For this reason, it is newly generated in SiC that the silicon power device does not become a problem because the breakdown electric field strength of silicon is reached before a large electric field is applied to the oxide film. That is, the problem with SiC is that the oxide film is destroyed by applying a large electric field. A large electric field strength is applied to the gate oxide film 106 of the SiC-MOSFET shown in FIG. 12, and if the gate oxide film 106 is destroyed, a serious problem arises in reliability. This is the same not only in SiC-MOSFET but also in SiC-IGBT.

また、上述したゲートパッド下の素子は、ゲートパッドと素子外部を接続する際に損傷を受けやすいことから、低オン抵抗化のための構造は具体化されていない。   Further, since the element under the gate pad described above is easily damaged when the gate pad is connected to the outside of the element, the structure for reducing the on-resistance is not realized.

本発明は、上記課題に鑑み、高電圧印加時においても、ゲート酸化膜が破壊されることがなく信頼性を有し、低オン抵抗を有する炭化珪素半導体装置およびその製造方法を提供することを目的とする。   In view of the above-described problems, the present invention provides a silicon carbide semiconductor device having a low on-resistance and a reliability without a gate oxide film being destroyed even when a high voltage is applied, and a method for manufacturing the same. Objective.

上記目的を達成するため、本発明にかかる炭化珪素半導体装置は、半導体基板内部に半導体装置構造が作り込まれ、前記半導体装置構造に電気的接触をとるための電極と、外部から前記電極と電気的接触をとるための電極パッドとを備え、前記電極パッドの下部の前記半導体基板にも前記半導体装置構造が作成された炭化珪素半導体装置であって、前記半導体装置構造は、第１導電型の半導体基板と、前記半導体基板上に形成された低不純物濃度の第１導電型の半導体層と、前記第１導電型の半導体層に選択的に形成された高不純物濃度の第２導電型の半導体層と、前記第２導電型の半導体層の表面に形成された低不純物濃度の第２導電型のベース層と、前記ベース層の表面層に選択的に形成された第１導電型のソース領域と、表面から前記ベース層を貫通して前記第１導電型の半導体層に達するように形成された第１導電型のウェル領域と、前記ソース領域と前記ウェル領域とに挟まれた前記ベース層の表面にゲート絶縁膜を介して形成された制御電極とを具備し、異なるセルのそれぞれの前記第２導電型の半導体層の一部同士が、前記ウェル領域の下の領域で互いに結合され、前記ゲートパッド部分の前記ソース領域が前記ゲートパッドの部分以外の前記半導体装置構造のソース領域と電気的に結合され、前記ソース領域が第２導電型領域に覆われ、ソースパッド部分におけるソースパッド領域に対する前記ソース領域の面積比より、前記ゲートパッド部分におけるゲートパッド領域に対する前記ソース領域の面積比が大きいことを特徴とする。
In order to achieve the above object, a silicon carbide semiconductor device according to the present invention includes a semiconductor device structure formed in a semiconductor substrate, an electrode for making electrical contact with the semiconductor device structure, and an external connection between the electrode and the electrode. A silicon carbide semiconductor device in which the semiconductor device structure is formed also on the semiconductor substrate below the electrode pad, the semiconductor device structure having a first conductivity type A semiconductor substrate; a low-conductivity first-conductivity-type semiconductor layer formed on the semiconductor substrate; and a high-impurity-concentration second-conductivity-type semiconductor selectively formed on the first-conductivity-type semiconductor layer. A second conductivity type base layer having a low impurity concentration formed on the surface of the second conductivity type semiconductor layer, and a first conductivity type source region selectively formed on the surface layer of the base layer And from the surface A first conductivity type well region formed so as to penetrate the source layer and reach the first conductivity type semiconductor layer; and a gate on the surface of the base layer sandwiched between the source region and the well region And a control electrode formed through an insulating film, wherein a part of each of the second conductivity type semiconductor layers of different cells is coupled to each other in a region under the well region, and the gate pad portion The source region is electrically coupled to a source region of the semiconductor device structure other than the gate pad portion, the source region is covered with a second conductivity type region, and the source region with respect to the source pad region in the source pad portion The area ratio of the source region to the gate pad region in the gate pad portion is larger than the area ratio of.

また、前記第１導電型の半導体基板の結晶学的面指数は（０００−１）面に対して平行な面もしくは１０度以内に傾いた面であることを特徴とする。   The crystallographic plane index of the first conductivity type semiconductor substrate is a plane parallel to the (000-1) plane or a plane tilted within 10 degrees.

また、前記第１導電型の半導体基板の結晶学的面指数は（０００１）面に対して平行な面もしくは１０度以内に傾いた面であることを特徴とする。   Further, the crystallographic plane index of the first conductivity type semiconductor substrate is a plane parallel to the (0001) plane or a plane tilted within 10 degrees.

また、前記ゲートパッド部分の前記ソース領域が直線状に形成されたことを特徴とする。   Further, the source region of the gate pad portion is formed in a straight line.

また、前記ゲートパッド部分の前記ソース領域が多角形の網の目状に形成されたことを特徴とする。   Further, the source region of the gate pad portion is formed in a polygonal mesh shape.

また、本発明にかかる炭化珪素半導体装置の製造方法は、第１導電型の半導体基板と、前記半導体基板上に形成された低不純物濃度の第１導電型の半導体層と、前記第１導電型の半導体層に選択的に形成された高不純物濃度の第２導電型の半導体層と、前記第２導電型の半導体層の表面に形成された低不純物濃度の第２導電型のベース層と、前記ベース層の表面層に選択的に形成された第１導電型のソース領域と、表面から前記ベース層を貫通して前記第１導電型の半導体層に達するように形成された第１導電型のウェル領域と、前記ソース領域と前記ウェル領域とに挟まれた前記ベース層の表面にゲート絶縁膜を介して形成された制御電極と、を具備し、異なるセルのそれぞれの前記第２導電型の半導体層の一部同士が、前記ウェル領域の下の領域で互いに結合された炭化珪素半導体装置であって、前記半導体基板上に前記第１導電型の半導体層をエピタキシャル成長により形成し、前記第１導電型の半導体層の表面に前記第２導電型の半導体層をイオン注入法により選択的に形成し、前記第１導電型の半導体層と前記第２導電型の半導体層の上に、前記ベース層をエピタキシャル成長法により形成し、前記ベース層の表面層に前記ソース領域と、表面から前記ベース層を貫通して前記第１導電型の半導体層に達する前記ウェル領域とをイオン注入法により選択的に形成したことを特徴とする。   In addition, a method for manufacturing a silicon carbide semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, a low conductivity concentration first conductivity type semiconductor layer formed on the semiconductor substrate, and the first conductivity type. A second conductivity type semiconductor layer having a high impurity concentration selectively formed in the semiconductor layer; a second conductivity type base layer having a low impurity concentration formed on the surface of the second conductivity type semiconductor layer; A source region of a first conductivity type selectively formed on a surface layer of the base layer, and a first conductivity type formed so as to penetrate the base layer from the surface and reach the semiconductor layer of the first conductivity type And a control electrode formed on the surface of the base layer sandwiched between the source region and the well region via a gate insulating film, and each of the second conductivity types of different cells. A portion of the semiconductor layer of the well region Silicon carbide semiconductor devices coupled to each other in the region, wherein the semiconductor layer of the first conductivity type is formed on the semiconductor substrate by epitaxial growth, and the second conductivity type is formed on the surface of the semiconductor layer of the first conductivity type. The semiconductor layer is selectively formed by ion implantation, the base layer is formed on the first conductive type semiconductor layer and the second conductive type semiconductor layer by epitaxial growth, and the surface of the base layer is formed. The source region and the well region that penetrates the base layer from the surface and reaches the first conductivity type semiconductor layer are selectively formed in a layer by an ion implantation method.

上記構成によれば、ソース・ドレイン間に高電圧を印加しても、ｎ型半導体ウェル領域の上のゲート酸化膜に大きな電界がかからず十分な素子耐圧を保持することができる。同様に、ｎ型半導体層ならびにｎ型半導体ウェル領域の不純物濃度を大きく上げて、オン抵抗を十分下げた場合でも十分な素子耐圧を保持することができる。   According to the above configuration, even when a high voltage is applied between the source and drain, a large electric field is not applied to the gate oxide film on the n-type semiconductor well region, and a sufficient device breakdown voltage can be maintained. Similarly, even when the impurity concentration of the n-type semiconductor layer and the n-type semiconductor well region is greatly increased to sufficiently reduce the on-resistance, a sufficient device breakdown voltage can be maintained.

本発明によれば、高電圧印加時においても、ゲート酸化膜が破壊されることがなく信頼性を有し、低オン抵抗化できるという効果を奏する。   According to the present invention, even when a high voltage is applied, the gate oxide film is not destroyed, and there is an effect that the on-resistance can be reduced with reliability.

本発明の第１実施例のＳｉＣ−ＭＯＳＦＥＴの製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of SiC-MOSFET of 1st Example of this invention. 本発明の第１実施例のＳｉＣ−ＭＯＳＦＥＴのｐ+層とセルの配置を表す平面図である。It is a top view showing arrangement | positioning of the p <+> layer and cell of SiC-MOSFET of 1st Example of this invention. 本発明の各実施例により作成したＳｉＣ−ＭＯＳＦＥＴの電気特性の測定結果を示す図表である。It is a graph which shows the measurement result of the electrical property of SiC-MOSFET created by each Example of this invention. 実施例１と比較例の素子耐圧およびｎ打ち返し層の幅を変えた時の素子耐圧の実測結果を示す図表である。It is a graph which shows the actual measurement result of the element withstand voltage when changing the element withstand voltage of Example 1 and a comparative example, and the width | variety of n napping layer. 実施例１のＳｉＣ−ＭＯＳＦＥＴの負荷短絡耐量の測定結果を示す図表である。6 is a chart showing measurement results of load short-circuit withstand capability of the SiC-MOSFET of Example 1. 実施例１のＳｉＣ−ＭＯＳＦＥＴのターンオフ破壊耐量の評価結果を示す図表である。6 is a chart showing evaluation results of turn-off breakdown resistance of the SiC-MOSFET of Example 1. 実施例１のＳｉＣ−ＭＯＳＦＥＴのゲートパッド下の装置構造を示す図である。It is a figure which shows the apparatus structure under the gate pad of SiC-MOSFET of Example 1. FIG. 実施例１のＳｉＣ−ＭＯＳＦＥＴのゲートパッド下の他の装置構造を示す図である。6 is a view showing another device structure under the gate pad of the SiC-MOSFET of Example 1. FIG. 本発明の実施例３のＳｉＣ−ＭＯＳＦＥＴのｐ+層とセルの配置を表す図である。It is a figure showing arrangement | positioning of the p <+> layer and cell of SiC-MOSFET of Example 3 of this invention. 各実施例のＳｉＣ−ＭＯＳＦＥＴのターンオフスイッチング波形を示す図表である。It is a graph which shows the turn-off switching waveform of SiC-MOSFET of each Example. 各実施例のＳｉＣ−ＭＯＳＦＥＴのターンオンスイッチング波形を示す図表である。It is a graph which shows the turn-on switching waveform of SiC-MOSFET of each Example. 一般的なＭＯＳＦＥＴの断面図である。It is sectional drawing of a common MOSFET. 従来のシリコン超接合ＭＯＳＦＥＴ断面構造を示す図である。It is a figure which shows the conventional silicon super junction MOSFET cross-section. 従来のシリコン超接合ＭＯＳＦＥＴ断面構造を示す図である。（マルチエピ法）It is a figure which shows the conventional silicon super junction MOSFET cross-section. (Multi-epi method) 従来のシリコン超接合ＭＯＳＦＥＴ断面構造を示す図である。（トレンチ埋め込み法）It is a figure which shows the conventional silicon super junction MOSFET cross-section. (Trench filling method)

以下に添付図面を参照して、この発明にかかる炭化珪素半導体装置およびその製造方法の好適な実施例を詳細に説明する。   Exemplary embodiments of a silicon carbide semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings.

（実施例１）
図１は、本発明の第１実施例のＳｉＣ−ＭＯＳＦＥＴの製造工程を示す断面図である。図１の（ａ）はｐ+層が結合していない部分の断面図、（ｂ）は、ｐ+層が結合している部分の断面図である。 Example 1
FIG. 1 is a cross-sectional view showing a manufacturing process of the SiC-MOSFET of the first embodiment of the present invention. (A) of FIG. 1 is a sectional view of a portion p + layer is not bound, (b) are cross-sectional views of a portion p + layer is bonded.

本実施例では、縦型プレーナーゲートＭＯＳＦＥＴとして、半導体材料として炭化珪素素（ＳｉＣ）を用い、素子耐圧１２００ＶのＭＯＳＦＥＴを示している。はじめに、（１）に示すように、ｎ+（第１導電型）のＳｉＣ半導体基板１を用意する。ＩＧＢＴの場合には、ｐ+の半導体基板１を用いる。ここでは、不純物として窒素を２×１０19ｃｍ-3程度含む低抵抗のＳｉＣ半導体基板１とした。このｎ+型半導体基板１の結晶学的面指数が（０００−１）面に対して、４度傾いた面の上に、窒素を１．８×１０16ｃｍ-3程度含むｎ-型（第１導電型）のＳｉＣ層２を１０μｍ程度エピタキシャル成長により積層する。 In the present embodiment, as a vertical planar gate MOSFET, a silicon carbide (SiC) is used as a semiconductor material, and a MOSFET having an element withstand voltage of 1200 V is shown. First, as shown in (1), an n + (first conductivity type) SiC semiconductor substrate 1 is prepared. In the case of an IGBT, a p + semiconductor substrate 1 is used. Here, a low-resistance SiC semiconductor substrate 1 containing about 2 × 10 19 cm −3 of nitrogen as an impurity is used. The n + -type semiconductor substrate 1 has an n − type containing about 1.8 × 10 16 cm −3 of nitrogen on a plane whose crystallographic plane index is inclined by 4 degrees with respect to the (000-1) plane. A SiC layer 2 of the first conductivity type is stacked by epitaxial growth of about 10 μm.

次に、（２）に示すように、ＳｉＣ層２の上に幅１３μｍで深さ０．５μｍの第２導電型のｐ+層３をイオン注入法により形成する。その際のイオンは、例えばアルミニウムを用いる。また、不純物濃度は、１．０×１０18ｃｍ-3となるようにドーズ量を設定した。その際、後述する第１導電型のｎ打ち返し層６の下でｐ+層３の一部を他のセル２０との間で互いに結合するようにする（図１（ｂ）の（４）参照、および平面図は図２参照）。また、ｐ+層３間において結合していない箇所の距離は２μｍとした。 Next, as shown in (2), a second conductivity type p + layer 3 having a width of 13 μm and a depth of 0.5 μm is formed on the SiC layer 2 by ion implantation. For example, aluminum is used as the ions at that time. The dose was set so that the impurity concentration was 1.0 × 10 18 cm −3 . At that time, a part of the p + layer 3 is coupled to another cell 20 under the n-type napping layer 6 of the first conductivity type described later (see (4) in FIG. 1B). FIG. 2 for a plan view). Further, the distance between the unbonded portions between the p + layers 3 was 2 μm.

その後、（３）に示すように、第２導電型のｐベース層４をエピタキシャル成長法により０．５μｍ厚で前記ｐ+層３ならびにｎ-型のＳｉＣ層２上に形成する。その際の不純物は、アルミニウムとし、不純物濃度は２．０×１０16ｃｍ-3となるようにした。 Thereafter, as shown in (3), a second conductivity type p base layer 4 is formed on the p + layer 3 and the n − type SiC layer 2 to a thickness of 0.5 μm by epitaxial growth. The impurity at that time was aluminum, and the impurity concentration was set to 2.0 × 10 16 cm −3 .

その後、（４）に示すように、ｎ打ち返し層６として、窒素イオンが５．０×１０16ｃｍ-3、深さ１．５μｍ、幅２．０μｍになるように選択的に注入する。そして、（５）に示すように、ｐベース層４内に第１導電型のｎ+ソース層７と、第２導電型のｐ+コンタクト層８を選択的に形成する。 Thereafter, as shown in (4), as the n-turnback layer 6, nitrogen ions are selectively implanted so as to be 5.0 × 10 16 cm −3 , a depth of 1.5 μm, and a width of 2.0 μm. Then, as shown in (5), the first conductivity type n + source layer 7 and the second conductivity type p + contact layer 8 are selectively formed in the p base layer 4.

その後、活性化アニールを実施する。熱処理温度・時間は１６２０℃・２分である。これにより、（６）に示すように、ゲート酸化膜を１００ｎｍの厚さで熱酸化により形成し、水素雰囲気中にて１０００℃付近でアニールする。そして、リンがドープされた多結晶シリコン層をゲート酸化膜上にゲート電極９として形成し、パターニングする。   Thereafter, activation annealing is performed. The heat treatment temperature and time are 1620 ° C. and 2 minutes. Thereby, as shown in (6), a gate oxide film is formed by thermal oxidation with a thickness of 100 nm, and annealed in the vicinity of 1000 ° C. in a hydrogen atmosphere. Then, a polycrystalline silicon layer doped with phosphorus is formed as a gate electrode 9 on the gate oxide film and patterned.

この後、（７）に示すように、層間絶縁膜１０としてリンガラスを１．０μｍ厚で成膜後、パターニングしてから熱処理する。また、１％シリコンを含んだアルミニウムを表面にスパッタ法にて厚さ５μｍで成膜し、表面電極（ソース電極）１１を形成する。素子裏面にはニッケルを成膜し９７０℃で熱処理後、チタン、ニッケル、金からなる裏面電極１２を成膜した。この後、保護膜を表面に付加して素子は完成する。   Thereafter, as shown in (7), a phosphorus glass film having a thickness of 1.0 μm is formed as the interlayer insulating film 10 and then heat-treated after patterning. Further, a surface electrode (source electrode) 11 is formed by depositing aluminum containing 1% silicon on the surface with a thickness of 5 μm by sputtering. A nickel film was formed on the back surface of the device, and after heat treatment at 970 ° C., a back electrode 12 made of titanium, nickel, and gold was formed. Thereafter, a protective film is added to the surface to complete the device.

図２は、本発明の第１実施例のＳｉＣ−ＭＯＳＦＥＴのｐ+層とセルの配置を表す平面図である。図２の例では、ｎ打ち返し層６の下でｐ+層３の各角部から他のセル２０の角部に向けて互いに結合部３ａにより結合している。図２の例では、各セル２０を６角形セルパターンにて作成した。これに限らず、各セル２０を４角形セルとしてもよい。 FIG. 2 is a plan view showing the arrangement of the p + layer and the cell of the SiC-MOSFET of the first embodiment of the present invention. In the example of FIG. 2, the n + layers 6 are coupled to each other from the corners of the p + layer 3 toward the corners of the other cells 20 by the coupling portions 3 a. In the example of FIG. 2, each cell 20 is created with a hexagonal cell pattern. Not only this but each cell 20 is good also as a square cell.

図３は、本発明の各実施例により作成したＳｉＣ−ＭＯＳＦＥＴの電気特性の測定結果を示す図表である。本発明の実施例のチップサイズは３ｍｍ角であり、活性面積は５．２７ｍｍ2であり、定格電流は２５Ａである。オン抵抗（ＲｏｎＡ）は２．８ｍΩｃｍ2と十分低い値を示し、初期の素子耐圧も１４５０Ｖとなり、１２００Ｖ素子として十分良好な特性を示している。 FIG. 3 is a chart showing the measurement results of the electrical characteristics of the SiC-MOSFETs produced according to the examples of the present invention. The chip size of the embodiment of the present invention is 3 mm square, the active area is 5.27 mm 2 , and the rated current is 25A. The on-resistance (RonA) is a sufficiently low value of 2.8 mΩcm 2, and the initial device breakdown voltage is 1450 V, indicating sufficiently good characteristics as a 1200 V device.

また、比較例（従来技術）として、ｐ+層３同士をまったく結合させないようにして作成したＳｉＣ−ＭＯＳＦＥＴを測定した。この比較例の場合、オン抵抗は、同等の２．８ｍΩｃｍ2と十分低い値を示したが、ソース・ドレイン間に８８０Ｖを印加したところで、ゲート酸化膜が破壊した。このことから、本発明は十分な素子耐圧を維持しながら、極めて小さいオン抵抗を示していることが分かる。 In addition, as a comparative example (prior art), an SiC-MOSFET prepared so as not to bond the p + layers 3 to each other was measured. In the case of this comparative example, the on-resistance was as low as 2.8 mΩcm 2 , but the gate oxide film was destroyed when 880 V was applied between the source and drain. From this, it can be seen that the present invention shows an extremely small on-resistance while maintaining a sufficient element breakdown voltage.

図４は、実施例１と比較例の素子耐圧およびｎ打ち返し層の幅を変えた時の素子耐圧の実測結果を示す図表である。比較例は、上述したように、ｐ+層３をセル間で全く結合させないＳｉＣ−ＭＯＳＦＥＴである。素子の各層の濃度厚さは上述のとおりである。その結果、本発明の実施例１の方が、１２００Ｖデバイスとして十分な耐圧特性である１４００Ｖ以上の高耐圧特性を実現していることが分かる。なお、オン抵抗は実施例１および比較例共に同一であり、実施例１のようにゲートパッド下にセルを作り込むことは、オン抵抗低減に効果があることが分かった。 FIG. 4 is a table showing the actual measurement results of the device breakdown voltage when the device breakdown voltage and the width of the n-type striking layer are changed between Example 1 and the comparative example. As described above, the comparative example is a SiC-MOSFET in which the p + layer 3 is not coupled between cells at all. The concentration thickness of each layer of the element is as described above. As a result, it can be seen that Example 1 of the present invention achieves a high breakdown voltage characteristic of 1400 V or higher, which is a sufficient breakdown voltage characteristic for a 1200 V device. The on-resistance is the same in both Example 1 and Comparative Example, and it has been found that forming a cell under the gate pad as in Example 1 is effective in reducing the on-resistance.

比較例のＳｉＣ−ＭＯＳＦＥＴで本実施例１と同等の１４００Ｖ以上の高耐圧特性を満足させるには、ｐ+層３の間の距離を１．０μｍ以下にし、かつｎ打ち返し層６の打ち返し濃度を５分の１まで低減させなくてはならないことが分かった。また、この条件の比較例におけるオン抵抗は１０．８ｍΩｃｍ2と極めて高い値を示した。これにより、本発明は、比較例に比してオン抵抗が小さく、同時に素子耐圧特性を高めることができる。 In order to satisfy the high breakdown voltage characteristic equal to or higher than 1400 V equivalent to the first embodiment in the SiC-MOSFET of the comparative example, the distance between the p + layers 3 is set to 1.0 μm or less, and the napping layer 6 has a bounce concentration. It has been found that it must be reduced to one fifth. In addition, the on-resistance in the comparative example under this condition showed an extremely high value of 10.8 mΩcm 2 . Thereby, the present invention has a smaller on-resistance than that of the comparative example, and can simultaneously improve the element withstand voltage characteristic.

図５は、実施例１のＳｉＣ−ＭＯＳＦＥＴの負荷短絡耐量の測定結果を示す図表である。負荷短絡耐量試験では、電源電圧を直接ソース・ドレイン間に印加し、その状態でゲート電極にＶｇ＝２０Ｖの電圧を印加し、何μｓｅｃの期間、ゲート酸化膜の破壊が生じないかを評価する。測定時の条件は、電源電圧Ｖｃｃ＝８００Ｖとし、また測定温度（Ｔｊ）は１７５℃とした。図５の測定波形に示すように、最大電流が素子定格の５倍である１２５Ａを導通させても破壊せず、さらに１５μｓｅｃでも破壊しないという十分な特性を示した。   FIG. 5 is a table showing the measurement results of the load short-circuit withstand capability of the SiC-MOSFET of Example 1. In the load short-circuit tolerance test, a power supply voltage is directly applied between the source and the drain, and a voltage of Vg = 20 V is applied to the gate electrode in that state, and evaluation is made for how many μsec the gate oxide film is not destroyed. . The measurement conditions were the power supply voltage Vcc = 800 V and the measurement temperature (Tj) was 175 ° C. As shown in the measurement waveform of FIG. 5, it showed sufficient characteristics that it does not break even when 125A, whose maximum current is five times the element rating, is conducted, and does not break even after 15 μsec.

図６は、実施例１のＳｉＣ−ＭＯＳＦＥＴのターンオフ破壊耐量の評価結果を示す図表である。ターンオフ耐量を評価したところ、ソース・ドレイン間電圧は１６３０Ｖにクランプされ（図６中のＶｄｓ ｃｌａｍｐ）、破壊することなく１００Ａ（定格電流の４倍）を１５０℃にてオフできることを確認した。このことから、実施例１では低オン抵抗を実現し、かつ負荷短絡耐量、ターンオフ耐量が極めて大きい素子であるということがわかる。比較例のＳｉＣ−ＭＯＳＦＥＴの耐量を評価したところ、素子耐圧が十分でないために負荷短絡耐量、ターンオフ耐量とも本実施例１の素子に大きく劣る結果となった（図３参照）。   6 is a table showing the evaluation results of the turn-off breakdown resistance of the SiC-MOSFET of Example 1. FIG. When the turn-off resistance was evaluated, the source-drain voltage was clamped at 1630 V (Vds clamp in FIG. 6), and it was confirmed that 100 A (four times the rated current) could be turned off at 150 ° C. without destruction. From this, it can be seen that Example 1 is an element that achieves a low on-resistance and has extremely large load short-circuit withstand capability and turn-off capability. When the tolerance of the SiC-MOSFET of the comparative example was evaluated, the device withstand voltage was not sufficient, so that both the load short-circuit tolerance and the turn-off tolerance were significantly inferior to those of the element of Example 1 (see FIG. 3).

なお、前記ｎ型半導体基板１の結晶学的面指数は（０００−１）面に対し、ＳｉＣ層２を０度、２度、８度、１０度傾いた面上にそれぞれ同様に成膜し、作成した素子であっても特性の変化はほとんどなく良好であった。   The crystallographic plane index of the n-type semiconductor substrate 1 is the same as that of the SiC layer 2 formed on the plane inclined by 0 °, 2 °, 8 °, and 10 ° with respect to the (000-1) plane. Even in the fabricated element, there was almost no change in characteristics and it was good.

図７は、実施例１のＳｉＣ−ＭＯＳＦＥＴのゲートパッド下の装置構造を示す図である。図７の（ａ）は平面図、（ｂ）は（ａ）のＡ−Ａ線断面図、（ｃ）は（ａ）のＢ−Ｂ線断面図であり、ゲート電極及び酸化膜は省略してある。実施例１の構成において、さらに、オン抵抗を低抵抗化するには、図７に示すように、ゲートパッド下に、ソースパッド下のソース領域７１からｎ型半導体を用いて電気的に接続されたソース領域７０を形成する。このｎ型半導体のソース領域７０はｐ型半導体領域７２のウェルによってｎ型半導体領域７３から分離されていなければならない。図７では、ゲートパッド下のソース領域７０が一直線状になっており、ゲート酸化膜保護のためのｐ層（第２導電型領域）７４をこのソース領域７０に直交して設けている。
FIG. 7 is a diagram illustrating a device structure under the gate pad of the SiC-MOSFET according to the first embodiment. 7A is a plan view, FIG. 7B is a cross-sectional view taken along line AA of FIG. 7A, and FIG. 7C is a cross - sectional view taken along line BB of FIG. 7A, omitting the gate electrode and the oxide film. It is. In the configuration of the first embodiment, in order to further reduce the on-resistance, as shown in FIG. 7, the n-type semiconductor is electrically connected from the source region 71 under the source pad under the gate pad. The source region 70 is formed. This n-type semiconductor source region 70 must be separated from the n-type semiconductor region 73 by the well of the p-type semiconductor region 72. In FIG. 7, the source region 70 under the gate pad is in a straight line, and a p layer (second conductivity type region) 74 for protecting the gate oxide film is provided orthogonal to the source region 70.

図８は、実施例１のＳｉＣ−ＭＯＳＦＥＴのゲートパッド下の他の装置構造を示す図である。図８の（ａ）は平面図、（ｂ）は（ａ）のＣ−Ｃ線断面図であり、ゲート電極及び酸化膜は省略してある。ゲートパッド下のソース領域７１を６角形の網の目状に形成している。そして、ゲート酸化膜保護のためのｐ層７４が６角形のソース領域７０の中心に浮遊しているものである。ソース領域７１の形状は６角形に限らず多角形にできる。   FIG. 8 is a diagram illustrating another device structure under the gate pad of the SiC-MOSFET according to the first embodiment. 8A is a plan view, and FIG. 8B is a sectional view taken along the line CC of FIG. 8A, omitting the gate electrode and the oxide film. A source region 71 under the gate pad is formed in a hexagonal mesh pattern. A p layer 74 for protecting the gate oxide film is floating in the center of the hexagonal source region 70. The shape of the source region 71 is not limited to a hexagon and can be a polygon.

これら図７、図８のように、ゲートパッド下にも素子を作製することにより、同一装置の面積内での素子利用面積を増やすことができ、オン抵抗を低減できるようになる。   As shown in FIGS. 7 and 8, by fabricating an element also under the gate pad, it is possible to increase the element use area within the area of the same device, and to reduce the on-resistance.

（実施例２）
本発明の実施例２では、実施例１と同様の製造工程にて１２００Ｖ、２５ＡのＳｉＣ−ＭＯＳＦＥＴを作成した。この実施例２ではｎ型半導体基板１の結晶学的面指数は（０００１）面に対して４度傾いた面の上に、窒素を１．８×１０16ｃｍ-3程度含むｎ型ＳｉＣ層２を１０μｍ程度エピタキシャル成長させている。その他の工程、およびセル構造は全く同一である。実施例２の素子の電気特性評価結果は、上記図３に示されており、オン抵抗は、実施例１に対し、５５％ほど増加するが、通常のＳｉＣ−ＭＯＳＦＥＴに対しては十分低いオン抵抗特性を示していることがわかる。なお、ｎ型半導体基板１の結晶学的面指数は（０００１）面に対して０度、２度、８度、１０度傾いた面上に、ｎ型ＳｉＣ層２を同様に成膜し、作成した素子についても素子評価を行ったところ、特性の変化はほとんどなく良好であった。 (Example 2)
In Example 2 of the present invention, a 1200 V, 25 A SiC-MOSFET was produced by the same manufacturing process as in Example 1. In Example 2, the crystallographic plane index of the n-type semiconductor substrate 1 is an n-type SiC layer containing about 1.8 × 10 16 cm −3 of nitrogen on a plane inclined by 4 degrees with respect to the (0001) plane. 2 is epitaxially grown by about 10 μm. Other processes and the cell structure are exactly the same. The electrical characteristic evaluation result of the element of Example 2 is shown in FIG. 3 above, and the on-resistance increases by 55% compared to Example 1, but it is sufficiently low for the normal SiC-MOSFET. It can be seen that the resistance characteristic is exhibited. In addition, the n-type SiC layer 2 is similarly formed on a surface inclined by 0 °, 2 °, 8 °, and 10 ° with respect to the (0001) plane of the crystallographic plane index of the n-type semiconductor substrate 1. When the device was evaluated for the fabricated device, the characteristics were almost unchanged and good.

（実施例３）
本発明の実施例３では、実施例１と同様の製造工程にて１２００Ｖ、２５ＡのＳｉＣ−ＭＯＳＦＥＴを作製した。ｎ型半導体基板１の結晶学的面指数は（０００−１）面に対して４度傾いた面の上に窒素を１．８×１０16ｃｍ-3程度含むｎ型ＳｉＣ層２を１０μｍ程度エピタキシャル成長させている。 (Example 3)
In Example 3 of the present invention, a 1200 V, 25 A SiC-MOSFET was manufactured by the same manufacturing process as in Example 1. The crystallographic plane index of the n-type semiconductor substrate 1 is about 10 μm of an n-type SiC layer 2 containing about 1.8 × 10 16 cm −3 of nitrogen on a plane inclined by 4 degrees with respect to the (000-1) plane. Epitaxial growth.

図９は、本発明の実施例３のＳｉＣ−ＭＯＳＦＥＴのｐ+層とセルの配置を表す図である。図９に示すように、セルはストライプパターンで形成している。そのため、ｐ+層３の配置は、セル２０，２０間のｐ+層３を結合部３ａにより結合させている。その他の工程は実施例１と同一である。作成した素子の電気特性評価結果は、上記図３に示されており、オン抵抗は実施例１に対し、１０％ほど増加するものの、通常のＳｉＣ−ＭＯＳＦＥＴに対しては十分低いオン抵抗特性と高耐圧特性を示していることがわかる。 FIG. 9 is a diagram illustrating the arrangement of the p + layer and the cell of the SiC-MOSFET according to the third embodiment of the present invention. As shown in FIG. 9, the cells are formed in a stripe pattern. Therefore, the arrangement of the p + layer 3 is coupled by the coupling portion 3a of the p + layer 3 between the cells 20, 20. Other steps are the same as those in the first embodiment. The electrical property evaluation result of the fabricated element is shown in FIG. 3, and the on-resistance increases by about 10% compared to Example 1, but the on-resistance characteristics are sufficiently low for a normal SiC-MOSFET. It can be seen that high breakdown voltage characteristics are exhibited.

（実施例４）
本発明の実施例４の製造方法について説明する。まず、ｎ型のＳｉＣ半導体基板１を用意する。不純物として窒素を２×１０19ｃｍ-3程度含む低抵抗のＳｉＣ半導体基板１を用いた。次に、ｎ型半導体基板１の結晶学的面指数は（０００−１）面に対して４度傾いた面の上に窒素を１．８×１０16ｃｍ-3程度含むｎ型ＳｉＣ層２を１０μｍ程度エピタキシャル成長させる。つぎに、ｎ型ＳｉＣ層２の上に幅１３μｍ、厚さ０．５μｍのｐ+層３をエピタキシャル法で形成する。その際の不純物イオンにアルミニウムを用いた。また、不純物濃度は、１．０×１０18ｃｍ-3となるようにドーズ量を設定した。その際、実施例１と同様、ｎ打ち返し層６の下でｐ+層３の一部を互いに結合するようにする（図２参照）。実施例４では、６角形セルパターンにて作成したが、４角形セルなどでも問題ない。また、ｐ+層３間において結合していない箇所のｐ+層３間の距離は２μｍとした。 Example 4
A manufacturing method of Example 4 of the present invention will be described. First, an n-type SiC semiconductor substrate 1 is prepared. A low resistance SiC semiconductor substrate 1 containing about 2 × 10 19 cm −3 of nitrogen as an impurity was used. Next, the crystallographic plane index of the n-type semiconductor substrate 1 is an n-type SiC layer 2 containing about 1.8 × 10 16 cm −3 of nitrogen on a plane inclined by 4 degrees with respect to the (000-1) plane. Is grown about 10 μm epitaxially. Next, a p + layer 3 having a width of 13 μm and a thickness of 0.5 μm is formed on the n-type SiC layer 2 by an epitaxial method. Aluminum was used as impurity ions at that time. The dose was set so that the impurity concentration was 1.0 × 10 18 cm −3 . At this time, as in the first embodiment, a part of the p + layer 3 is coupled to each other under the n-turnback layer 6 (see FIG. 2). In the fourth embodiment, a hexagonal cell pattern is used, but there is no problem even with a quadrangular cell. The distance between the p + layer 3 of a portion not bonded in between the p + layer 3 was set to 2 [mu] m.

その後、ｐベース層４をエピタキシャル成長法により０．５μｍ厚でｐ+層３ならびにｎ型ＳｉＣ層２上に形成する。その際の不純物はアルミニウムとし、不純物濃度は２．０×１０16ｃｍ-3となるようにした。その後、ｎ打ち返し層６として窒素イオンを選択的に注入し、ｎ+ソース層７、ｐ+コンタクト層８をｐベース層４内に選択的に形成する。ｎ打ち返し層６の濃度、厚さ、幅は実施例１と同じである。 Thereafter, the p base layer 4 is formed on the p + layer 3 and the n-type SiC layer 2 to a thickness of 0.5 μm by an epitaxial growth method. The impurity at that time was aluminum, and the impurity concentration was set to 2.0 × 10 16 cm −3 . Thereafter, nitrogen ions are selectively implanted as the n-back layer 6 to selectively form the n + source layer 7 and the p + contact layer 8 in the p base layer 4. The concentration, thickness, and width of the n-turnback layer 6 are the same as those in the first embodiment.

その後活性化アニールを実施する。活性化アニール時の熱処理温度と時間は、それぞれ１６２０℃、２分である。その後、ゲート酸化膜１００ｎｍの厚さを熱酸化で形成し、水素雰囲気中にて１０００℃付近でアニールする。リンがドープされた多結晶シリコン層をゲート電極として形成、パターニング後、層間絶縁膜１０としてリンガラスを１．０μｍ厚で成膜およびパターニングして熱処理し、１％シリコンを含んだアルミニウムを表面にスパッタ法にて厚さ５μｍで成膜した。素子裏面にはニッケルを成膜し９７０℃で熱処理後、チタン、ニッケル、金からなる裏面電極１２を成膜した。そして保護膜を表面に付加して素子は完成する。   Thereafter, activation annealing is performed. The heat treatment temperature and time during activation annealing are 1620 ° C. and 2 minutes, respectively. Thereafter, a gate oxide film having a thickness of 100 nm is formed by thermal oxidation and annealed in the hydrogen atmosphere at around 1000 ° C. Forming and patterning a polycrystalline silicon layer doped with phosphorus as a gate electrode, patterning, forming and patterning phosphorus glass with a thickness of 1.0 μm as an interlayer insulating film 10, and heat-treating aluminum containing 1% silicon on the surface A film was formed with a thickness of 5 μm by sputtering. A nickel film was formed on the back surface of the device, and after heat treatment at 970 ° C., a back electrode 12 made of titanium, nickel, and gold was formed. Then, a protective film is added to the surface to complete the device.

このようにして作成した実施例４のＳｉＣ−ＭＯＳＦＥＴの電気特性の測定結果を図３に示す。チップサイズは３ｍｍ角であり、活性面積は５．２７ｍｍ2であり、定格電流は２５Ａである。オン抵抗（ＲｏｎＡ）は２．８５ｍΩｃｍ2と十分低い値を示し、初期の素子耐圧も１４５５Ｖと、１２００Ｖ素子として十分良好な特性を示している。なお、ｎ型半導体基板１の結晶学的面指数は（０００−１）面に対して０度、２度、８度、１０度傾いた面上同様に成膜し、作成した素子についても素子評価を行ったところ、特性の変化はほとんどなく良好であった。 FIG. 3 shows the measurement results of the electrical characteristics of the SiC-MOSFET of Example 4 created in this way. The chip size is 3 mm square, the active area is 5.27 mm 2 , and the rated current is 25A. The on-resistance (RonA) is a sufficiently low value of 2.85 mΩcm 2, and the initial device breakdown voltage is 1455 V, which is sufficiently good for a 1200 V device. Note that the crystallographic plane index of the n-type semiconductor substrate 1 is similarly formed on a plane inclined at 0 °, 2 °, 8 °, and 10 ° with respect to the (000-1) plane, and the created device is also an element. As a result of evaluation, there was almost no change in characteristics, and it was good.

（実施例５）
実施例５では、実施例４と同様の製造工程にて１２００Ｖ、２５ＡのＳｉＣ−ＭＯＳＦＥＴを作製した。ただし、実施例５では、ｎ型半導体基板１の結晶学的面指数は（０００１）面に対して４度傾いた面の上に窒素を１．８×１０16ｃｍ-3程度含むｎ型ＳｉＣ層２を１０μｍ程度エピタキシャル成長させた。その他の工程は全く同一である。作製した素子の電気特性評価結果を図４に示す。オン抵抗は、実施例４に対し、５０％ほど増加するものの、通常のＳｉＣ−ＭＯＳＦＥＴに対しては十分低いオン抵抗特性を示していることがわかる。なお、ｎ型半導体基板１の結晶学的面指数は（０００１）面に対して０度、２度、８度、１０度傾いた面上同様に成膜し、作成した素子についても素子評価を行ったところ、特性の変化はほとんどなく良好であった。 (Example 5)
In Example 5, a 1200 V, 25 A SiC-MOSFET was manufactured by the same manufacturing process as in Example 4. However, in Example 5, the crystallographic plane index of the n-type semiconductor substrate 1 is n-type SiC containing about 1.8 × 10 16 cm −3 of nitrogen on a plane inclined by 4 degrees with respect to the (0001) plane. Layer 2 was epitaxially grown by about 10 μm. Other processes are exactly the same. FIG. 4 shows the result of evaluating the electrical characteristics of the manufactured element. Although the on-resistance increases by about 50% with respect to Example 4, it can be seen that the on-resistance characteristics are sufficiently low for a normal SiC-MOSFET. The crystallographic plane index of the n-type semiconductor substrate 1 was similarly formed on a plane inclined at 0 °, 2 °, 8 °, and 10 ° with respect to the (0001) plane. As a result, there was almost no change in characteristics and it was good.

図１０は、各実施例のＳｉＣ−ＭＯＳＦＥＴのターンオフスイッチング波形を示す図表、図１１は、各実施例のＳｉＣ−ＭＯＳＦＥＴのターンオンスイッチング波形を示す図表である。実施例１〜４により作成したＳｉＣ-ＭＯＳＦＥＴのスイッチング損失評価を示している。それぞれ（ａ）は室温（ＲＴ）、（ｂ）は温度２００度の測定結果である。ターンオン損失およびターンオフ損失を低減でき、ターンオンおよびターンオフのスイッチングともに良好な波形が得られた。本発明のＳｉＣ−ＭＯＳＦＥＴによれば、図３に示すように、ターンオン、ターンオフ損失とも、同一定格のＳｉ−ＩＧＢＴ（１２００Ｖ、２５Ａ）に対し、６０％以上もの低減を図ることができる。   FIG. 10 is a chart showing the turn-off switching waveform of the SiC-MOSFET in each embodiment, and FIG. 11 is a chart showing the turn-on switching waveform of the SiC-MOSFET in each embodiment. The switching loss evaluation of the SiC-MOSFET produced by Examples 1-4 is shown. (A) is a measurement result at room temperature (RT), and (b) is a measurement result at a temperature of 200 degrees. Turn-on loss and turn-off loss could be reduced, and good waveforms were obtained for both turn-on and turn-off switching. According to the SiC-MOSFET of the present invention, as shown in FIG. 3, both the turn-on and turn-off losses can be reduced by 60% or more with respect to the same rated Si-IGBT (1200 V, 25 A).

上記構成によれば、ｎ型半導体層ならびにｎ型半導体ウェル領域の不純物濃度を大きく上げて、オン抵抗を十分下げた場合、またはｐ型半導体層の間、およびベース層の間の距離を広げてオン抵抗を十分下げた場合、またはソース・ドレイン間に高電圧を印加した場合（ソースが０Ｖ、ドレインに＋電圧を印加）、のいずれにおいても、ｎ型半導体ウェル領域の上のゲート酸化膜に大きな電界がかからず十分な素子耐圧を保持することができる。これは空乏層がｐ+コンタクト層に沿って横方向に広がりやすくなるためである。その結果、ｎ型半導体層ならびにｎ型半導体ウェル領域の不純物濃度を従来のＳｉ−ＭＯＳＦＥＴよりも高く設定しても空乏層が広がりやすい設計であるため、ｐ型のコンタクト層の間、ならびにｐ型のベース層の間の距離を広げて素子耐圧を十分保ちつつオン抵抗を小さくできる。 According to the above configuration, the impurity concentration in the n-type semiconductor layer and the n-type semiconductor well region is greatly increased to sufficiently reduce the on-resistance, or the distance between the p-type semiconductor layer and the base layer is increased. In either case where the on-resistance is sufficiently lowered or a high voltage is applied between the source and the drain (the source is 0 V and the + voltage is applied to the drain), the gate oxide film on the n-type semiconductor well region is applied. A large electric field is not applied and a sufficient element breakdown voltage can be maintained. This is because the depletion layer tends to spread laterally along the p + contact layer. As a result, the depletion layer tends to spread even if the impurity concentration of the n-type semiconductor layer and the n-type semiconductor well region is set higher than that of the conventional Si-MOSFET. By increasing the distance between the base layers, the on-resistance can be reduced while maintaining a sufficient device breakdown voltage.

また、ｐ型のベース層をエピタキシャル成長法によって形成した場合、表面荒れがほとんどない程度に平坦にできるため、表面のＭＯＳＦＥＴ部分の移動度が極めて大きくなり、その結果、オン抵抗をさらに小さくすることができる。   Further, when the p-type base layer is formed by the epitaxial growth method, it can be flattened to the extent that there is almost no surface roughness, so that the mobility of the MOSFET portion on the surface becomes extremely high, and as a result, the on-resistance can be further reduced. it can.

さらに、半導体材料に炭化珪素も用いる場合、ｎ型半導体基板の結晶学的面指数は、（０００−１）面に対して平行な面もしくは１０度以内、またはｎ型半導体基板の結晶学的面指数は（０００１）面に対して平行な面もしくは１０度以内に設定することにより、ゲート酸化膜と半導体界面の界面準位密度を低減でき、ＭＯＳＦＥＴ部分の移動度をさらに向上させることができる。その結果、オン抵抗を極めて小さくすることができる。   Further, when silicon carbide is also used as the semiconductor material, the crystallographic plane index of the n-type semiconductor substrate is a plane parallel to the (000-1) plane or within 10 degrees, or the crystallographic plane of the n-type semiconductor substrate. By setting the index to a plane parallel to the (0001) plane or within 10 degrees, the interface state density between the gate oxide film and the semiconductor interface can be reduced, and the mobility of the MOSFET portion can be further improved. As a result, the on-resistance can be made extremely small.

そして、ゲートパッド下にもソース領域を形成し、素子構造を作り込む構造とすることによって、複雑な階層状の電極構造を必要とせずとも有効素子面積を増大し、オン抵抗を小さくすることができるようになる。   Further, by forming a source region under the gate pad and forming an element structure, the effective element area can be increased and the on-resistance can be reduced without requiring a complicated hierarchical electrode structure. become able to.

上記の実施例では、本発明の炭化珪素半導体装置として、ＭＯＳＦＥＴを例に説明したが、これに限るものではない。例えば、ＩＧＢＴにも同様に適用でき、高電圧印加時においても、ゲート酸化膜が破壊されることがなく信頼性を有し、低オン抵抗を有することができる。   In the above embodiment, the MOSFET is described as an example of the silicon carbide semiconductor device of the present invention, but the present invention is not limited to this. For example, the present invention can be similarly applied to an IGBT, and even when a high voltage is applied, the gate oxide film is not destroyed and has reliability and low on-resistance.

そして、本発明によれば、基板の結晶面方位によらず十分な素子耐圧特性を保持したまま、低オン抵抗で破壊耐量が大きく、さらに高速スイッチング特性が可能なＭＯＳＦＥＴならびにＩＧＢＴ等のパワーデバイスを提供することが可能になる。   According to the present invention, power devices such as MOSFETs and IGBTs that have a low on-resistance, a large breakdown resistance, and a high-speed switching characteristic while maintaining a sufficient element breakdown voltage characteristic regardless of the crystal plane orientation of the substrate. It becomes possible to provide.

以上のように、本発明は、ＳｉＣ基板を用いたパワーデバイス全般に適用することができ、ＭＯＳＦＥＴやＩＧＢＴの製造に有用である。   As described above, the present invention can be applied to all power devices using a SiC substrate, and is useful for manufacturing MOSFETs and IGBTs.

１ ＳｉＣ半導体基板
２ ＳｉＣ層
３ ｐ+層
４ ベース層
６ ｎ打ち返し層
７ ソース層
８ コンタクト層
１１ ソース電極
１２ 裏面電極
２０ セル DESCRIPTION OF SYMBOLS 1 SiC semiconductor substrate 2 SiC layer 3 p + layer 4 Base layer 6 n Return layer 7 Source layer 8 Contact layer 11 Source electrode 12 Back surface electrode 20 Cell

Claims (6)

半導体基板内部に半導体装置構造が作り込まれ、前記半導体装置構造に電気的接触をとるための電極と、外部から前記電極と電気的接触をとるためのゲートパッドとを備え、前記ゲートパッドの下部の前記半導体基板にも前記半導体装置構造が作成された炭化珪素半導体装置であって、
前記半導体装置構造は、
第１導電型の半導体基板と、前記半導体基板上に形成された低不純物濃度の第１導電型の半導体層と、前記第１導電型の半導体層に選択的に形成された高不純物濃度の第２導電型の半導体層と、前記第２導電型の半導体層の表面に形成された低不純物濃度の第２導電型のベース層と、前記ベース層の表面層に選択的に形成された第１導電型のソース領域と、表面から前記ベース層を貫通して前記第１導電型の半導体層に達するように形成された第１導電型のウェル領域と、前記ソース領域と前記ウェル領域とに挟まれた前記ベース層の表面にゲート絶縁膜を介して形成された制御電極とを具備し、
異なるセルのそれぞれの前記第２導電型の半導体層の一部同士が、前記ウェル領域の下の領域で互いに結合され、
前記ゲートパッド部分の前記ソース領域が前記ゲートパッドの部分以外の前記半導体装置構造のソース領域と電気的に結合され、
前記ソース領域が第２導電型領域に覆われ、
ソースパッド部分におけるソースパッド領域に対する前記ソース領域の面積比より、前記ゲートパッド部分におけるゲートパッド領域に対する前記ソース領域の面積比が大きいことを特徴とする炭化珪素半導体装置。 A semiconductor device structure is formed inside a semiconductor substrate, and includes an electrode for making electrical contact with the semiconductor device structure, and a gate pad for making electrical contact with the electrode from the outside, and a lower portion of the gate pad A silicon carbide semiconductor device in which the semiconductor device structure is also formed on the semiconductor substrate,
The semiconductor device structure is:
A first conductivity type semiconductor substrate; a low impurity concentration first conductivity type semiconductor layer formed on the semiconductor substrate; and a high impurity concentration first layer selectively formed on the first conductivity type semiconductor layer. A second conductivity type semiconductor layer; a low conductivity second conductivity type base layer formed on the surface of the second conductivity type semiconductor layer; and a first selectively formed on the surface layer of the base layer. A conductive type source region, a first conductive type well region formed so as to penetrate the base layer from the surface and reach the first conductive type semiconductor layer, and sandwiched between the source region and the well region A control electrode formed on the surface of the base layer through a gate insulating film,
A portion of each of the second conductivity type semiconductor layers of different cells are coupled together in a region below the well region;
The source region of the gate pad portion is electrically coupled to the source region of the semiconductor device structure other than the gate pad portion;
The source region is covered with a second conductivity type region;
A silicon carbide semiconductor device, wherein an area ratio of the source region to the gate pad region in the gate pad portion is larger than an area ratio of the source region to the source pad region in the source pad portion. 前記第１導電型の半導体基板の結晶学的面指数は（０００−１）面に対して平行な面もしくは１０度以内に傾いた面であることを特徴とする請求項１に記載の炭化珪素半導体装置。   2. The silicon carbide according to claim 1, wherein the crystallographic plane index of the semiconductor substrate of the first conductivity type is a plane parallel to a (000-1) plane or a plane tilted within 10 degrees. Semiconductor device. 前記第１導電型の半導体基板の結晶学的面指数は（０００１）面に対して平行な面もしくは１０度以内に傾いた面であることを特徴とする請求項１に記載の炭化珪素半導体装置。   2. The silicon carbide semiconductor device according to claim 1, wherein a crystallographic plane index of the first conductivity type semiconductor substrate is a plane parallel to a (0001) plane or a plane tilted within 10 degrees. . 前記ゲートパッド部分の前記ソース領域が直線状に形成されたことを特徴とする請求項１に記載の炭化珪素半導体装置。   The silicon carbide semiconductor device according to claim 1, wherein the source region of the gate pad portion is formed linearly. 前記ゲートパッド部分の前記ソース領域が多角形の網の目状に形成されたことを特徴とする請求項１に記載の炭化珪素半導体装置。   The silicon carbide semiconductor device according to claim 1, wherein the source region of the gate pad portion is formed in a polygonal mesh pattern. 第１導電型の半導体基板と、前記半導体基板上に形成された低不純物濃度の第１導電型の半導体層と、前記第１導電型の半導体層に選択的に形成された高不純物濃度の第２導電型の半導体層と、前記第２導電型の半導体層の表面に形成された低不純物濃度の第２導電型のベース層と、前記ベース層の表面層に選択的に形成された第１導電型のソース領域と、表面から前記ベース層を貫通して前記第１導電型の半導体層に達するように形成された第１導電型のウェル領域と、前記ソース領域と前記ウェル領域とに挟まれた前記ベース層の表面にゲート絶縁膜を介して形成された制御電極と、を具備し、異なるセルのそれぞれの前記第２導電型の半導体層の一部同士が、前記ウェル領域の下の領域で互いに結合され、前記ゲートパッド部分の前記ソース領域が前記ゲートパッドの部分以外の前記半導体装置構造のソース領域と電気的に結合され、前記ソース領域が第２導電型領域に覆われ、ソースパッド部分におけるソースパッド領域に対する前記ソース領域の面積比より、前記ゲートパッド部分におけるゲートパッド領域に対する前記ソース領域の面積比が大きい炭化珪素半導体装置であって、
前記半導体基板上に前記第１導電型の半導体層をエピタキシャル成長により形成し、
前記第１導電型の半導体層の表面に前記第２導電型の半導体層をイオン注入法により選択的に形成し、
前記第１導電型の半導体層と前記第２導電型の半導体層の上に、前記ベース層をエピタキシャル成長法により形成し、
前記ベース層の表面層に前記ソース領域と、表面から前記ベース層を貫通して前記第１導電型の半導体層に達する前記ウェル領域とをイオン注入法により選択的に形成した
ことを特徴とする炭化珪素半導体装置の製造方法。 A first conductivity type semiconductor substrate; a low impurity concentration first conductivity type semiconductor layer formed on the semiconductor substrate; and a high impurity concentration first layer selectively formed on the first conductivity type semiconductor layer. A second conductivity type semiconductor layer; a low conductivity second conductivity type base layer formed on the surface of the second conductivity type semiconductor layer; and a first selectively formed on the surface layer of the base layer. A conductive type source region, a first conductive type well region formed so as to penetrate the base layer from the surface and reach the first conductive type semiconductor layer, and sandwiched between the source region and the well region A control electrode formed on the surface of the base layer through a gate insulating film, and a part of each of the second conductivity type semiconductor layers of different cells is formed under the well region. Bonded to each other in the region, and the gate pad portion Over scan region is a source region and electrically coupling the semiconductor device structures other than the portion of the gate pad, the source region is covered with the second conductive type region, the source region to the source pad region in the source pad portion A silicon carbide semiconductor device having a larger area ratio of the source region to a gate pad region in the gate pad portion than an area ratio,
Forming the first conductivity type semiconductor layer on the semiconductor substrate by epitaxial growth;
Forming the second conductive type semiconductor layer selectively on the surface of the first conductive type semiconductor layer by ion implantation;
Forming the base layer on the first conductive type semiconductor layer and the second conductive type semiconductor layer by an epitaxial growth method;
The source region in the surface layer of the base layer and the well region that penetrates the base layer from the surface and reaches the semiconductor layer of the first conductivity type are selectively formed by an ion implantation method. A method for manufacturing a silicon carbide semiconductor device.
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