JP6523621B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Semiconductor device and method of manufacturing semiconductor device Download PDF

Info

Publication number
JP6523621B2
JP6523621B2 JP2014126260A JP2014126260A JP6523621B2 JP 6523621 B2 JP6523621 B2 JP 6523621B2 JP 2014126260 A JP2014126260 A JP 2014126260A JP 2014126260 A JP2014126260 A JP 2014126260A JP 6523621 B2 JP6523621 B2 JP 6523621B2
Authority
JP
Japan
Prior art keywords
semiconductor
layer
region
base layer
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014126260A
Other languages
Japanese (ja)
Other versions
JP2016004966A (en
Inventor
明将 木下
明将 木下
保幸 星
保幸 星
原田 祐一
祐一 原田
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP2014126260A priority Critical patent/JP6523621B2/en
Publication of JP2016004966A publication Critical patent/JP2016004966A/en
Application granted granted Critical
Publication of JP6523621B2 publication Critical patent/JP6523621B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a semiconductor device using a wide band gap semiconductor having a wider band gap than silicon as a substrate and a method of manufacturing the semiconductor device.
  Conventionally, silicon (Si) is used as a constituent material of a power semiconductor device that controls high voltage and large current. There are multiple types of power semiconductor devices, such as bipolar transistors, IGBTs (insulated gate bipolar transistors), and MOSFETs (insulated gate field effect transistors), and these are used according to applications.
  For example, bipolar transistors and IGBTs have higher current densities and can be made larger than MOSFETs, but can not be switched at high speed. Specifically, the use of the bipolar transistor is limited at a switching frequency of about several kHz, and the use of an IGBT is limited at a switching frequency of about several tens of kHz. On the other hand, power MOSFETs have lower current density and are difficult to increase in current as compared to bipolar transistors and IGBTs, but high-speed switching operation up to about several MHz is possible.
  However, in the market, there is a strong demand for power semiconductor devices having both high current and high speed, and efforts are being made to improve IGBTs and power MOSFETs, and development is currently progressing to near the material limit. . From the viewpoint of power semiconductor devices, semiconductor materials to replace silicon have been studied, and silicon carbide (SiC) as a semiconductor material capable of producing (manufacturing) next-generation power semiconductor devices excellent in low on voltage, high speed characteristics, and high temperature characteristics. Has attracted attention (see, for example, Non-Patent Document 1 below).
  Silicon carbide is a chemically very stable semiconductor material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. In addition, silicon carbide is expected as a semiconductor material that can sufficiently reduce the on-resistance because the maximum electric field strength is also larger by one digit or more than that of silicon. Such characteristics of silicon carbide also apply to another semiconductor (hereinafter referred to as a wide band gap semiconductor) having a wider band gap than silicon (eg, gallium nitride (GaN)). Therefore, by using the wide band gap semiconductor, the breakdown voltage of the semiconductor device can be increased (see, for example, Non-Patent Document 2 below). In addition, in order to realize resistance reduction, it is general to form a device structure in which a large number of cells are arranged in parallel.
  As a structure in which cells are arranged in parallel, there are a stripe structure in which the cell width is shortened and a long cell is arranged in one direction in order to reduce resistance, and a structure in which cells are arranged in a rectangular or hexagonal pattern. In particular, in a structure in which cells are arranged in a square or hexagonal shape and arranged in a periodic pattern, the area per unit area of a channel or junction FET (JFET) serving as a resistance component can be increased (eg, See Patent Document 1 below).
  However, in a structure in which cells are arranged in a square or hexagonal pattern in a periodic pattern, the JFET is branched to increase the JFET area where the electric field is concentrated. There is a risk of
  FIG. 9B is a plan view showing the configuration of the active portion of the silicon carbide semiconductor device. At the portion of JFET branch 200 employing the hexagonal periodic structure shown in FIG. 9B, an electrical load exceeding the breakdown withstand capacity may be applied, resulting in breakage.
  As a method of avoiding an electric field concentration point formed by such a periodic structure (cell structure), a method of partially connecting cells can be considered (see, for example, Patent Document 2 and Patent Document 3 below).
JP 03-142972 A JP 09-55506 JP 2009-94314 A
K. Shenai, 2 others, Optimum Semiconductors for High-Power Electronics, I Triple E Transactions on Electron Devices (1989), Optimum Semiconductors for High-Power Electronics, 1989 36, No. 9, p. 1811-1823 B. Jayant Baliga, Silicon Carbide Power Devices, (US), World Scientific Publishing Co. (World Scientific Publishing Co.), March 30, 2006, p. . 61-68
  Although Patent Document 2 shows a method in which cells are connected by an n source region and a p base region and the electric field concentration point is filled, the JFET portion is widely designed in a Si based design. Even if an n source region and a p base region for connecting n are added, no significant influence on the structure is observed. However, since the JFET portion is designed to be narrow in SiC having a large electric field breakdown strength, the addition of the n source region and the p base region connecting the cells causes the JFET portion to be largely crushed, which affects the on resistance. For example, in SiC, there is a structure in which cells are connected only by the p base region as shown in the above-mentioned Patent Document 3. However, when JFET is designed with a width of 2 μm, the crossing portion of JFET is diagonally 1 μm p base region And the narrow portion becomes 0.91 μm wide. This width is half or less than 2 μm of the appropriate width, which causes the on resistance to increase. In addition, since the design can not be performed due to the patterning capability of the photolithography process of the SiC process, for example, in the above design example, if the patterning capability is 1 μm, a design of 0.91 μm can not be designed.
  In order to solve the above-mentioned subject, an object of the present invention is to be able to realize a high breakdown voltage without reducing the JFET region which is a resistance component as much as possible.
In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type formed of a wide band gap semiconductor having a wider band gap than silicon, and a band gap formed over the semiconductor substrate. A semiconductor deposition film of a first conductivity type comprising a wide band gap semiconductor having a wide range of impurities and having an impurity concentration lower than that of the semiconductor substrate, and a semiconductor layer of a second conductivity type selectively formed on the surface layer of the semiconductor deposition film. A base layer of a second conductivity type formed on the semiconductor deposition film and the semiconductor layer and having a lower impurity concentration than the semiconductor layer; and a first layer selectively formed on the surface layer of the base layer A source region of a conductivity type, a contact region of a second conductivity type formed in the base layer and having a higher impurity concentration than the base layer, and the base layer penetrated from the surface At least a part of the surface exposed portion of the base layer sandwiched between the source region and the well region of the first conductivity type formed to reach the semiconductor deposited film, and a gate insulating film interposed therebetween And a drain electrode provided on the back surface of the semiconductor substrate, wherein the planar shape of the semiconductor layer is the same as that of the semiconductor layer. The semiconductor layers are periodically arranged in a square shape, and are connected to the adjacent semiconductor layers only at two opposing corner portions of the semiconductor layers, and a plurality of the connected semiconductor layers are spaced apart and the adjacent semiconductor layers are arranged sides are parallel, the base layer, the contact region and the source region is divided into a plurality of cells, possess the well region between said base layers to each other of said different cell, wherein the base Wherein the periphery of the scan layer is surrounded by the well region.
  In addition, an interval between sides of the square of the semiconductor layer is 3 μm or less.
Further, wherein the plurality of pre-xenon Le is hexagonal.
  Further, the wide band gap semiconductor is silicon carbide.
  The crystallographic plane index of the semiconductor substrate is characterized in that it is a plane parallel to (000-1) or a plane inclined within 10 degrees.
In order to achieve the above object, according to a method of manufacturing a semiconductor device of the present invention, a semiconductor substrate of a first conductivity type made of a wide band gap semiconductor having a wider band gap than silicon and silicon formed on the semiconductor substrate A first conductive type semiconductor deposited film made of a wide band gap semiconductor having a wide band gap and having an impurity concentration lower than that of the semiconductor substrate, and a second conductive type selectively formed on the surface layer of the semiconductor deposited film Selectively formed on the surface layer of the base layer, the base layer of the second conductivity type formed on the semiconductor deposition film and the semiconductor layer, and having a lower impurity concentration than the semiconductor layer; The source region of the first conductivity type, the contact region of the second conductivity type formed in the base layer and having a higher impurity concentration than the base layer, and the base from the surface A gate region of at least a portion of a surface exposed portion of the base layer sandwiched between the source region and the well region, and a well region of the first conductivity type formed to penetrate the semiconductor deposition film to reach the semiconductor deposition film Manufacturing a semiconductor device comprising a gate electrode layer provided via a film, a source electrode in common contact with the surfaces of the source region and the contact region, and a drain electrode provided on the back surface of the semiconductor substrate In the method, the planar shape of the semiconductor layer is periodically arranged in a square, and only two opposing corner portions of the semiconductor layer are connected to the adjacent semiconductor layer to separate a plurality of the connected semiconductor layers. and arranged, side of the semiconductor layer adjacent to the parallel, said base layer, said divided source regions and said contact area into a plurality of cells, the base layers to each other of said different cell Said well region is formed, the periphery of the base layer, characterized in that the surrounding in the well region.
  Furthermore, the base layer is formed by epitaxial growth.
  According to the above configuration, there is no branch point causing the decrease in breakdown voltage in the JFET region causing the increase in the on resistance, and no narrow region exists in the width between the JFET regions causing the increase in the on resistance. Low resistance can be maintained.
  According to the present invention, the effects of maintaining high withstand voltage and realizing low resistance are achieved.
It is a sectional view showing the composition of the silicon carbide semiconductor device concerning an embodiment. It is a top view which shows the structure of the silicon carbide semiconductor device concerning embodiment. It is a top view which shows the structure of p base layer of the silicon carbide semiconductor device concerning embodiment. It is a top view which shows the structure of the silicon carbide semiconductor device concerning embodiment. FIG. 5 is a cross-sectional view schematically showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view schematically showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view schematically showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view schematically showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view schematically showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view schematically showing the state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 6 is a plan view showing a configuration of a silicon carbide semiconductor device according to Comparative Example 1; FIG. 16 is a plan view showing a configuration of a silicon carbide semiconductor device according to Comparative Example 2. It is a characteristic view which shows the pressure | voltage resistant characteristic of the silicon carbide semiconductor device concerning an Example.
  Hereinafter, preferred embodiments of a semiconductor device and a method of manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, in the layer or region having n or p, it is meant that electrons or holes are majority carriers, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals and redundant description will be omitted. Further, in the present specification, in the notation of Miller index (crystallographic surface index), "-" means a bar attached to the index immediately thereafter, and it is negative by putting "-" in front of the index. It represents the index.
Embodiment
FIG. 1 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the embodiment. FIG. 2A is a plan view showing the configuration of the silicon carbide semiconductor device according to the embodiment. FIG. 2A is a plan view of the substrate in which the above configuration is removed from the gate insulating film 10 in the active region 101 of FIG. FIG. 2B is a plan view showing the configuration of the p base layer of the silicon carbide semiconductor device according to the embodiment. FIG. 2C is a plan view showing the configuration of the silicon carbide semiconductor device according to the embodiment. AA 'of FIG. 1 is a cross section of AA' of FIG. 2A. Only one of the plurality of active regions 101 shown in FIG. 2A is shown in FIG. Moreover, the pressure-resistant structure part 102 of FIG. 1 is not shown in figure by FIG. The silicon carbide semiconductor device according to the embodiment will be described using a vertical planar gate MOSFET as an example. In the embodiment, the n + -type silicon carbide substrate 1, the n-type silicon carbide epitaxial layer 2 and the p base layer 4 described later are combined to form a silicon carbide semiconductor substrate.
As shown in FIG. 1, in the silicon carbide semiconductor device according to the embodiment, an n-type silicon carbide epitaxial layer 2 is deposited on the main surface of an n + -type silicon carbide substrate 1 to be a drain region. A back electrode 14 is provided on the surface of the n + silicon carbide substrate 1 opposite to the n-type silicon carbide epitaxial layer 2 side (the back surface of the silicon carbide semiconductor substrate). The back surface electrode 14 constitutes a drain electrode.
In the active region 101, a MOS (insulated gate made of metal-oxide film-semiconductor) structure (element structure) is formed on the front surface side of the silicon carbide semiconductor substrate. Specifically, in active region 101, the surface layer of n-type silicon carbide epitaxial layer 2 on the opposite side to the n + -type silicon carbide substrate 1 side (the front surface side of the silicon carbide semiconductor substrate) A + type region (first second conductivity type semiconductor region) 3 is selectively provided. The p + -type region 3 has a rectangular planar shape and is connected to the adjacent p + -type region 3 at two corners 3a facing each other (adjacent to the vertical direction in FIG. 2B) (see FIG. 2B). The p + -type region 3 is doped with, for example, aluminum.
The mutually p + -type region 3, and the adjacent p + -type region 3 sandwiched by n-type silicon carbide epitaxial layer 2 of the surface next to, p-type silicon carbide epitaxial layer (hereinafter referred to as p-base layer, a second A conductive wide band gap semiconductor deposition layer 4 is selectively deposited. The p base layer 4 extends from the active region 101 to the pressure resistant structure 102 and is also deposited on the upper portion of the pressure resistant structure 102. The impurity concentration of the p base layer 4 is lower than the impurity concentration of the p + -type region 3. The p base layer 4 is doped with, for example, aluminum.
An n + source region 5 and ap + contact region 7 are provided in a portion of the p base layer 4 on the p + type region 3. Also, the n + source region 5 and the p + contact region 7 are in contact with each other. The p + contact region 7 is disposed closer to the center of the cell (the cell in which the p + contact region 7 is formed) than the n + source region 5.
Further, an n-well region 9 which penetrates p base layer 4 in the depth direction and reaches n type silicon carbide epitaxial layer 2 is provided in a portion of p base layer 4 on n type silicon carbide epitaxial layer 2 There is. The n-well region 9 constitutes a drift region together with the n-type silicon carbide epitaxial layer 2. The p base layer 4 may be divided into cells by the n well region 9 (see FIG. 2C). An n well region 9 is provided between the p base layers 4 adjacent in the vertical direction in the figure. A gate electrode 11 is provided on the surface of a portion of the p base layer 4 sandwiched by the n + source region 5 and the n well region 9 via a gate insulating film 10. The gate electrode 11 may be provided on the surface of the n well region 9 via the gate insulating film 10.
Here, JFET region 103 is a region obtained by combining the portion of n-type silicon carbide epitaxial layer 2 sandwiched between n-well region 9 and p + -type region 3. The width L of the JFET region 103 is preferably designed to be 3 μm or less. The reason is to reduce the on-resistance and to obtain an ideal withstand voltage.
Interlayer insulating film 12 is provided on the entire front surface side of the silicon carbide semiconductor base so as to cover gate electrode 11. Source electrode 13 is in contact with n + source region 5 and p + contact region 7 through a contact hole opened in interlayer insulating film 12. Source electrode 13 is electrically insulated from gate electrode 11 by interlayer insulating film 12. An electrode pad 15 is provided on the source electrode 13 so as to be in contact with all the source electrodes 13 of all the cells from the active region 101 to the breakdown voltage structure part 102. On the withstand voltage structure portion 102, for example, protection of a passivation film made of polyimide so as to cover an end portion of the electrode pad 15 and an end portion of the source electrode 13 of the cell closest to the withstand pressure structure portion 102 A membrane 16 is provided. The protective film 16 has a discharge prevention function.
The surface layer of n-type silicon carbide epitaxial layer 2 on the side opposite to n + -type silicon carbide substrate 1 in breakdown voltage structure portion 102 is formed of a p-type region. Has a structure to ease the In FIG. 1, a junction termination extension (JTE) structure in which a p-type region 8 is disposed as a withstand voltage structure is used. However, electric field concentration like a floating field limiting ring (FLR) structure in which a plurality of p regions is disposed in a ring Other structures that relax may be used.
  Although only one MOS gate (metal-oxide-semiconductor insulated gate) structure is illustrated in the active region 101 in FIG. 1, a plurality of MOS gate structures may be arranged in parallel.
FIGS. 3-8 is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. For example, the case of producing a MOSFET of a withstand voltage class of 1200 V will be described as an example. First, as shown in FIG. 3, an n + -type silicon carbide substrate 1 doped with nitrogen at an impurity concentration of, for example, about 2 × 10 19 cm −3 is prepared. The front surface of the n + -type silicon carbide substrate 1 may be, for example, a (000-1) surface having an off angle of about 4 degrees in the <11-20> direction. Next, a 10 μm thick n-type silicon carbide epitaxial layer 2 doped with nitrogen at an impurity concentration of 1.0 × 10 16 cm −3 on the (000-1) plane of the n + -type silicon carbide substrate 1 is Grow up.
Next, as shown in FIG. 4, p + -type region 3 is selectively formed in the surface layer of n-type silicon carbide epitaxial layer 2 by photolithography and ion implantation. In this ion implantation, for example, the dopant may be aluminum, and the dose may be set so that the impurity concentration of the p + -type region 3 is 1.0 × 10 18 cm −3 . The width and depth of the p + -type region 3 may be 13 μm and 0.5 μm, respectively. The distance between adjacent p + -type regions 3 may be, for example, 2 μm.
Next, on the surface of n-type silicon carbide epitaxial layer 2, a p-type silicon carbide epitaxial layer to be p base layer 4 is grown with a thickness of 0.5 μm, for example. At this time, for example, a p-type silicon carbide epitaxial layer doped with aluminum may be grown such that the impurity concentration of the p base layer 4 is 5.0 × 10 15 cm −3 .
Next, as shown in FIG. 5, the conductivity type of the portion of p base layer 4 on n type silicon carbide epitaxial layer 2 is reversed by photolithography and ion implantation to selectively form n well region 9. . In this ion implantation, for example, the dopant may be nitrogen and the dose may be set so that the impurity concentration of the n-well region 9 is 5.0 × 10 16 cm −3 . The width and the depth of the n well region 9 may be 2.0 μm and 0.6 μm, respectively.
Next, the outer peripheral portion of the withstand voltage structure portion 102 is removed by a depth of, for example, 0.7 μm by etching so that the base layer 4 remains on the withstand voltage structure portion 102, and the n-type silicon carbide epitaxial layer 2 is exposed. Next, the conductivity type of the portion on n-type silicon carbide epitaxial layer 2 is inverted by photolithography and ion implantation to selectively form p-type region 8 constituting the JTE structure. The width and depth of the p-type region 8 may be 60 μm and 0.5 μm, respectively, the dopant may be aluminum, and the dose may be set so that the impurity concentration is 6.0 × 10 17 cm −3 .
Next, n + source region 5 is selectively formed in the surface layer of the portion on p + type region 3 of p base layer 4 by photolithography and ion implantation. At the same time, channel stopper region 6 is formed in the surface layer of n-type silicon carbide epitaxial layer 2 exposed to breakdown voltage structure portion 102 so as to be disposed outside p-type region 8. Next, p + contact region 7 is selectively formed in the surface layer of the portion on p + type region 3 of p base layer 4 by photolithography and ion implantation. Next, heat treatment (annealing) is performed to activate n + source region 5, channel stopper region 6, p + contact region 7, p type region 8 and n well region 9. The heat treatment temperature and the heat treatment time at this time may be 1620 ° C. and 2 minutes, respectively.
Here, the order of forming the n + source region 5, the channel stopper region 6, the p + contact region 7, the p type region 8 and the n well region 9 can be variously changed.
  Next, as shown in FIG. 6, the front surface side of the silicon carbide semiconductor substrate is thermally oxidized to form a gate insulating film 10 with a thickness of 100 nm. This thermal oxidation may be performed by heat treatment at a temperature of about 1000 ° C. in a mixed atmosphere of oxygen and hydrogen. Thereby, each region formed on the surface of p base layer 4 and n type silicon carbide epitaxial layer 2 is covered with gate insulating film 10.
Next, a polycrystalline silicon layer doped with, for example, phosphorus (P) is formed as the gate electrode 11 on the gate insulating film 10. Next, the polycrystalline silicon layer is patterned and selectively removed, leaving the polycrystalline silicon layer on the portion of p base layer 4 sandwiched between n + source region 5 and n well region 9. At this time, a polycrystalline silicon layer may be left on n well region 9. Next, for example, phosphosilicate glass (PSG) is formed to a thickness of 1.0 μm as the interlayer insulating film 12 so as to cover the gate insulating film 10.
Next, as shown in FIG. 7, the interlayer insulating film 12 and the gate insulating film 10 are patterned and selectively removed to form a contact hole, and the n + source region 5 and the p + contact region 7 are exposed. Next, heat treatment (reflow) for planarizing the interlayer insulating film 12 is performed.
Next, as shown in FIG. 8, for example, a nickel film serving as source electrode 13 on the front surface of the silicon carbide semiconductor substrate so as to be in contact with n + source region 5 and p + contact region 7 exposed to the contact holes. (Hereinafter, the case where a nickel film is formed will be described as an example) is formed. Next, a nickel film to be the source electrode 13 is left in the contact holes by photolithography and etching. Next, for example, a nickel film to be the lowermost layer of back electrode 14 (hereinafter, the case where a nickel film is formed will be described as an example) on the entire back surface of n + silicon carbide substrate 1 (back surface of silicon carbide semiconductor substrate). To form a film.
  Then, heat treatment is performed, for example, at a temperature of 970 ° C. to cause the nickel film on both sides of the substrate to react with the silicon carbide semiconductor portion to form a nickel silicide film as the lowermost layer of the source electrode 13 and the back electrode 14 on both sides of the substrate. Form an ohmic junction with the silicon carbide semiconductor portion. Next, an electrode pad 15 is deposited on the entire front surface of the silicon carbide semiconductor substrate by, for example, sputtering. The thickness of the portion of the electrode pad 15 on the interlayer insulating film 12 may be, for example, 5 μm. The electrode pad 15 may be made of, for example, aluminum (Al-Si) containing silicon at a ratio of 1%.
  Next, polyimide is applied to the entire surface as a protective film 16, and then a film is formed selectively to cover the interlayer insulating film 12 and a part of the electrode pad 15 by photolithography and etching. Next, on the nickel silicide film on the back surface of the silicon carbide semiconductor substrate, for example, titanium, nickel and gold (Au) are formed as the back surface electrode 14 in this order to form a MOSFET having a cross section shown in FIG. Complete.
(Example)
Next, the structure in which the JFET regions described in the above-described embodiment are arranged in a straight line in plan view, the structure in which the JFET regions are periodically arranged in hexagons, and the zigzag structure (rectangular p + -type regions 3 are connected at corner 3 a Voltage resistance and on-resistance characteristics of the structure arranged in a zigzag structure).
  FIG. 9 is a plan view showing the configuration of the active region of the silicon carbide semiconductor device according to the comparative example, and FIG. 9A is a plan view showing the configuration of the active region of the silicon carbide semiconductor device with the stripe structure of comparative example 1. . FIG. 9B is a plan view showing the configuration of the active region of the silicon carbide semiconductor device of the hexagonal cell structure of Comparative Example 2.
  First, as an example, the MOSFET described in the above-described embodiment was manufactured. Specifically, it has the structure of the cross-sectional view shown in FIG. 1, and the JFET region 103 has a zigzag structure as shown in FIG. 2A in plan view.
Further, as a comparative example, a stripe structure (comparative example 1) in which the JFET region 103 shown in FIG. 9A is straight and a hexagonal cell structure (comparative example 2) in which the JFET region 103 shown in FIG. , Usually striped structure and hexagonal cell structure). The configurations other than the arrangement condition of the surface of the embodiment and the comparative examples 1 and 2 are the same. Specifically, the concentration of the n-type silicon carbide epitaxial layer 2 is 1 × 10 16 cm −3 and the thickness is 10 μm.
  FIG. 10 is a characteristic diagram showing the pressure resistance characteristics of the silicon carbide semiconductor device according to the example. The breakdown voltage and the on-resistance characteristic of the silicon carbide semiconductor devices of the example and the comparative examples 1 and 2 are shown. As shown in FIG. 10, although there is sufficient withstand voltage in the stripe structure (comparative example 1), the on resistance is large, but in the hexagonal cell structure (comparative example 2), the on resistance is reduced but the withstand voltage is also reduced. On the other hand, in the zigzag structure of the example, it could be confirmed that the on-resistance can be lowered while maintaining the same withstand voltage as the stripe structure.
  As described above, by arranging the JFET region of the silicon carbide substrate in a zigzag structure having a constant width, there is no branch point causing the breakdown voltage reduction in the JFET region causing the increase in the on resistance, and the on resistance High breakdown voltage and low resistance can be maintained because there is no narrow region in the width between the JFET regions that cause the increase.
  In the present invention, the case where the front surface of the silicon carbide substrate made of silicon carbide is the (000-1) plane and the MOS gate structure is formed on the (000-1) plane has been described above as an example. The present invention is not limited to this, and various changes can be made to the plane orientation of the main surface of the substrate, the wide band gap semiconductor material that constitutes the substrate, and the like. For example, a semiconductor substrate made of a wide band gap semiconductor such as gallium nitride (GaN) may be formed with the front surface of a silicon carbide substrate as a (0001) surface and a MOS gate structure formed on the (0001) surface. May be used.
In the present invention, the low concentration p -- type layer is formed by epitaxial growth, but may be formed by ion implantation.
  Further, in the present invention, the vertical MOSFET is described as an example, but the present invention is not limited to the above embodiment, and can be applied to semiconductor devices of various configurations provided with a JFET structure.
  As described above, the semiconductor device and the method of manufacturing the semiconductor device according to the present invention are useful for a high breakdown voltage semiconductor device used for a power conversion device or a power supply device such as various industrial machines.
1 n + type silicon carbide substrate 2 n type silicon carbide epitaxial layer 3 p + type region 4 p base layer 5 n + source region 6 channel stopper 7 p + contact region 8 JTE structure 9 n well region 10 gate insulating film 11 gate electrode 12 interlayer insulating film 13 source electrode 14 back surface electrode 15 electrode pad 16 protective film 101 active region 102 withstand voltage structure portion 103 JFET region 200 JFET branch portion of hexagonal cell structure

Claims (7)

  1. A semiconductor substrate of a first conductivity type made of a wide band gap semiconductor having a wider band gap than silicon;
    A semiconductor deposition film of a first conductivity type formed of a wide band gap semiconductor having a wider band gap than silicon and having a lower impurity concentration than the semiconductor substrate, formed on the semiconductor substrate;
    A semiconductor layer of a second conductivity type selectively formed on the surface layer of the semiconductor deposited film;
    A second conductivity type base layer formed on the semiconductor deposition film and the semiconductor layer, having a lower impurity concentration than the semiconductor layer;
    A source region of a first conductivity type selectively formed in the surface layer of the base layer;
    A contact region of a second conductivity type formed in the base layer and having a higher impurity concentration than the base layer;
    A well region of a first conductivity type formed to penetrate the base layer from the surface to reach the semiconductor deposited film;
    A gate electrode layer provided via a gate insulating film on at least a part of a surface exposed portion of the base layer sandwiched between the source region and the well region;
    A source electrode commonly in contact with surfaces of the source region and the contact region;
    A drain electrode provided on the back surface of the semiconductor substrate;
    Equipped with
    The planar shape of the semiconductor layer is periodically arranged in a square shape, and only two opposing corner portions of the semiconductor layer are connected to the adjacent semiconductor layer, and a plurality of the connected semiconductor layers are spaced apart is, the sides of the semiconductor layer adjacent are parallel,
    The base layer, the contact region and the source region is divided into a plurality of cells, possess the well region between said base layers to each other of said different cell, that around the base layer is surrounded by the well region A semiconductor device to be characterized.
  2.   The semiconductor device according to claim 1, wherein an interval between sides of the square of the semiconductor layer is 3 μm or less.
  3.   The semiconductor device according to claim 1, wherein the plurality of cells are hexagonal.
  4.   The semiconductor device according to any one of claims 1 to 3, wherein the wide band gap semiconductor is silicon carbide.
  5.   5. The semiconductor device according to claim 4, wherein a crystallographic plane index of the semiconductor substrate is a plane parallel to (000-1) or a plane inclined within 10 degrees.
  6. A semiconductor substrate of a first conductivity type formed of a wide band gap semiconductor having a wider band gap than silicon, and a wide band gap semiconductor formed on the semiconductor substrate and having a wider band gap than silicon and greater than the semiconductor substrate The semiconductor deposition film of the first conductivity type having a low impurity concentration, the semiconductor layer of the second conductivity type selectively formed on the surface layer of the semiconductor deposition film, and the semiconductor deposition film and the semiconductor layer The second conductive type base layer having a lower impurity concentration than the semiconductor layer, the first conductive type source region selectively formed on the surface layer of the base layer, and the base layer A contact region of a second conductivity type having an impurity concentration higher than that of the base layer, and a first formed from the surface to penetrate the base layer to reach the semiconductor deposition film A gate electrode layer provided via a gate insulating film on at least a part of a surface exposed portion of the base layer sandwiched between the source region and the well region; A method of manufacturing a semiconductor device, comprising: a source electrode in common contact with a surface of a contact region; and a drain electrode provided on the back surface of the semiconductor substrate,
    The planar shape of the semiconductor layer is periodically arranged in a square, and only two opposing corner portions of the semiconductor layer are connected to the adjacent semiconductor layer, and a plurality of the connected semiconductor layers are spaced apart The sides of the adjacent semiconductor layers are parallel, the base layer, the source region and the contact region are divided into a plurality of cells, and the well region is formed between the base layers of different cells , A method of manufacturing a semiconductor device, wherein a periphery of a base layer is surrounded by the well region .
  7.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the base layer is formed by epitaxial growth.
JP2014126260A 2014-06-19 2014-06-19 Semiconductor device and method of manufacturing semiconductor device Active JP6523621B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014126260A JP6523621B2 (en) 2014-06-19 2014-06-19 Semiconductor device and method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014126260A JP6523621B2 (en) 2014-06-19 2014-06-19 Semiconductor device and method of manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JP2016004966A JP2016004966A (en) 2016-01-12
JP6523621B2 true JP6523621B2 (en) 2019-06-05

Family

ID=55224015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014126260A Active JP6523621B2 (en) 2014-06-19 2014-06-19 Semiconductor device and method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP6523621B2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112011101442T5 (en) * 2010-04-26 2013-04-25 Mitsubishi Electric Corporation Semiconductor device
WO2013080641A1 (en) * 2011-12-01 2013-06-06 三菱電機株式会社 Semiconductor device
JP6074787B2 (en) * 2012-05-25 2017-02-08 国立研究開発法人産業技術総合研究所 Silicon carbide semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JP2016004966A (en) 2016-01-12

Similar Documents

Publication Publication Date Title
US10461077B2 (en) Method of manufacturing a semiconductor device
JP6049784B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
US10062758B2 (en) Semiconductor device
JP5992094B2 (en) Semiconductor device
US10714609B2 (en) Semiconductor device with stripe-shaped trench gate structures, transistor mesas and diode mesas
US9041173B2 (en) Semiconductor device
JP5617175B2 (en) Wide band gap semiconductor device and manufacturing method thereof
US7750377B2 (en) Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors
US7781786B2 (en) Semiconductor device having a heterojunction diode and manufacturing method thereof
JP5177151B2 (en) Silicon carbide semiconductor device
US9419133B2 (en) Semiconductor device and fabrication method of semiconductor device
US9184238B2 (en) Vertical-channel type junction SiC power FET and method of manufacturing same
JP4921880B2 (en) High voltage semiconductor device
EP1204145B1 (en) Semiconductor element
US9472403B2 (en) Power semiconductor switch with plurality of trenches
CN102947934B (en) Power semiconductor
JP5011681B2 (en) Semiconductor device
US9673313B2 (en) Silicon carbide semiconductor device and fabrication method thereof
US8198676B2 (en) P-channel silicon carbide MOSFET
JP5433352B2 (en) Manufacturing method of semiconductor device
US9136371B2 (en) Monolithic bidirectional silicon carbide switching devices
WO2010116575A1 (en) Semiconductor device and method of producing semiconductor device
JP2012059943A (en) Semiconductor device
WO2012127821A1 (en) Semiconductor device and method for producing same
JP5002693B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170515

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170926

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171127

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20180306

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180605

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20180613

A912 Removal of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20180629

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190426

R150 Certificate of patent or registration of utility model

Ref document number: 6523621

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150