CN114792721A - Silicon controlled transient voltage suppressor with high maintaining voltage and manufacturing method thereof - Google Patents
Silicon controlled transient voltage suppressor with high maintaining voltage and manufacturing method thereof Download PDFInfo
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- 230000001052 transient effect Effects 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 7
- 229910052710 silicon Inorganic materials 0.000 title description 6
- 239000010703 silicon Substances 0.000 title description 6
- 238000002347 injection Methods 0.000 claims abstract description 223
- 239000007924 injection Substances 0.000 claims abstract description 223
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 230000000149 penetrating effect Effects 0.000 claims abstract description 27
- 238000002513 implantation Methods 0.000 claims description 95
- 230000001629 suppression Effects 0.000 claims description 44
- 238000005468 ion implantation Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 30
- 239000007943 implant Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 4
- 238000012423 maintenance Methods 0.000 abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000003071 parasitic effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The invention relates to the technical field of semiconductor devices, and particularly discloses a thyristor transient voltage suppressor with high maintenance voltage, wherein the thyristor transient voltage suppressor comprises: a second conductive type substrate, a first conductive type epitaxial layer; a first conductive type well region and a second conductive type well region are arranged in the first conductive type epitaxial layer; a first N + injection region and a first P + injection region are arranged in the first conductive type well region; a second N + injection region and a second P + injection region are arranged in the second conductive type well region; forming a first conductive type buried layer at the junction position of the first conductive type epitaxial layer and the second conductive type substrate; at least one first groove penetrating through the second conductive type well region is formed at the edge position of the second N + injection region close to the first P + injection region, and the bottom end of the first groove extends into the first conductive type buried layer. The invention also discloses a manufacturing method. The thyristor transient voltage suppressor with high maintenance voltage provided by the invention effectively improves the surge protection capability.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a thyristor transient voltage suppression device with high maintenance voltage and a manufacturing method of the thyristor transient voltage suppression device with high maintenance voltage.
Background
A Transient Voltage Suppressor (TVS) is a necessary surge protection device in system applications, and applications of various TVS are different. In high voltage power line systems, TVS devices with a holding voltage Vh higher than the supply voltage and with high inrush current are often required. TVS is usually implemented by diode strings, which have high clamping voltage and weak protection capability, and require a large area.
Therefore, how to provide a tvs diode device with high holding voltage to improve the protection capability is an urgent technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a thyristor transient voltage suppressor with high maintenance voltage and a manufacturing method of the thyristor transient voltage suppressor with high maintenance voltage, and solves the problem of surge protection capability in the related technology.
As a first aspect of the present invention, there is provided a thyristor transient voltage suppression device having a high sustain voltage, comprising:
the epitaxial layer comprises a second conductive type substrate and a first conductive type epitaxial layer arranged on the second conductive type substrate;
a first conductive type well region and a second conductive type well region are arranged in the first conductive type epitaxial layer, and the first conductive type well region and the second conductive type well region are arranged at intervals;
a first N + injection region and a first P + injection region are arranged in the first conductive type well region, and the first N + injection region and the first P + injection region are arranged at intervals;
a second N + injection region and a second P + injection region are arranged in the second conductive type well region, and the second N + injection region and the second P + injection region are arranged at intervals;
the first P + injection region is close to the second N + injection region;
a first conductive type buried layer is formed at the junction position of the first conductive type epitaxial layer and the second conductive type substrate and is positioned below the second conductive type well region;
at least one first trench penetrating through the second conductive type well region is formed in the second N + injection region close to the edge of the first P + injection region, and the bottom end of the first trench extends into the first conductive type buried layer;
the first N + injection region and the first P + injection region are connected to form an anode contact, and the second N + injection region and the second P + injection region are connected to form a cathode contact.
Further, the ion implantation concentration of the first conductive type buried layer is 1 x 10 15 cm -3 ~5*10 16 cm -3 In between.
Further, the thickness of the first conduction type epitaxial layer is 5-20 μm.
Furthermore, the ion implantation concentration of the first conductive type well region is 1 × 10 13 cm -3 ~1*10 15 cm -3 The ion implantation concentration of the second conduction type well region is 1 x 10 13 cm -3 ~5*10 16 cm -3 In the meantime.
Furthermore, the carrier density of the first N + injection region, the second N + injection region, the first P + injection region and the second P + injection region is all 1 x 10 15 cm -3 ~5*10 16 cm -3 In the meantime.
As another aspect of the present invention, there is provided a thyristor transient voltage suppression device having a high sustain voltage, comprising:
a second conductive type substrate, and a second conductive type epitaxial layer disposed on the second conductive type substrate;
a first conductive type well region and a second conductive type well region are arranged in the second conductive type epitaxial layer, and the first conductive type well region and the second conductive type well region are arranged at intervals;
a first N + injection region and a first P + injection region are arranged in the first conductive type well region, and the first N + injection region and the first P + injection region are arranged at intervals;
a second N + injection region and a second P + injection region are arranged in the second conductive type well region, and the second N + injection region and the second P + injection region are arranged at intervals;
the first P + injection region is close to the second N + injection region;
a second conductive type buried layer is formed at the junction position of the second conductive type epitaxial layer and the second conductive type substrate and is positioned below the first conductive type well region;
at least one second groove penetrating through the first conductive type well region is formed at the edge position of the first P + injection region, which is close to the second N + injection region, and the bottom end of the second groove extends into the second conductive type buried layer;
the first N + injection region and the first P + injection region are connected to form an anode contact, and the second N + injection region and the second P + injection region are connected to form a cathode contact.
As another aspect of the present invention, there is provided a thyristor transient voltage suppression device having a high sustain voltage, comprising:
a second conductive type substrate, and a second conductive type epitaxial layer disposed on the second conductive type substrate;
a first conductive type well region and a second conductive type well region are arranged in the second conductive type epitaxial layer, and the first conductive type well region and the second conductive type well region are arranged at intervals;
a first N + injection region and a first P + injection region are arranged in the first conductive type well region, and the first N + injection region and the first P + injection region are arranged at intervals;
a second N + injection region and a second P + injection region are arranged in the second conductive type well region, and the second N + injection region and the second P + injection region are arranged at intervals;
the first P + injection region is close to the second N + injection region;
forming first conductive type buried layers and second conductive type buried layers which are arranged at intervals at the junction position of the second conductive type epitaxial layer and the second conductive type substrate, wherein the first conductive type buried layers are positioned below the second conductive type well region, and the second conductive type buried layers are positioned below the first conductive type well region;
at least one first trench penetrating through the second conductive type well region is formed in the second N + injection region close to the edge of the first P + injection region, and the bottom end of the first trench extends into the first conductive type buried layer;
at least one second groove penetrating through the first conductive type well region is formed at the edge position of the first P + injection region, which is close to the second N + injection region, and the bottom end of the second groove extends into the second conductive type buried layer;
the first N + injection region and the first P + injection region are connected to form an anode contact, and the second N + injection region and the second P + injection region are connected to form a cathode contact.
As another aspect of the present invention, there is provided a method for manufacturing a thyristor transient voltage suppression device with a high sustain voltage, for manufacturing the thyristor transient voltage suppression device with a high sustain voltage, wherein the method comprises:
providing a second conductive type substrate;
growing a first conductive type epitaxial layer on the second conductive type substrate;
forming a first conductive type buried layer at the junction position of the first conductive type epitaxial layer and the second conductive type substrate in an ion implantation mode;
forming a first conductive type well region and a second conductive type well region which are arranged at intervals on the surface of the first conductive type epitaxial layer, which is far away from the second conductive type substrate, in an ion implantation mode, wherein the second conductive type well region is positioned above the first conductive type buried layer;
performing N + injection and P + injection in the first conductivity type well region to form a first N + injection region and a first P + injection region which are arranged at intervals, and performing N + injection and P + injection in the second conductivity type well region to form a second N + injection region and a second P + injection region which are arranged at intervals, wherein the first P + injection region is close to the second N + injection region;
manufacturing at least one first trench penetrating through the second conductive type well region at the edge position of the second N + injection region close to the first P + injection region, wherein the bottom end of the first trench extends into the first conductive type buried layer;
and connecting the first N + injection region and the first P + injection region to form an anode contact, and connecting the second N + injection region and the second P + injection region to form a cathode contact.
As another aspect of the present invention, there is provided a method for manufacturing a thyristor transient voltage suppression device with a high sustain voltage, for manufacturing the thyristor transient voltage suppression device with a high sustain voltage, wherein the method comprises:
providing a second conductive type substrate;
growing a second conductive type epitaxial layer on the second conductive type substrate;
forming a second conductive type buried layer at the junction position of the second conductive type epitaxial layer and the second conductive type substrate in an ion implantation mode;
forming a first conductive type well region and a second conductive type well region which are arranged at intervals on the surface of the second conductive type epitaxial layer, which is far away from the second conductive type substrate, in an ion implantation mode, wherein the first conductive type well region is positioned above the second conductive type buried layer;
performing N + injection and P + injection in the first conductivity type well region to form a first N + injection region and a first P + injection region which are arranged at intervals, and performing N + injection and P + injection in the second conductivity type well region to form a second N + injection region and a second P + injection region which are arranged at intervals, wherein the first P + injection region is close to the second N + injection region;
at least one second groove penetrating through the first conductive type well region is manufactured at the edge position of the first P + injection region close to the second N + injection region, and the bottom end of the second groove extends into the second conductive type buried layer;
and connecting the first N + injection region and the first P + injection region to form an anode contact, and connecting the second N + injection region and the second P + injection region to form a cathode contact through metal.
As another aspect of the present invention, a method for manufacturing a thyristor transient voltage suppression device with a high holding voltage is provided, for manufacturing the thyristor transient voltage suppression device with a high holding voltage, where the method includes:
providing a second conductive type substrate;
growing a second conductive type epitaxial layer on the second conductive type substrate;
forming a first conductive type buried layer and a second conductive type buried layer which are arranged at intervals at the junction position of the second conductive type epitaxial layer and the second conductive type substrate in an ion implantation mode;
forming a first conductive type well region and a second conductive type well region which are arranged at intervals on the surface of the second conductive type epitaxial layer, which is far away from the second conductive type substrate, in an ion implantation mode, wherein the first conductive type well region is positioned above the second conductive type buried layer, and the second conductive type well region is positioned above the first conductive type buried layer;
performing N + injection and P + injection in the first conductivity type well region to form a first N + injection region and a first P + injection region which are arranged at intervals, and performing N + injection and P + injection in the second conductivity type well region to form a second N + injection region and a second P + injection region which are arranged at intervals, wherein the first P + injection region is close to the second N + injection region;
forming at least one first trench penetrating through the second conductivity type well region at an edge position of the second N + implantation region close to the first P + implantation region, and a bottom end of the first trench extends into the first conductivity type buried layer, and forming at least one second trench penetrating through the first conductivity type well region at an edge position of the first P + implantation region close to the second N + implantation region, and a bottom end of the second trench extends into the second conductivity type buried layer;
and connecting the first N + injection region and the first P + injection region to form an anode contact, and connecting the second N + injection region and the second P + injection region to form a cathode contact.
The thyristor transient voltage suppression device with high maintenance voltage greatly reduces the positive feedback of the thyristor structure through the matching of the groove and the buried layer, effectively improves the surge protection capability and realizes the target of high maintenance voltage. Meanwhile, because the device has high compatibility with the traditional process, the device can be used as a TVS discrete device independently and can be integrated with a related integrated circuit, thereby being oriented to on-chip protection.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic diagram of a transient suppression diode device in the prior art.
Fig. 2 is a schematic structural diagram of an embodiment of a scr transient voltage suppressor with a high sustain voltage according to the present invention.
Fig. 3 is a schematic structural diagram of another embodiment of the scr transient voltage suppression device with high holding voltage according to the present invention.
Fig. 4 is a schematic structural diagram of another embodiment of the scr transient voltage suppressor with high holding voltage according to the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make those skilled in the art better understand the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
For surge protection, the SCR structure is a reliable device that can be used for low voltage power supply or small signal surge protection designs rather than high voltage due to the limitations of the low holding voltage Vh characteristic of the SCR, as shown in fig. 1. Therefore, the invention provides a transient voltage suppression device which has high maintaining voltage characteristic and is based on a silicon controlled rectifier structure, the transient voltage suppression device can improve the maintaining voltage through a groove and an epitaxial technology, and meanwhile, the transient voltage suppression device can be integrated in an ESD device as a latch-up (latch-up) in an integrated circuit manufacturing process with a groove and an epitaxial process flow.
As a specific embodiment of the present invention, as shown in fig. 2, there is provided a thyristor transient voltage suppression device having a high sustain voltage, comprising:
a second conductivity type substrate 22, and a first conductivity type epitaxial layer 21 disposed on the second conductivity type substrate 22;
a first conductivity type well region 11 and a second conductivity type well region 12 are arranged in the first conductivity type epitaxial layer 21, and the first conductivity type well region 11 and the second conductivity type well region 12 are arranged at intervals;
a first N + injection region 111 and a first P + injection region 112 are disposed in the first conductive type well region 11, and the first N + injection region 111 and the first P + injection region 112 are disposed at an interval;
a second N + implantation region 121 and a second P + implantation region 122 are disposed in the second conductive type well region 12, and the second N + implantation region 121 and the second P + implantation region 122 are disposed at an interval;
the first P + implant region 112 is close to the second N + implant region 121;
a first conductivity type buried layer 31 is formed at the boundary position of the first conductivity type epitaxial layer 21 and the second conductivity type substrate 22, and the first conductivity type buried layer 31 is located below the second conductivity type well region 12;
at least one first trench 30 penetrating through the second conductive type well region 12 is formed in the second N + implantation region 121 near the edge of the first P + implantation region 112, and the bottom end of the first trench 30 extends into the first conductive type buried layer 31;
the first N + implantation region 111 and the first P + implantation region 112 are connected to form an anode contact 41, and the second N + implantation region 121 and the second P + implantation region 122 are connected to form a cathode contact 42.
According to the thyristor transient voltage suppression device with high maintenance voltage provided by the embodiment of the invention, the first conduction type buried layer positioned below the second conduction type well region is formed at the junction position of the first conduction type epitaxial layer and the second conduction type substrate, and the first groove is formed to change the current path, so that more holes or electrons are compounded through the first conduction type buried layer, the current gain of a parasitic PNP (plug-and-play) transistor is effectively reduced, the length of the current path of the thyristor structure is increased, and the effect of effectively improving the maintenance voltage of the thyristor on the premise of not changing the size of the transient suppression diode device is achieved.
It should be noted that, taking the direction shown in fig. 2 as an example, the position of the second N + implantation region 121 close to the edge of the first P + implantation region 112 herein can be specifically understood as a position tangential to the left edge of the second N + implantation region 121.
In the embodiment of the present invention, the first conductivity type may be specifically an N type, and the second conductivity type may be specifically a P type, so that the first conductivity type epitaxial layer 21 includes an N type epitaxial layer, the second conductivity type substrate 22 includes a P type substrate, the first conductivity type well region 11 includes an N type well region, the second conductivity type well region 12 includes a P type well region, and the first conductivity type buried layer 31 includes an N type buried layer.
Specifically, the first conductive type buried layer 31 may be a high-concentration buried layer carrier recombination region, and the ion implantation concentration of the first conductive type buried layer is 1 × 10 15 cm -3 ~5*10 16 cm -3 In the meantime.
Specifically, the thickness of the first conductive type epitaxial layer 21 is between 5 μm and 20 μm.
In the embodiment of the invention, the thickness of the N-type epitaxial layer can be between 5 μm and 20 μm.
Specifically, the ion implantation concentration of the first conductivity type well region is 1 × 10 13 cm -3 ~1*10 15 cm -3 The ion implantation concentration of the second conductive type well region is 1 x 10 13 cm -3 ~5*10 16 cm -3 In between.
In the embodiment of the present invention, the ion implantation concentration of the N-well may be 1 × 10 13 cm -3 ~1*10 15 cm -3 Meanwhile, the ion implantation concentration of the P-type well region is 1 x 10 13 cm -3 ~5*10 16 cm -3 In the meantime.
It should be understood that ion implantation is a process, and in the embodiment of the present invention, the implanted ions may be determined by many types, and may specifically be determined according to the selected conductivity type, and are not limited herein.
Specifically, the carrier density of the first N + injection region, the second N + injection region, the first P + injection region and the second P + injection region is 1 x 10 15 cm -3 ~5*10 16 cm -3 In between.
As another embodiment of the present invention, a method for manufacturing a scr transient voltage suppressor having a high sustain voltage as shown in fig. 2 is provided, where the method includes:
providing a second conductivity type substrate 22;
growing a first conductive type epitaxial layer 21 on the second conductive type substrate 22;
forming a first conductive type buried layer 31 at the boundary position of the first conductive type epitaxial layer 21 and the second conductive type substrate 22 by means of ion implantation;
forming a first conductivity type well region 11 and a second conductivity type well region 12 which are arranged at intervals on the surface of the first conductivity type epitaxial layer 21 away from the second conductivity type substrate 22 by means of ion implantation, wherein the second conductivity type well region 12 is located above the first conductivity type buried layer 31;
performing N + implantation and P + implantation in the first conductivity type well region 11 to form a first N + implantation region 111 and a first P + implantation region 112 which are arranged at an interval, and performing N + implantation and P + implantation in the second conductivity type well region 12 to form a second N + implantation region 121 and a second P + implantation region 122 which are arranged at an interval, wherein the first P + implantation region 112 is close to the second N + implantation region 121;
forming at least one first trench 30 penetrating through the second conductive type well region 12 at a position of the second N + implantation region 121 close to the edge of the first P + implantation region 112, and a bottom end of the first trench 30 extends into the first conductive type buried layer 31;
the first N + implantation region 111 and the first P + implantation region 112 are connected to form an anode contact 41, and the second N + implantation region 121 and the second P + implantation region 122 are connected to form a cathode contact 42.
As described above, the first conductive type may specifically be an N type, and the second conductive type may specifically be a P type in the embodiment of the present invention, and therefore, as a specific implementation manner of the present invention, the manufacturing method may specifically include the following steps:
growing an N-type epitaxial layer with the thickness of 5-20 mu m and the substrate resistivity of 0.05-50 ohm.cm above a P substrate;
step two, implanting ions 1 x 10 at the junction position of the N-type epitaxial layer and the P substrate 15 cm -3 ~5*10 16 cm -3 The high-concentration N-type buried layer;
step three, taking the direction shown in fig. 2 as an example, 1 × 10 ions are implanted into the left side of the surface of the N-type epitaxial layer 13 cm -3 ~1*10 15 cm -3 Forming an N-type well region;
step four, taking the direction shown in fig. 2 as an example, 1 × 10 ions are implanted into the right side of the surface of the N-type epitaxial layer 13 cm -3 ~5*10 16 cm -3 The P-type trap is formed on the P-type buried layer and is positioned above the N-type buried layer;
step five, respectively carrying out N + injection and P + injection in the N-type trap region and the P-type trap region, wherein the density of carriers is 1 x 10 15 cm -3 ~5*10 16 cm -3 And the N + implant is always located to the left of the P + implant (taking the direction shown in fig. 2 as an example);
taking the direction shown in fig. 2 as an example, at least one first trench (specifically, a deep trench) is formed in the left edge of the N + injection region of the P-type well region, and the lower end of the deep trench is located in the N-type buried layer;
and seventhly, respectively connecting the N + injection region and the P + injection region in the N-type well region and the P-type well region through metal to form an anode contact 41 and a cathode contact 42 of the device respectively.
As another specific embodiment of the present invention, as shown in fig. 3, there is provided a thyristor transient voltage suppression device having a high sustain voltage, including:
a second conductive-type substrate 22, and a second conductive-type epitaxial layer 24 disposed on the second conductive-type substrate 22;
a first conductivity type well region 11 and a second conductivity type well region 12 are arranged in the second conductivity type epitaxial layer 24, and the first conductivity type well region 11 and the second conductivity type well region 12 are arranged at an interval;
a first N + injection region 111 and a first P + injection region 112 are disposed in the first conductive type well region 11, and the first N + injection region 111 and the first P + injection region 112 are disposed at an interval;
a second N + implantation region 121 and a second P + implantation region 122 are disposed in the second conductive type well region 12, and the second N + implantation region 121 and the second P + implantation region 122 are disposed at an interval;
the first P + implantation region 112 is close to the second N + implantation region 121;
a second conductive type buried layer 32 is formed at the interface position of the second conductive type epitaxial layer 24 and the second conductive type substrate 22, and the second conductive type buried layer 32 is located below the first conductive type well region 11;
at least one second trench 33 penetrating through the first conductive type well region 11 is formed at a position of the first P + implantation region 112 close to the edge of the second N + implantation region 121, and a bottom end of the second trench 33 extends into the second conductive type buried layer 32;
the first N + implantation region 111 and the first P + implantation region 112 are connected to form an anode contact 41, and the second N + implantation region 121 and the second P + implantation region 122 are connected to form a cathode contact 42.
It should be understood that this embodiment replaces the first conductivity type epitaxial layer 21 by the second conductivity type epitaxial layer 24 and the first conductivity type buried layer 31 by the second conductivity type buried layer 32, and the position of the second conductivity type buried layer 32 is moved to below the first conductivity type well region 11 while the second trench 33 is made at the edge position of the first P + region, as compared to the previous embodiment, and the other structure is kept unchanged.
Therefore, in the thyristor transient voltage suppression device with high sustain voltage provided by the embodiment of the present invention, the second conductive type buried layer located below the first conductive type well region is formed at the boundary position of the second conductive type epitaxial layer and the second conductive type substrate, and the second trench is formed to change the current path, so that more holes or electrons are compounded through the second conductive type buried layer, the current gain of the parasitic NPN transistor is effectively reduced, the length of the current path of the thyristor structure is increased, and the effect of effectively increasing the sustain voltage of the thyristor on the premise of not changing the size of the transient suppression diode device is achieved.
As described above, in the embodiment of the present invention, the first conductivity type may be specifically N-type, and the second conductivity type may be specifically P-type, so that the second conductivity type epitaxial layer 24 includes a P-type epitaxial layer, the second conductivity type substrate 22 includes a P-type substrate, the first conductivity type well region 11 includes an N-type well region, the second conductivity type well region 12 includes a P-type well region, and the second conductivity type buried layer 32 includes a P-type buried layer.
Therefore, in the thyristor transient voltage suppression device with high sustain voltage provided by the embodiment of the invention, when the gain of the parasitic transistor is reduced, the positive feedback of the thyristor structure is blocked, and the sustain voltage Vh under the pulse is increased. The second groove is arranged, so that the shortest path of the silicon controlled structure is blocked, the current of the silicon controlled structure is enabled to bypass the groove and pass through the P-type buried layer, and the concentration of the P-type buried layer is far higher than that of the P-type epitaxial layer and the P-type well region, so that electrons are greatly compounded at the P-type buried layer, the gain of the parasitic NPN tube is greatly reduced, and the purpose of improving the holding voltage Vh of the device is achieved.
As another embodiment of the present invention, there is provided a method for manufacturing a scr transient voltage suppression device having a high holding voltage as shown in fig. 3, the method including:
providing a second conductivity type substrate 22;
growing a second conductive type epitaxial layer 24 on the second conductive type substrate 22;
forming a second conductive type buried layer 32 at the boundary position of the second conductive type epitaxial layer 24 and the second conductive type substrate 22 by means of ion implantation;
forming a first conductivity type well region 11 and a second conductivity type well region 12 which are arranged at intervals on the surface of the second conductivity type epitaxial layer 24 away from the second conductivity type substrate 22 by means of ion implantation, wherein the first conductivity type well region 11 is located above the second conductivity type buried layer 32;
performing N + implantation and P + implantation in the first conductivity type well region 11 to form a first N + implantation region 111 and a first P + implantation region 112 which are arranged at an interval, and performing N + implantation and P + implantation in the second conductivity type well region 12 to form a second N + implantation region 121 and a second P + implantation region 122 which are arranged at an interval, wherein the first P + implantation region 112 is close to the second N + implantation region 121;
forming at least one second trench 33 penetrating through the first conductive well 11 at an edge of the first P + implantation region 112 close to the second N + implantation region 121, wherein a bottom end of the second trench 33 extends into the second conductive buried layer 32;
the first N + implantation region 111 and the first P + implantation region 112 are connected to form an anode contact 41, and the second N + implantation region 121 and the second P + implantation region 122 are connected to form a cathode contact 42.
It should be understood that, since the structure of the thyristor transient voltage suppression device with high sustaining voltage shown in fig. 3 is different from that of the thyristor transient voltage suppression device with high sustaining voltage shown in fig. 2 only in that the epitaxial layer adopted is the second conductivity type epitaxial layer, and the position of the buried layer is changed corresponding to this, that is, the second conductivity type buried layer is located below the first conductivity type well region, and the corresponding second trench is disposed through the first conductivity type well region, and the other structures are the same, the method for manufacturing the thyristor transient voltage suppression device with high sustaining voltage shown in fig. 3 can refer to the specific description of the method for manufacturing the thyristor transient voltage suppression device with high sustaining voltage shown in fig. 2, and will not be described herein again.
As another specific embodiment of the present invention, as shown in fig. 4, there is provided a thyristor transient voltage suppression device having a high sustain voltage, including:
a second conductive-type substrate 22, and a second conductive-type epitaxial layer 24 disposed on the second conductive-type substrate 22;
a first conductivity type well region 11 and a second conductivity type well region 12 are arranged in the second conductivity type epitaxial layer 24, and the first conductivity type well region 11 and the second conductivity type well region 12 are arranged at an interval;
a first N + injection region 111 and a first P + injection region 112 are disposed in the first conductivity type well region 11, and the first N + injection region 111 and the first P + injection region 112 are disposed at an interval;
a second N + implantation region 121 and a second P + implantation region 122 are disposed in the second conductive type well region 12, and the second N + implantation region 121 and the second P + implantation region 122 are disposed at an interval;
the first P + implant region 112 is close to the second N + implant region 121;
a first conductivity type buried layer 31 and a second conductivity type buried layer 32 which are arranged at intervals are formed at the boundary position of the second conductivity type epitaxial layer 24 and the second conductivity type substrate 22, the first conductivity type buried layer 31 is positioned below the second conductivity type well region 12, and the second conductivity type buried layer 32 is positioned below the first conductivity type well region 11;
at least one first trench 30 penetrating through the second conductive well region 12 is formed in the second N + implantation region 121 near the edge of the first P + implantation region 112, and the bottom end of the first trench 30 extends into the first conductive buried layer 31;
at least one second trench 33 penetrating through the first conductive type well region 11 is formed at a position of the first P + implantation region 112 close to the edge of the second N + implantation region 121, and a bottom end of the second trench 33 extends into the second conductive type buried layer 32;
the first N + implantation region 111 and the first P + implantation region 112 are connected to form an anode contact 41, and the second N + implantation region 121 and the second P + implantation region 122 are connected to form a cathode contact 42.
It should be understood that this embodiment is a combination of the structures of the first two embodiments, and compared to the embodiment shown in fig. 2, the first conductivity type epitaxial layer 21 is replaced by the second conductivity type epitaxial layer 24, and the second conductivity type buried layer 32 and the second trench 33 are added, and the other structures are kept unchanged.
Therefore, the thyristor transient voltage suppression device with high maintaining voltage provided by the embodiment of the invention, by forming the second conductivity type buried layer located under the first conductivity type well region and the first conductivity type buried layer located under the second conductivity type well region at the intersection of the second conductivity type epitaxial layer and the second conductivity type substrate, and a second trench penetrating the first conductive type well region and a first trench penetrating the second conductive type are formed, the change of the current path is realized, thereby more holes or electrons are compounded through the first conductive type buried layer and the second conductive type buried layer, the current gain of the parasitic NPN tube and the parasitic PNP tube is effectively reduced, the current path length of the controllable silicon structure is increased, and further, the effect of effectively improving the maintaining voltage of the transient suppression diode device is achieved on the premise of not changing the size of the transient suppression diode device.
As described above, in the embodiment of the present invention, the first conductivity type may be specifically N-type, and the second conductivity type may be specifically P-type, so that the second conductivity type epitaxial layer 24 includes a P-type epitaxial layer, the second conductivity type substrate 22 includes a P-type substrate, the first conductivity type well region 11 includes an N-type well region, the second conductivity type well region 12 includes a P-type well region, the first conductivity type buried layer 31 includes an N-type buried layer, and the second conductivity type buried layer 32 includes a P-type buried layer.
Therefore, the thyristor transient voltage suppression device with high sustain voltage provided by the embodiment of the invention blocks the shortest path of the thyristor so that the current of the thyristor must bypass the trench and pass through the N-type buried layer and the P-type buried layer, and the electrons and the holes of the thyristor are fully compounded, so that no matter the electrons emitted by the parasitic NPN or the holes emitted by the parasitic PNP, the electrons and the holes are greatly compounded at the buried layer, the total gain of the thyristor is greatly reduced, and the purpose of effectively improving the sustain voltage Vh is achieved.
As another embodiment of the present invention, a method for manufacturing a scr transient voltage suppressor having a high sustain voltage as shown in fig. 4 is provided, where the method includes:
providing a second conductivity type substrate 22;
growing a second conductive type epitaxial layer 24 on the second conductive type substrate 22;
forming a first conductive type buried layer 31 and a second conductive type buried layer 32 which are arranged at intervals at the boundary position of the second conductive type epitaxial layer 24 and the second conductive type substrate 22 in an ion implantation mode;
forming a first conductivity type well region 11 and a second conductivity type well region 12 which are arranged at intervals on the surface of the second conductivity type epitaxial layer 24 away from the second conductivity type substrate 22 by means of ion implantation, wherein the first conductivity type well region 11 is located above the second conductivity type buried layer 32, and the second conductivity type well region 12 is located above the first conductivity type buried layer 31;
performing N + implantation and P + implantation in the first conductivity type well region 11 to form first N + implantation regions 111 and first P + implantation regions 112 arranged at intervals, and performing N + implantation and P + implantation in the second conductivity type well region 12 to form second N + implantation regions 121 and second P + implantation regions 122 arranged at intervals, wherein the first P + implantation region 112 is close to the second N + implantation region 121;
forming at least one first trench 30 penetrating through the second conductivity type well region 12 at an edge position of the second N + implantation region 121 close to the first P + implantation region 112, and a bottom end of the first trench 30 extends into the first conductivity type buried layer 31, and forming at least one second trench 33 penetrating through the first conductivity type well region 11 at an edge position of the first P + implantation region 112 close to the second N + implantation region 121, and a bottom end of the second trench 33 extends into the second conductivity type buried layer 32;
the first N + implantation region 111 and the first P + implantation region 112 are connected to form an anode contact 41, and the second N + implantation region 121 and the second P + implantation region 122 are connected to form a cathode contact 42.
It should be understood that the scr transient voltage suppression device with high sustaining voltage shown in fig. 4 is obtained by combining the structures of fig. 2 and fig. 3, and compared with the structure shown in fig. 2, only the epitaxial layer adopted is the second conductivity type epitaxial layer, and the second conductivity type buried layer is added and the second trench is added, so that the method for manufacturing the scr transient voltage suppression device with high sustaining voltage shown in fig. 4 can refer to the specific description of the method for manufacturing the scr transient voltage suppression device with high sustaining voltage shown in fig. 2, and is not described herein again.
In conclusion, the thyristor transient voltage suppressor with high maintaining voltage provided by the invention can be effectively used for high-voltage latch-up resisting ESD and surge protection, and the surge protection capability is improved. The structure greatly reduces the positive feedback of the silicon controlled rectifier structure through the matching of the groove and the buried layer, and achieves the aim of high maintenance voltage. Meanwhile, because the device has high compatibility with the traditional process, the device can be used as a TVS discrete device independently and can be integrated with a related integrated circuit, thereby being oriented to on-chip protection.
It will be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention, and the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A thyristor transient voltage suppression device having a high holding voltage, comprising:
the epitaxial layer comprises a second conductive type substrate and a first conductive type epitaxial layer arranged on the second conductive type substrate;
a first conductive type well region and a second conductive type well region are arranged in the first conductive type epitaxial layer, and the first conductive type well region and the second conductive type well region are arranged at intervals;
a first N + injection region and a first P + injection region are arranged in the first conductive type well region, and the first N + injection region and the first P + injection region are arranged at intervals;
a second N + injection region and a second P + injection region are arranged in the second conductive type well region, and the second N + injection region and the second P + injection region are arranged at intervals;
the first P + injection region is close to the second N + injection region;
a first conductive type buried layer is formed at the junction position of the first conductive type epitaxial layer and the second conductive type substrate and is positioned below the second conductive type well region;
at least one first trench penetrating through the second conductive type well region is formed in the second N + injection region close to the edge of the first P + injection region, and the bottom end of the first trench extends into the first conductive type buried layer;
the first N + injection region and the first P + injection region are connected to form an anode contact, and the second N + injection region and the second P + injection region are connected to form a cathode contact.
2. The scr tvs of claim 1, wherein said first-conductivity-type buried layer has an ion implantation concentration of 1 x 10 15 cm -3 ~5*10 16 cm -3 In between.
3. The thyristor transient voltage suppression device with high holding voltage of claim 1, wherein the first conductivity type epitaxial layer has a thickness of between 5 μm and 20 μm.
4. The scr tvs of claim 1, wherein said first-conductivity-type well region has an ion implantation concentration of 1 x 10 13 cm -3 ~1*10 15 cm -3 The ion implantation concentration of the second conduction type well region is 1 x 10 13 cm -3 ~5*10 16 cm -3 In the meantime.
5. The scr tvs device of claim 1, wherein said first N + implant region, said second N + implant region, said first P + implant region, and said second P + implant region each have a carrier density of 1 x 10 15 cm -3 ~5*10 16 cm -3 In the meantime.
6. A thyristor transient voltage suppression device having a high holding voltage, comprising:
a second conductive type substrate, and a second conductive type epitaxial layer disposed on the second conductive type substrate;
a first conductive type well region and a second conductive type well region are arranged in the second conductive type epitaxial layer, and the first conductive type well region and the second conductive type well region are arranged at intervals;
a first N + injection region and a first P + injection region are arranged in the first conductive type well region, and the first N + injection region and the first P + injection region are arranged at intervals;
a second N + injection region and a second P + injection region are arranged in the second conductive type well region, and the second N + injection region and the second P + injection region are arranged at intervals;
the first P + injection region is close to the second N + injection region;
a second conductive type buried layer is formed at the junction position of the second conductive type epitaxial layer and the second conductive type substrate and is positioned below the first conductive type well region;
at least one second groove penetrating through the first conductive type well region is formed at the edge position of the first P + injection region, which is close to the second N + injection region, and the bottom end of the second groove extends into the second conductive type buried layer;
the first N + injection region and the first P + injection region are connected to form an anode contact, and the second N + injection region and the second P + injection region are connected to form a cathode contact.
7. A thyristor transient voltage suppression device having a high holding voltage, comprising:
a second conductive type substrate, and a second conductive type epitaxial layer disposed on the second conductive type substrate;
a first conductive type well region and a second conductive type well region are arranged in the second conductive type epitaxial layer, and the first conductive type well region and the second conductive type well region are arranged at intervals;
a first N + injection region and a first P + injection region are arranged in the first conductive type well region, and the first N + injection region and the first P + injection region are arranged at intervals;
a second N + injection region and a second P + injection region are arranged in the second conductive type well region, and the second N + injection region and the second P + injection region are arranged at intervals;
the first P + injection region is close to the second N + injection region;
forming first conductive type buried layers and second conductive type buried layers which are arranged at intervals at the junction position of the second conductive type epitaxial layer and the second conductive type substrate, wherein the first conductive type buried layers are positioned below the second conductive type well region, and the second conductive type buried layers are positioned below the first conductive type well region;
at least one first trench penetrating through the second conductive type well region is formed in the second N + injection region close to the edge of the first P + injection region, and the bottom end of the first trench extends into the first conductive type buried layer;
at least one second groove penetrating through the first conductive type well region is formed at the edge position of the first P + injection region, which is close to the second N + injection region, and the bottom end of the second groove extends into the second conductive type buried layer;
the first N + injection region and the first P + injection region are connected to form an anode contact, and the second N + injection region and the second P + injection region are connected to form a cathode contact.
8. A method for manufacturing a thyristor transient voltage suppression device having a high sustaining voltage, the thyristor transient voltage suppression device having a high sustaining voltage according to any one of claims 1 to 5, the method comprising:
providing a second conductive type substrate;
growing a first conductive type epitaxial layer on the second conductive type substrate;
forming a first conductive type buried layer at the junction position of the first conductive type epitaxial layer and the second conductive type substrate in an ion implantation mode;
forming a first conductive type well region and a second conductive type well region which are arranged at intervals on the surface of the first conductive type epitaxial layer, which is far away from the second conductive type substrate, in an ion implantation mode, wherein the second conductive type well region is positioned above the first conductive type buried layer;
performing N + injection and P + injection in the first conductivity type well region to form a first N + injection region and a first P + injection region which are arranged at intervals, and performing N + injection and P + injection in the second conductivity type well region to form a second N + injection region and a second P + injection region which are arranged at intervals, wherein the first P + injection region is close to the second N + injection region;
manufacturing at least one first trench penetrating through the second conductive type well region at the edge position of the second N + injection region close to the first P + injection region, wherein the bottom end of the first trench extends into the first conductive type buried layer;
and connecting the first N + injection region and the first P + injection region to form an anode contact, and connecting the second N + injection region and the second P + injection region to form a cathode contact through metal.
9. A method for manufacturing a thyristor transient voltage suppression device having a high sustaining voltage according to claim 6, the method comprising:
providing a second conductive type substrate;
growing a second conductive type epitaxial layer on the second conductive type substrate;
forming a second conductive type buried layer at the junction position of the second conductive type epitaxial layer and the second conductive type substrate in an ion implantation mode;
forming a first conductive type well region and a second conductive type well region which are arranged at intervals on the surface of the second conductive type epitaxial layer, which is far away from the second conductive type substrate, in an ion implantation mode, wherein the first conductive type well region is positioned above the second conductive type buried layer;
performing N + injection and P + injection in the first conductivity type well region to form a first N + injection region and a first P + injection region which are arranged at intervals, and performing N + injection and P + injection in the second conductivity type well region to form a second N + injection region and a second P + injection region which are arranged at intervals, wherein the first P + injection region is close to the second N + injection region;
manufacturing at least one second groove penetrating through the first conductive type well region at the edge position of the first P + injection region close to the second N + injection region, wherein the bottom end of the second groove extends into the second conductive type buried layer;
and connecting the first N + injection region and the first P + injection region to form an anode contact, and connecting the second N + injection region and the second P + injection region to form a cathode contact through metal.
10. A method for manufacturing a scr transient voltage suppressor device with high sustaining voltage according to claim 7, wherein the method comprises:
providing a second conductive type substrate;
growing a second conductive type epitaxial layer on the second conductive type substrate;
forming a first conductive type buried layer and a second conductive type buried layer which are arranged at intervals at the junction position of the second conductive type epitaxial layer and the second conductive type substrate in an ion implantation mode;
forming a first conductive type well region and a second conductive type well region which are arranged at intervals on the surface of the second conductive type epitaxial layer, which is far away from the second conductive type substrate, in an ion implantation mode, wherein the first conductive type well region is positioned above the second conductive type buried layer, and the second conductive type well region is positioned above the first conductive type buried layer;
performing N + injection and P + injection in the first conductivity type well region to form a first N + injection region and a first P + injection region which are arranged at intervals, and performing N + injection and P + injection in the second conductivity type well region to form a second N + injection region and a second P + injection region which are arranged at intervals, wherein the first P + injection region is close to the second N + injection region;
forming at least one first trench penetrating through the second conductivity type well region at an edge position of the second N + implantation region close to the first P + implantation region, and a bottom end of the first trench extends into the first conductivity type buried layer, and forming at least one second trench penetrating through the first conductivity type well region at an edge position of the first P + implantation region close to the second N + implantation region, and a bottom end of the second trench extends into the second conductivity type buried layer;
and connecting the first N + injection region and the first P + injection region to form an anode contact, and connecting the second N + injection region and the second P + injection region to form a cathode contact.
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