WO2021068462A1

WO2021068462A1 - Tvs device using vertical triode to trigger surface silicon controlled rectifier structure

Info

Publication number: WO2021068462A1
Application number: PCT/CN2020/081888
Authority: WO
Inventors: 赵德益; 苏海伟; 吕海凤; 蒋骞苑; 张啸; 王允; 赵志方
Original assignee: 上海维安半导体有限公司
Priority date: 2019-07-01
Filing date: 2020-03-27
Publication date: 2021-04-15
Also published as: CN110600467A

Abstract

Disclosed in the present invention is a TVS device using a vertical triode to trigger a surface silicon controlled rectifier structure, comprising a semiconductor body, the semiconductor body comprising a surface junction silicon controlled rectifier structure and a vertical NPN structure, the pass-through isolation of an anode of the silicon controlled rectifier structure and the semiconductor body being connected by metal; when the vertical NPN structure breaks down, the surface junction silicon controlled rectifier structure is triggered; by means of the addition of the trigger structure, the present invention provides a voltage or current in order to reduce the trigger voltage and increase the maintenance voltage, such that the TVS performance of the silicon controlled rectifier structure is closer to ideal.

Description

A TVS device using a vertical triode to trigger a surface thyristor structure

Technical field

The invention belongs to the field of semiconductor technology, and particularly relates to a TVS device using a vertical triode to trigger a surface thyristor structure.

Background technique

TVS, as the main component of PCB board-level electrostatic and surge protection, provides a path for charge discharge. The transient interference of voltage and current is always present, which can cause fatal damage to the equipment at any time, and the demand and reliance on transient voltage suppressors (TVS) will increase accordingly. With the shrinking of the process size, the protection level of the on-chip integrated circuit is getting weaker and weaker, and higher requirements are put forward for the characteristics of the TVS, and the clamping voltage of the TVS is required to continuously decrease.

Due to the amplification effect of the two transistors in the current path, the thyristor technology will enter a large current and low voltage latched state after it is turned on. When used as a TVS application, it has the characteristics of low clamping voltage, so it is favored by engineers and widely studied . Because of its latched state, the power port that can provide continuous high current is burned out, and it cannot be applied to the power port. However, it is an ideal choice for signal port protection. Transient voltages such as static electricity and surge are applied to the thyristor structure. When the voltage across the TVS is higher than its turn-on voltage, the reverse diode in the PNPN structure breaks down first, and the current acting on the well resistor makes the voltage across the resistor greater than the PN forward voltage, the PN junction is forward biased, and the two transistors All enter the amplification area, and positive feedback is formed, and it enters the latched state of large current and low voltage; when the transient voltage disappears, it exits the latched state because it cannot provide a continuous current.

1 and 2, in the prior art, the cross-sectional structure diagram of the TVS structure formed by the surface junction thyristor and its equivalent circuit diagram, from the N-type well Nwell, the P-type heavily doped P+, the N-type well Nwell, and the P-type well The transistor one Q1 formed by the well Pwell, the N-well Nwell, the P-well Pwell and the N+ in the P-well Pwell constitute the transistor two Q2, and the P-type heavily doped P+ connected from Pin2 passes through the P-well Pwell to the transistor two Q2 base There is a resistor R1 in the area, and the N+ connected from Pin1 through Nwell to the base area of Q1 has resistors R2. Q1, Q2, R1, and R2 form a SCR (Silicon Controlled Rectifier) structure, which is opposite to the PN junction TVS and NPN structure The advantage of TVS is that its snapback characteristics make the maintenance voltage much lower than the breakdown voltage of PN junction and the avalanche breakdown or punch-through breakdown voltage of NPN structure TVS. When comparing structures with the same dynamic resistance, the clamping voltage differs by at least 5V. The TVS of the thyristor structure can provide a more secure guarantee for the later-stage protected IC. On the other hand, as the breakdown voltage of the PN junction TVS increases, its dynamic resistance attenuates accordingly. The TVS dynamic resistance of the thyristor structure will not be greatly attenuated with the change of the opening voltage, which is especially suitable for high-voltage signal port applications. , Generally refers to the 12V～24V signal port, because the SCR structure can adjust the opening voltage higher than the power supply voltage when the voltage is unchanged, so the clamping voltage of the high voltage signal port can be lower by about 12V to 24V.

The turn-on voltage of the thyristor structure TVS is relatively high. For example, the turn-on voltage is higher than the withstand voltage of the protected IC. Although the thyristor structure TVS can protect the IC circuit at high voltage, there is a low transient pulse. In the case of IC burnout, the TVS turn-on voltage of the thyristor structure exceeds the safe working area. This weakness limits the application of SCR. Therefore, in view of the shortcomings in the actual production and implementation of the above-mentioned solutions, they are revised and improved. At the same time, they are based on the spirit and philosophy of seeking good, and are assisted by professional knowledge and experience, as well as ingenuity and experimentation. Later, Fang created the present invention, and especially provides a TVS device that uses a vertical triode to trigger a surface thyristor structure.

Summary of the invention

The purpose of the present invention is to provide a TVS device that uses a vertical triode to trigger a surface thyristor structure. A trigger structure is added to provide voltage or current, so as to reduce the trigger voltage while increasing the sustaining voltage, so that the TVS performance of the thyristor structure is improved. Tend to be ideal to solve the problems in the prior art.

The technical solution of the present invention is realized as follows: a TVS device with a surface thyristor structure triggered by a vertical triode includes a semiconductor body including a surface junction thyristor structure and a vertical NPN structure, the thyristor structure The interconnection isolation between the anode and the semiconductor body is connected by metal, and when the vertical NPN structure breaks down, the surface junction thyristor structure is triggered.

As a preferred embodiment, the semiconductor body further includes a horizontal NPN structure, and the cathode of the thyristor structure is isolated from the interconnection through a metal connection, and is used to trigger the controllable surface junction alone or together with the vertical NPN structure. Silicon structure.

As a preferred embodiment, the semiconductor body includes a substrate and an epitaxial layer arranged in sequence; and an N-type interconnection isolation arranged side by side with the epitaxial layer on the side of the N-type buried layer; and arranged on the side of the epitaxial layer and The N-type and P-type wells located in the middle of the N-type through isolation; and the N-type and P-type heavily doped in the N-type well, and the N-type and P-type heavily doped in the P-type well. Doped.

As a preferred embodiment, the surface junction SCR structure includes a P-type well, an N-type well, a P-type heavily doped and an N-type heavily doped.

As a preferred embodiment, the vertical NPN structure includes an N-type buried layer, an epitaxial layer, and a P-type well.

As a preferred embodiment, the breakdown mechanism of the longitudinal NPN structure includes avalanche breakdown and Zener breakdown.

As a preferred embodiment, the breakdown voltage of the vertical NPN structure is less than or equal to 10V.

As a preferred embodiment, the substrate is an N-type substrate, and the epitaxial layer is an N-type epitaxial layer.

As a preferred embodiment, the substrate is an N-type substrate, and the epitaxial layer is a P-type epitaxial layer.

As a preferred embodiment, the substrate is an N-type substrate, the epitaxial layer is a P-type epitaxial layer, and an N-type buried layer is provided between the N-type substrate and the P-type epitaxial layer.

The advantages of a TVS device using a vertical triode to trigger a surface thyristor structure of the present invention are: small current and large current have different current paths, and the longitudinal NPN structure is used as the main path for opening and small current. When the current increases, the longitudinal NPN structure The current from the middle P-type well (the gate of the SCR structure) to the N-type heavily doped (the cathode of the SCR structure) is used as the SCR gate trigger current to turn on the SCR structure. When the current is large, the SCR is the main current path. The different current paths of small current and large current make the structure have excellent turn-on voltage, negative resistance characteristics and excellent dynamic resistance characteristics.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor.

Figure 1 is a schematic diagram of the cross-sectional structure of a TVS structure formed by a commonly used surface junction thyristor;

Figure 2 The equivalent circuit diagram of a TVS structure formed by a commonly used surface junction thyristor;

FIG. 3 is a schematic diagram of a cross-sectional structure of a TVS device (N-type substrate with N-type buried layer and N-type epitaxy) using a vertical triode to trigger a surface thyristor structure;

FIG. 4 is a schematic diagram of a cross-sectional structure of a TVS device (N-type substrate with N-type buried layer and P-type epitaxy) using a vertical triode to trigger a surface thyristor structure;

FIG. 5 is a schematic diagram of a cross-sectional structure of a TVS device (N-type substrate N-type epitaxy) using a vertical triode to trigger a surface-controlled silicon structure;

FIG. 6 is a schematic cross-sectional structure diagram of a TVS device (N-type substrate with P-type epitaxy) using a vertical triode to trigger a surface thyristor structure;

Figure 7 is an equivalent circuit diagram of a TVS device using a longitudinal triode to trigger a surface thyristor structure;

Fig. 8 The equivalent circuit diagram of a TVS device using a longitudinal triode to trigger a surface thyristor structure (combined triode emitter);

Figure 9 is a cross-sectional structure diagram of a TVS structure (N-type buried layer and N-type epitaxy on an N-type substrate) formed by a surface junction thyristor that is triggered by a horizontal triode and a vertical triode;

FIG. 10 is a schematic diagram of the cross-sectional structure of a TVS structure (the N-type substrate has an N-type buried layer and a P-type epitaxy) formed by a surface junction thyristor that is triggered by a horizontal triode and a vertical triode;

Figure 11 is a cross-sectional structure diagram of a TVS structure (N-type substrate N-type epitaxy) formed by adding a horizontal triode and a vertical triode jointly triggered by a surface junction thyristor;

FIG. 12 is a schematic diagram of the cross-sectional structure of a TVS structure (P-type epitaxy on an N-type substrate) formed by a surface junction thyristor that is jointly triggered by a horizontal triode and a vertical triode;

Figure 13 adds the equivalent circuit diagram of the TVS structure formed by the surface junction thyristor triggered by the horizontal triode and the vertical triode;

Figure 14 adds the equivalent circuit diagram of the TVS structure formed by the surface junction thyristor triggered by the horizontal triode and the vertical triode (combined triode emitter);

FIG. 15 is a schematic diagram of IV characteristics of a TVS device using a vertical triode to trigger a surface thyristor structure;

Fig. 16 is a schematic diagram of the cross-sectional structure of a TVS device (N-type substrate with N-type buried layer and N-type epitaxial layer) using a vertical triode to trigger a surface thyristor structure led by a back electrode;

FIG. 17 is a schematic diagram of the cross-sectional structure of a TVS device (an N-type substrate with an N-type buried layer and a P-type epitaxial layer) using a vertical triode to trigger a surface thyristor structure led by a back electrode;

Fig. 18 is a schematic diagram of a cross-sectional structure of a TVS device (N-type substrate and N-type epitaxial layer) using a vertical triode to trigger a surface thyristor structure led by a back electrode;

Fig. 19 is a schematic diagram of a cross-sectional structure of a TVS device (N-type substrate P-type epitaxial layer) with a backside electrode that uses a vertical triode to trigger a surface thyristor structure;

Figure 20 is a cross-sectional structure diagram of a TVS structure (N-type substrate with N-type buried layer and N-type epitaxial layer) formed by the surface junction thyristor formed by increasing the horizontal triode and the vertical triode triggered by the back electrode;

Figure 21 is a cross-sectional structure diagram of a TVS structure (N-type substrate with N-type buried layer and P-type epitaxial layer) formed by a surface junction thyristor formed by adding a horizontal triode and a vertical triode that are triggered by a back electrode;

Figure 22 is a schematic diagram of the cross-sectional structure of a TVS structure (N-type substrate with N-type epitaxial layer) formed by a surface junction thyristor that is triggered by a horizontal triode and a vertical triode with a back electrode;

Figure 23 is a cross-sectional structure diagram of a TVS structure (N-type substrate with P-type epitaxial layer) formed by the surface junction thyristor formed by increasing the horizontal triode and the vertical triode triggered by the back electrode;

The label description in the figure,

Nsub——N-type substrate; Nbury——N-type buried layer; Nepi——N-type epitaxial layer;

Pepi——P-type epitaxial layer; Niso——N-type butt isolation;

Pwell——P-type well; Nwell——N-type well;

P+——P-type heavily doped; N+——N-type heavily doped; SCR——SCR.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

Figures 3 to 23 show the cross-sectional structure and equivalent circuit diagram of a TSV device using a longitudinal triode to trigger a surface thyristor structure in several different embodiments, and Figures 3 to 9 specifically show the use of a longitudinal triode to trigger A cross-sectional view and equivalent circuit diagram of a TVS device with a surface thyristor structure. Figures 10-15 are cross-sectional views and equivalent circuit diagrams of a TVS structure formed by adding a surface junction thyristor triggered by a horizontal triode and a vertical triode. The present invention uses the vertical A TVS device with a triode-triggered surface thyristor structure includes a semiconductor body, the semiconductor body includes a surface junction thyristor structure and a vertical NPN structure, the anode of the thyristor structure is isolated from the semiconductor body through a metal connection When the vertical NPN structure breaks down, the surface junction thyristor structure is triggered.

The semiconductor body may further include a horizontal NPN structure, and the cathode of the thyristor structure is connected to the interconnection isolation through a metal for triggering the surface junction thyristor structure alone or together with the vertical NPN structure.

Example 1

A TVS device using a vertical triode to trigger a surface thyristor structure, as shown in Figure 3. The TVS device includes an N-type substrate Nsub with an N-type buried layer Nbury, an N-type epitaxial layer Nepi, and an N-type epitaxial layer Nepi. The upper thyristor structure sequentially includes: N-type interconnection isolation Niso, N-type well Nwell, P-type well Pwell, N-type heavily doped N+, P-type heavily doped P+ semiconductor body, among which,

The semiconductor body includes silicon wafers with an N-type substrate, an N-type buried layer, and an N-type epitaxial layer arranged in sequence, and two N-type interconnect isolations arranged side by side on the N-type epitaxial layer to the N-type buried layer are located in the two The surface junction thyristor structure composed of N-type wells and P-type wells in the middle of the N-type to-through isolation, where,

The N-type to-through isolation Niso has N-type heavily doped N+;

In the P-type well Pwell, there are sequential N-type heavily doped N+, P-type heavily doped P+ and N-type heavily doped N+;

N-type well Nwell contains N-type heavily doped N+ and P-type heavily doped P+;

In this embodiment, two N-type wells Nwell with the same structure are provided on both sides of the P-type well Pwell; the two N-type wells Nwell are respectively provided with N-type interconnection isolation Niso including N-type heavily doped N+ regions on the outside;

In this embodiment, the metal wiring of the surface junction SCR structure is of an insert finger design, and the anode of the SCR structure is isolated and connected to the N-type butt through a metal connection.

The size and spacing of P-type heavily doped P+, N-type well, P-type well and N-type heavily doped N+ are appropriately designed to form a surface junction thyristor structure.

The structure is shown in Figure 3, and the equivalent circuit is shown in Figure 7. The PNP transistor Q1 is formed by the P-type heavily doped in the N-type well, the N-type well Nwell, and the P-type well Pwell. The N-type heavily doped in the well Pwell and the P-type well Pwell constitute the second NPN transistor Q2, and the vertical triode Q3 formed by the N-type epitaxial Nepi, Pwell, and N+ in the Pwell; the P-type heavily doped connected from the terminal Pin2 The impurity P+ passes through the P-well Pwell to the resistance of the base region of the transistor two Q2: R1; the N-type heavily doped N+ connected from the terminal Pin1 through the N-type well Nwell to the resistance of the transistor one Q1 base region two R2; from the terminal Pin1 The connected N-type pair-through isolation Niso is heavily doped N+, and the resistance from the N-type buried layer Nbury to the N-type epitaxial layer Nepi through the N-type pair-through isolation Niso, the N-type epitaxial layer Nepi constitutes the resistance three R3; by the transistor one, two Q1, Q2 and resistors one, two R1 and R2 form a thyristor structure SCR. The vertical NPN structure formed by the vertical triode Q3 and resistor three R3 is used as the current path for opening and small current, and its breakdown voltage is controlled to be less than the thyristor SCR When the transient high voltage pulse reaches the Pin1 port, the vertical triode Q3 is turned on before the thyristor to form a current path. This current is used as the base current of the triode Q2 in the thyristor structure, or called In order to trigger the current by the SCR gate, the SCR structure is turned on to form a low-resistance current path; when the current is large, the SCR acts as the main current path to form a low-resistance current path.

Because of the physical structure, the base and emitter of the vertical triode Q3 and the second transistor Q2 are very similar to the PN structure, and the equivalent circuit diagram is combined as shown in Figure 7. The base area and emitter of the vertical triode Q3 and the second transistor Q2 can obtain the equivalent circuit. As shown in Figure 8.

Figure 15 shows the IV characteristic diagram of the TVS device with the surface thyristor structure triggered by the vertical triode. The characteristic curve of the surface thyristor SCR is shown in the SCR deep snapback curve in Figure 15. In the first quadrant, with the two ends of the device in this embodiment The voltage rises, the device breaks down through the PN junction, and flows from the base of the transistor to the base terminal Pin2. The current acts on the base well resistor, causing the base-emitter to be positively biased, and the surface SCR enters the negative resistance region to reach the latch. Locked state; the vertical transistor Q3 connected to the Niso and the buried layer is isolated through the N-type interconnection. When the voltage at both ends of the device rises, as shown in the BJT shallow snapback curve in Figure 15, the vertical transistor Q3 has a lower voltage than the thyristor SCR structure Then it can enter the breakdown state. When the voltage of the well resistance introduced by it is greater than that required for the base-emitter positive bias, the SCR SCR structure enters the negative resistance region and reaches the latched state.

The third quadrant is the application of a negative voltage across the device of this embodiment. Since the PN junction formed by the N-well Nwell and the P-well Pwell has a lower concentration and a larger spacing than the PN junction formed by the Nbury/Nepi and Pwell, the vertical triode’s impact The breakdown voltage is lower than that of the thyristor SCR structure, and the overall performance is the breakdown characteristic of a vertical triode.

For example, when the distance between the heavily doped junction and the well boundary is far, the breakdown of the N-type well Nwell and the P-type well Pwell is an avalanche breakdown, and its concentration gradient, well resistance, and concentration difference determine the breakdown voltage of the withstand voltage junction ; For example, when the distance between the heavily doped junction and the boundary of the well is close, the punch-through and breakdown mechanism plays a major role. The junction distance and junction morphology determine the turn-on voltage of the SCR structure.

Design the doping concentration and thickness of the N-type buried layer, the N-type epitaxial layer, and the P-type well to form a vertical NPN structure, and appropriately design the N-type on-connection isolation and the doping concentration of the N-type buried layer to obtain the lowest possible on-resistance. The anode of the thyristor structure is isolated and connected to the interconnect through a metal connection. There are two possibilities for the breakdown mechanism of the vertical NPN structure: avalanche breakdown and punch-through breakdown, which are determined by the thickness and concentration of the epitaxial layer and the P-type well. Through the structural design, the breakdown voltage of the vertical triode structure is lower than the turn-on voltage of the SCR structure. , And control its breakdown voltage in the safe operating area of the IC. In the event of an ESD event or a surge event, the on-current is first turned on by the vertical NPN junction. When the vertical transistor is broken down, the P-type well (the gate of the thyristor structure) Polar)-N-type heavily doped (SCR structure cathode) junction is positively biased, triggering the surface junction SCR structure.

That is, small current and large current have different current paths. The vertical NPN structure is the main path for opening and small current. When the current increases, the P-type well (the gate of the SCR structure) in the vertical NPN structure to the N-type heavily doped (SCR) The current of the cathode of the structure is used as the trigger current of the SCR gate to turn on the SCR structure, and the SCR is used as the main current path when the current is large. The different current paths of small current and large current make the structure have excellent turn-on voltage, negative resistance characteristics and excellent dynamic resistance characteristics.

Therefore, the TVS device with the vertical triode trigger surface thyristor structure can obtain a low trigger voltage while maintaining a lower voltage and dynamic resistance than the SCR without a trigger structure. Structural design includes but is not limited to the following:

A) The concentration and thickness of the epitaxial layer are designed so that the breakdown mechanism includes avalanche breakdown and punch-through breakdown, and the breakdown voltage is adjusted to be less than 10V or lower;

B) Well concentration and morphology control, such as multiple well implants with different energies and doses, and appropriate advance time and temperature;

C) Use a precise injection barrier layer to control the accuracy of the injection, such as polysilicon gate as a barrier layer, field oxide layer as a barrier layer, and photoresist as a barrier layer;

Since the metal wiring of the surface-junction thyristor structure is an insert finger design, the metal wire assumes the role of positive charge dispersion and convergence, and the priority damage point is the location where the current is most concentrated. It is necessary to calculate the charge that can pass through the width and thickness of the metal line, and to compromise the design of the metal line length to realize the current sharing design.

Example 2

A TVS device that uses a vertical triode to trigger a surface thyristor structure, as shown in Figure 4, is similar to Embodiment 1, except that the epitaxial structure is different. The TVS device includes an N-type substrate Nsub, an N-type buried layer Nbury, and P Type epitaxial layer Pepi, N-type opposite isolation Niso, N-type well Nwell, P-type well Pwell, N-type heavily doped N+ and P-type heavily doped P+ semiconductor body, wherein, on the upper surface of the P-type epitaxial layer Pepi Set in order:

The N-type to-through isolation Niso has N-type heavily doped N+;

N-type well Nwell contains N-type heavily doped N+ and P-type heavily doped P+;

The metal wiring of the surface junction thyristor structure in this embodiment is of an interposer design.

Example 3

A TVS device using a vertical triode to trigger a surface thyristor structure, as shown in Figure 5, is similar to Embodiment 1, except that the N-type buried layer structure is different. The TVS device includes an N-type substrate Nsub and an N-type epitaxial layer. Nepi, N-type pair isolation Niso, N-type well Nwell, P-type well Pwell, N-type heavily doped N+ and P-type heavily doped P+ semiconductor body, the upper surface of the N-type epitaxial layer Nepi sequentially contains:

N-type heavily doped N+, P-type heavily doped P+, and N-type heavily doped N+ regions P-type well Pwell, forming a vertical NPN junction and a horizontal NPN;

The two sides of the P-type well Pwell are provided with two N-type wells Nwell with the same structure including N-type heavily doped N+ and P-type heavily doped P+ regions;

The two N-type wells Nwell are respectively provided with an N-type interconnection isolation Niso including an N-type heavily doped N+ region on the outside;

The metal wiring of the surface junction thyristor structure is an interposer design.

Example 4

A TVS device using a vertical triode to trigger a surface thyristor structure, as shown in Figure 6, is similar to Embodiment 2, except that the N-type buried layer structure is different. The TVS device includes an N-type substrate Nsub and a P-type epitaxial layer. Pepi, N-type pair isolation Niso, N-type well Nwell, P-type well Pwell, N-type heavily doped N+ and P-type heavily doped P+ semiconductor bodies are arranged in order on the upper surface of the P-type epitaxial layer Pepi:

Sequentially include N-type heavily doped N+, P-type heavily doped P+, and N-type heavily doped N+ regions P-well Pwell, forming a vertical NPN junction and a horizontal NPN;

Example 5

A TVS device using a vertical triode to trigger a surface thyristor structure, as shown in FIG. 9, is similar to Embodiment 1, except that the heavily doped structure in the P-well Pwell is different. The TVS device includes an N-type substrate Nsub, A semiconductor body composed of N-type buried layer Nbury, N-type epitaxial layer Nepi, N-type interconnection isolation Niso, N-type well Nwell, P-type well Pwell, N-type heavily doped N+ and P-type heavily doped P+.

The semiconductor body includes silicon wafers with an N-type substrate Nsub, an N-type buried layer Nbury, and an N-type epitaxial layer Nepi arranged in sequence, and two N-type interconnect isolations arranged side by side on the N-type epitaxial layer Nepi to the N-type buried layer Niso, a surface junction thyristor structure and a lateral NPN structure composed of an N-type well Nwell and a P-type well Pwell located between the two N-type opposing isolation Nisos,

The P-type well Pwell sequentially includes five heavily doped N-type heavily doped N+, N-type heavily doped N+, P-type heavily doped P+, N-type heavily doped N+ and N-type heavily doped N+ Area;

The two sides of the P-type well Pwell are provided with N-type wells Nwell with the same structure including N-type heavily doped N+ and P-type heavily doped P+ regions;

The metal wiring of the surface junction thyristor structure is an insert finger design; the size and spacing of the P-type heavily doped P+, the N-type well Nwell, the P-type well Pwell, and the N-type heavily doped N+ form the surface-junction thyristor structure.

The structure is shown in Figure 9, and the equivalent circuit is shown in Figure 13. The PNP transistor Q1 is composed of P-type heavily doped P+ in Nwell, N-type well Nwell, and P-type well Pwell, N-type well Nwell, P-type The N+ in the well Pwell and the N-well Pwell constitute the second NPN transistor Q2, the vertical triode Q3 formed by the N-type epitaxial Nepi, the P-well Pwell, and the N+ in the P-well Pwell, and the P-well Pwell is connected to Pin1 N-type heavily doped N+, P-type well Pwell, and P-type well Pwell are connected to the N+ of Pin2 to form a lateral transistor Q4; the P+ connected from Pin2 through Pwell to the base of transistor Q2 forms a resistor R1, and N+ connected from Pin1 The resistance two R2 formed by the N-type well Nwell to the base of the transistor-Q1, the N-type through-to-isolation from Pin1 connects the N+ in the Niso through the N-type through-to-isolation Niso, the N-type buried layer Nbury to the N-type epitaxial layer Nepi The resistance constitutes the resistance three R3, and the resistance connected from Pin1 to the N+ in the P-well Pwell is the resistance four R4;

Transistor one, two Q1, Q2 and resistor one, two R1, R2 form a thyristor SCR structure; a vertical triode Q3, resistor three R3 form a vertical NPN structure as a vertical triode current path, horizontal triode Q4, resistor four R4 A horizontal NPN structure is formed as the current path of the horizontal triode, and the breakdown voltage of the vertical triode Q3 and the horizontal triode Q4 is controlled to be less than the trigger voltage of the thyristor SCR. When the transient high voltage pulse reaches the Pin1 port, the vertical triode Q3 and the horizontal triode Q4 precede The thyristor SCR is turned on to form a small current path. This current is used as the base current of the transistor Q2 in the thyristor structure, and the thyristor SCR structure is turned on to form a low resistance current path.

Due to the physical structure, the base and emitter of the vertical transistor Q3 and the horizontal transistor Q4 are formed into a PN structure that is extremely the same. The combined equivalent circuit diagram is shown in Figure 13 for the base and emitter of the vertical transistors Q3, Q4 and Q2 to obtain an equivalent circuit. As shown in Figure 14.

The well contact (gate) in the P-type well where the SCR structure cathode is located and the N-type heavily doped size and spacing form a horizontal NPN structure with a suitable opening voltage. The anode of the SCR structure is isolated from the interconnection through a metal connection. The N-type heavily doped connection in the P-type well where the cathode is located. The horizontal triode structure and the vertical triode structure trigger the surface junction thyristor structure together.

Example 6

A TVS device using a vertical triode to trigger a surface thyristor structure, as shown in Figure 10, is similar to Embodiment 5, except that the epitaxial structure is different. The TVS device includes an N-type substrate Nsub, an N-type buried layer Nbury, and P The semiconductor body composed of the N-type epitaxial layer Pepi, the N-type counter-connection isolation Niso, the N-type well Nwell, the P-type well Pwell, the N-type heavily doped N+ and the P-type heavily doped P+, in order on the upper surface of the N-type epitaxial layer Nepi Settings:

P-type well Pwell sequentially includes five heavily doped regions of N-type heavily doped N+, N-type heavily doped N+, P-type heavily doped P+, N-type heavily doped N+, and N-type heavily doped N+. Type well Pwell;

Example 7

A TVS device using a vertical triode to trigger a surface thyristor structure, as shown in FIG. 11, is similar to Embodiment 5, except that the buried layer structure is different. The TVS device includes an N-type substrate Nsub, an N-type epitaxial layer Nepi, The semiconductor body composed of N-type pair isolation Niso, N-type well Nwell, P-type well Pwell, N-type heavily doped N+ and P-type heavily doped P+ are arranged in order on the upper surface of the N-type epitaxial layer Nepi:

Example 8

A TVS device using a vertical triode to trigger a surface thyristor structure, as shown in FIG. 12, is similar to Embodiment 5, except that the buried layer and the epitaxial layer structure are different. The TVS device includes an N-type substrate Nsub and a P-type epitaxial layer. The layers Pepi, N-type pair isolation Niso, N-type well Nwell, P-type well Pwell, N-type heavily doped N+ and P-type heavily doped P+ semiconductor bodies are arranged in order on the upper surface of the N-type epitaxial layer Nepi:

Example 9

As shown in Figure 16, the others are the same as Embodiment 1. Based on the structure of Embodiment 1, the back surface of the N-type substrate Nsub is metalized, and the back electrode is led out. The frame and exposed pins connected to the front Pin1 are connected by conductive glue during packaging. .

The back surface is metallized, and the back surface electrode is led out. When packaging, the frame connected to the front Pin1 and the exposed pins are connected through conductive glue.

Due to the high substrate concentration, low resistivity and good electrical conductivity, the structure protection effect of adding the back electrode is better. At the same time, the back electrode is led out to the entire back plane, and the distance to the surface junction is similar. Compared with the Niso extraction method through the N-type butt isolation , The current path is more uniform.

Example 10

As shown in FIG. 17, the others are the same as the second embodiment, except that the back surface of the N-type substrate Nsub is metalized, and the back electrode is led out. When packaging, the frame connected to the front Pin1 and the exposed pins are connected by conductive glue.

Example 11

As shown in FIG. 18, the others are the same as Embodiment 3, except that the back surface of the N-type substrate Nsub is metalized, and the back electrode is led out. During packaging, the frame connected to the front Pin1 and the exposed pins are connected by conductive glue.

Example 12

As shown in Fig. 19, the others are the same as in Embodiment 4, except that the back surface of the N-type substrate Nsub is metalized, and the back electrode is led out. During packaging, the frame connected to the front Pin1 and the exposed pins are connected by conductive glue.

Example 13

As shown in FIG. 20, the others are the same as Embodiment 5, except that the back surface of the N-type substrate Nsub is metalized, and the back electrode is led out, and the frame connected to the front Pin1 and the exposed pins are connected by conductive glue during packaging.

Example 14

As shown in FIG. 21, the others are the same as Embodiment 6, except that the back surface of the N-type substrate Nsub is metalized, and the back electrode is led out. When packaging, the frame connected to the front Pin1 and the exposed pins are connected by conductive glue.

Example 15

As shown in FIG. 22, the others are the same as in Embodiment 7, except that the back surface of the N-type substrate Nsub is metalized, and the back electrode is led out. During packaging, the frame connected to the front Pin1 and the exposed pins are connected by conductive glue.

Example 16

As shown in FIG. 23, the others are the same as in Embodiment 8, except that the back surface of the N-type substrate Nsub is metalized, and the back electrode is led out. During packaging, the frame connected to the front Pin1 and the exposed pins are connected by conductive glue.

In addition, the substrate type of the TVS device of the present invention is not limited to the N-type buried layer and the N-type epitaxial layer, and N-type substrate and N-type epitaxial layer, N-type buried layer and P-type epitaxial layer, N-type buried layer and P-type epitaxial layer of suitable concentration and thickness are used. Type substrate and P-type epitaxial layer can also obtain similar electrical characteristic parameters.

The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the present invention. Within the scope of protection.

Claims

A TVS device using a vertical triode to trigger a surface thyristor structure includes a semiconductor body, characterized in that the semiconductor body includes a surface junction thyristor structure and a vertical NPN structure, and the anode of the thyristor structure is connected to the semiconductor body The interconnection isolation is connected by metal, and the breakdown voltage of the vertical NPN structure is lower than the turn-on voltage of the thyristor structure. When the vertical NPN structure breaks down, the surface junction thyristor structure is triggered.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 1, wherein the semiconductor body further comprises a horizontal NPN structure, and the cathode of the thyristor structure is connected to the interconnection isolation by metal, Used to trigger the surface junction thyristor structure alone or together with the longitudinal NPN structure.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 1 or 2, wherein the semiconductor body comprises a substrate and an epitaxial layer arranged in sequence; and the epitaxial layer is arranged side by side in the N-type buried N-type interconnection isolation on the side of the layer; and N-type wells and P-type wells arranged on the side of the epitaxial layer and in the middle of the N-type interconnection isolation; and N-type heavily doped and P-type heavy Doping, N-type heavy doping and P-type heavy doping arranged in the P-type well.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 1, wherein the surface junction thyristor structure includes a P-type well, an N-type well, a P-type heavily doped and an N-type heavy Doped.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 1, wherein the vertical NPN structure includes an N-type buried layer, an epitaxial layer, a P-type well, and an N-type heavily doped.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 1, wherein the breakdown mechanism of the vertical NPN structure includes avalanche breakdown and Zener breakdown.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 1, wherein the breakdown voltage of the vertical NPN structure is less than or equal to 10V.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 3, wherein the substrate is an N-type substrate, and the epitaxial layer is an N-type epitaxial layer.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 3, wherein the substrate is an N-type substrate, and the epitaxial layer is a P-type epitaxial layer.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 3, wherein the substrate is an N-type substrate, the epitaxial layer is a P-type epitaxial layer, and the N-type substrate An N-type buried layer is arranged between the P-type epitaxial layer.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 3, characterized in that:

The semiconductor body includes silicon wafers of an N-type substrate, an N-type buried layer, and an N-type epitaxial layer arranged in sequence, and two N-type interconnect isolations arranged side by side on the N-type epitaxial layer to the N-type buried layer are located in two The surface junction thyristor structure composed of N-type wells and P-type wells in the middle of the N-type to-through isolation, where,

The N-type pair-through isolation has N-type heavily doped N+;

In the P-type well, there are N-type heavily doped N+, P-type heavily doped P+, and N-type heavily doped N+ in sequence;

There are N-type heavily doped and P-type heavily doped in the N-type well;

Two N-type wells with the same structure are arranged on both sides of the P-type well; the outer sides of the two N-type wells are respectively provided with N-type interconnection isolation containing N-type heavily doped, and the metal wiring of the surface junction thyristor structure is an insert finger Design, the anode of the thyristor structure is isolated and connected with the N-type through metal connection, and the PNP transistor one (Q1) is formed by the P-type heavily doped, the N-type well, and the P-type well in the N-type well. , P-type well, N-type heavily doped in P-type well constitutes NPN transistor two (Q2), which is formed by N-type epitaxy, P-type well, and N-type heavily doped in P-type well. ); The P-type heavily doped from the terminal Pin2 through the P-type well to the resistance one (R1) of the transistor two (Q2) base region; the N-type heavily doped from the terminal Pin1 through the N-type well to the transistor one (Q1) Resistance two (R2) of the base region; N-type heavy doping in the N-type through isolation connected from the terminal Pin1 is formed by the N-type through isolation, the N-type buried layer and the resistance of the N-type epitaxial layer Resistor three (R3); transistor one and two (Q1, Q2) and resistor one and two (R1, R2) form a thyristor structure, and a vertical triode (Q3) and resistor three (R3) form a vertical NPN structure As the current path at turn-on and small current, the breakdown voltage is controlled to be less than the trigger voltage of the thyristor. When the transient high voltage pulse reaches the Pin1 port, the vertical triode (Q3) turns on before the thyristor to form a current The current is used as the base current of the transistor two (Q2), or called the thyristor gate trigger current, and the thyristor structure is turned on to form a low-resistance current path; when the current is large, the thyristor is the main current path.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 11, wherein the semiconductor is a silicon wafer with an N-type substrate, an N-type buried layer, or a P-type epitaxial layer, or the The semiconductor is a silicon wafer with an N-type substrate and an N-type epitaxial layer, or the semiconductor is a silicon wafer with an N-type substrate and a P-type epitaxial layer.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 12, characterized in that the back surface of the N-type substrate is metalized, the back electrode is led out, and the frame and the frame connected to the front Pin1 are connected by conductive glue during packaging. Exposed pins.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 3, characterized in that:

The semiconductor body includes silicon wafers with an N-type substrate, an N-type buried layer, and an N-type epitaxial layer arranged in sequence. The N-type epitaxial layer is arranged side by side to the N-type buried layer. The surface junction thyristor structure and lateral NPN structure composed of N-type wells and P-type wells in the middle of the N-type to-through isolation,

The P-type well includes five heavily doped regions of N-type heavily doped, N-type heavily doped, P-type heavily doped, N-type heavily doped, and N-type heavily doped in sequence;

Both sides of the P-type well are provided with N-type wells with the same structure including N-type heavily doped N+ and P-type heavily doped P+ regions;

The two N-type wells are respectively provided with an N-type interconnection isolation including an N-type heavily doped N+ region on the outside;

The metal wiring of the surface junction thyristor structure is an insert finger design. The PNP transistor one (Q1) composed of P-type heavily doped, N-type well, and P-type well in the N-type well is composed of N-type well, P-type well, The N+ in the P-type well constitutes the second NPN transistor (Q2), and the vertical transistor (Q3) is formed by the N-type epitaxy, the P-type well, and the N+ in the P-type well. The P-type well is connected to the N+ and P-type wells of Pin1, The N+ connected to Pin2 in the P-type well forms a lateral triode (Q4); the P+ connected from Pin2 passes through the P-type well to the base of transistor two (Q2) to form a resistor one (R1), and the N+ connected from Pin1 passes through the N-type well Nwell to Transistor one (Q1) base region constitutes resistor two (R2), the N+ in the N-type in-to-through isolation connected from Pin1, through the N-type in-to-through isolation, the resistance from the N-type buried layer to the N-type epitaxial layer, constitutes the resistor three (R3 ), the resistance connected from Pin1 to N+ in the P-well is resistance four (R4);

Among them, one and two transistors (Q1, Q2) and resistors one and two (R1, R2) form a thyristor structure; a vertical triode (Q3) and a resistor three (R3) form a vertical NPN structure; a horizontal triode (Q4) and resistor four (R4) form a horizontal NPN structure, which controls the breakdown voltage of the vertical triode (Q3) and the horizontal triode (Q4) to be less than the trigger voltage of the thyristor. When the transient high voltage pulse reaches the Pin1 port, the vertical triode (Q3) and the lateral transistor (Q4) are turned on before the thyristor to form a small current path. This current is used as the base current of the transistor two (Q2) in the thyristor structure, and the thyristor structure is turned on to form a low resistance current path.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 14, wherein the semiconductor is a silicon wafer with an N-type substrate, an N-type buried layer, or a P-type epitaxial layer, or the The semiconductor is a silicon wafer with an N-type substrate and an N-type epitaxial layer, or the semiconductor is a silicon wafer with an N-type substrate and a P-type epitaxial layer.
The TVS device using a vertical triode to trigger a surface thyristor structure according to claim 14, characterized in that:

The back surface of the N-type substrate Nsub is metallized, and the back electrode is led out, and the frame connected to the front Pin1 and the exposed pins are connected through conductive glue during packaging.