CN107393915B - Transient voltage suppressor and method of manufacturing the same - Google Patents
Transient voltage suppressor and method of manufacturing the same Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
Abstract
The invention relates to a transient voltage suppressor and a manufacturing method thereof, wherein the transient voltage suppressor comprises a main Zener diode and at least one pair of a first diode and a second diode which are connected in series; the method comprises the following steps: sequentially forming a stacked N + type monocrystalline silicon substrate, an N type silicon epitaxial layer, a buffer oxidation layer and a silicon nitride layer; forming a plurality of first trenches in the epitaxial layer, wherein the first trenches isolate areas for forming the first diode, the second diode and the main Zener diode; forming a plurality of second grooves in the epitaxial layer, wherein the second grooves respectively separate corresponding doped regions in the regions where the first diode, the second diode and the main Zener diode are formed; forming the first diode, second diode, and main zener diode structures. The method and the device formed by the method have high current leakage capacity and low capacitance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a transient voltage suppressor and a manufacturing method thereof.
Background
With the development of electronic information technology, semiconductor devices are becoming more compact, high density and multifunctional, especially portable consumer electronic products have strict requirements on the area of a main board, and meanwhile, the response time of the devices is required to be fast to meet the transmission of high-speed data lines, and the devices are required to be prevented from being degraded after being subjected to multiple transient interferences of voltage and current so as to ensure the due quality of electronic equipment.
A Transient Voltage Suppressor (TVS) is used as a high-performance protection device for a silicon PN junction to solve these problems. The TVS device is suitable for the condition that the circuit board surface of the portable equipment is tense in high packaging integration level, and absorbs surge power of thousands of watts at a response speed of P seconds when being impacted by reverse transient high energy, so that precise components in an electronic circuit are effectively protected.
Since the video data line has a very high data transmission rate (above 1 GHZ), people put higher demands on TVS devices for video line protection: the capacitance of the TVS tube cannot be larger than 1.0PF so as to reduce the interference of parasitic capacitance to the circuit and reduce the attenuation of high-frequency circuit signals, and meanwhile, the ESD resistance is kept high.
The conventional TVS diode has a relatively simple manufacturing process, and adopts a micron-level process technology of discrete devices, such as a junction isolation technology and a local silicon oxidation isolation technology, which results in low integration level of the chip, small ESD resistance per unit area, and large capacitance of a main device, generally above 30PF, and obviously, the conventional TVS diode cannot meet the requirements of protection of a USB3.0 high-speed data line, application in digital video interfaces (transmission rate is up to above 1G), high-speed ethernet, ultra-thin notebook computers, monitors, and the like, because the TVS chip needs to have high current discharge capacity and low capacitance, so as to meet the requirements of electrostatic protection and the integrity requirements of data transmission.
Disclosure of Invention
In view of the above, there is a need for a method of manufacturing a transient voltage suppressor having high current sinking capability and low capacitance.
Further, the transient voltage suppressor is provided with a high current bleeding capability and a low capacitance.
A method of manufacturing a transient voltage suppressor, said transient voltage suppressor comprising a main zener diode and at least one pair of first and second diodes connected in series; the method comprises the following steps:
sequentially forming a stacked N + type monocrystalline silicon substrate, an N type silicon epitaxial layer, a buffer oxidation layer and a silicon nitride layer;
forming a plurality of first windows on the silicon nitride layer and the buffer oxide layer, and forming a plurality of first trenches in the epitaxial layer according to the plurality of first windows, wherein the plurality of first trenches isolate regions for forming the first diode, the second diode and the main Zener diode;
forming a P-type doped region at the bottom of the first trenches;
depositing a silicon dioxide insulating layer and a P-type polycrystalline silicon layer in sequence to fill the first groove;
sequentially removing the P-type polycrystalline silicon layer and the silicon dioxide insulating layer formed on the silicon nitride layer, and removing the silicon nitride layer to expose the buffer oxide layer;
forming a silicon nitride layer on the buffer oxide layer again;
forming a plurality of second windows on the silicon nitride layer and the buffer oxide layer which are formed again, and forming a plurality of second grooves in the epitaxial layer according to the plurality of second windows, wherein the plurality of second grooves respectively separate corresponding doped regions in the regions where the first diode, the second diode and the main Zener diode are formed;
forming the first diode, second diode, and main zener diode structures.
A transient voltage suppressor comprises a main Zener diode and at least one pair of first and second diodes connected in series;
a first groove filled with a silicon dioxide insulating layer and a P-type polycrystalline silicon layer is adopted among the main Zener diode, the first diode and the second diode for device isolation;
and the main Zener diode, the first diode and the second diode are all separated into corresponding doped regions by adopting second grooves filled with silicon dioxide insulating layers.
The method and the device (1) adopt the Shallow Trench Isolation (STI) technology of an advanced process platform to realize the high integration of the chip, and compared with the conventional TVS diode, the area of the chip is reduced by more than 30 percent;
(2) the trench isolation technology is combined with the chemical mechanical polishing process of silicon dioxide, so that complete planarization in device manufacturing is realized, the control of the process is facilitated, the stability of the device is obviously improved, and the yield of chip manufacturing is improved;
(3) the ESD current discharge capacity of the unit chip area of the device is greatly improved, and a system is effectively protected from being impacted by various transient high voltages;
(4) a high-voltage-resistant insulating layer is formed by adopting a Deep Trench Isolation (Deep Trench Isolation) technology, effective Isolation between devices is implemented, and the technical problem of parasitic transistor latch is fundamentally solved.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a TVS according to an embodiment;
FIGS. 2-12 are cross-sectional views of intermediate structures processed at various steps of FIG. 1;
FIG. 13 is a schematic view of an ion concentration distribution of a main Zener diode;
fig. 14 is a circuit configuration diagram of the transient high voltage suppressor.
Detailed Description
The following further description is made in conjunction with the accompanying drawings and examples.
Step S101: and sequentially forming a stacked N + type monocrystalline silicon substrate, an N type silicon epitaxial layer, a buffer oxide layer and a silicon nitride layer. As shown in fig. 2, specifically: an N-type silicon epitaxial layer 102 is epitaxially grown on the high-concentration N + -type single crystal silicon 101. A buffer oxide layer 103 is chemically vapor deposited on the surface of the epitaxial layer 102. A silicon nitride layer 104 is deposited on the buffer oxide layer 103 by a plasma enhanced chemical vapor deposition (pecvd) process. The thickness of the epitaxial layer 102 is 9-11 microns, and in this embodiment, 10 microns is used. The thickness of the silicon nitride layer 104 is 1.8 to 2.2 micrometers, and 2 micrometers is adopted in the embodiment. The buffer oxide layer is typically a silicon dioxide layer formed by thermal oxidation of silicon, and serves to buffer the transition between silicon and silicon nitride.
The parasitic NPN tube formed after the transient voltage suppressor is started can greatly enhance the current discharge capacity, and the substrate high-concentration N + is the NPN emitter and provides an electron source.
Step S102: a first window region is defined in the silicon nitride layer 104 using photoresist as a masking layer.
Step S103: and removing the silicon nitride layer and the buffer oxide layer by wet etching in the first window region to form a first window 105. Referring to fig. 3, first windows 105 are formed at a plurality of positions of the silicon nitride layer 104 and the buffer oxide layer 103. In this embodiment, a hot phosphoric acid solution is used to perform wet etching on the silicon nitride layer 104 and the buffer oxide layer 103 at multiple locations.
Step S104: a first trench 106 is formed in the epitaxial layer 102 using a plasma etch. The first trench 106 is obtained by plasma etching the epitaxial layer 102 according to the position defined by the first window 105. The depth of the first trench 106 is greater than 7 microns and less than the thickness (10 microns) of the epitaxial layer 102, and the aspect ratio of the first trench 106 is 10: 1-30: 1. It can be seen that the first trench 106 is deeper.
The structure after the processing in steps S102 to S104 is shown in fig. 3. The 2 first trenches 106 isolate a region 107 for forming the first diode, a region 108 for forming the second diode, and a region 109 for forming the main zener diode.
Step S105: a P-type doped region 110 is formed at the bottom of the plurality of first trenches. Refer to fig. 4. The method specifically comprises the following steps: carrying out vertical boron ion implantation and heat treatment activation; the dose of implanted boron ions is 1.0 × 1013cm-2～1.0×1014cm-2. Since the plasma etching trench of step S104 has an uneven portion at the bottom of the first trench 106, and the local electric field is concentrated and easy to break down, the P-type doped region 110 and the epitaxial layer 102 form a PN junction, and the reverse biased NP depletion layer can shield the external electric field and protect the bottom of the first trench 106 from breaking down.
Step S106: a silicon dioxide insulating layer 111 and a P-type polysilicon layer 112 are sequentially deposited to fill the first trench 106. The silicon dioxide insulating layer 111, which has a thickness greater than 0.1 μm, is formed on the sidewalls and bottom surface of the first trench 106 and the surface of the silicon nitride layer 104. The P-type polysilicon 112 fills the first trench 106 and is deposited on the surface of the silicon dioxide insulating layer 111. In other embodiments, other insulating and semi-insulating materials, such as partially oxidized polysilicon (semi-insulating polysilicon), silicon-rich silicon oxide (SRO), and other oxide materials, may be deposited in the first trench 106.
The structure after the processing of step S105 and step S106 is shown in fig. 4.
Step S107: the P-type polysilicon layer 112 and the silicon dioxide insulating layer 111 formed on the silicon nitride layer 104 are sequentially removed, and the silicon nitride layer 104 is removed to expose the buffer oxide layer 103. The method specifically comprises the following steps: grinding the P-type polysilicon layer 112 and the silicon dioxide insulating layer 111 by adopting a chemical mechanical polishing process, and stopping at the silicon nitride layer 104; the silicon nitride layer 104 is then etched using a hot phosphoric acid solution.
Step S108: a silicon nitride layer 113 is again formed on the buffer oxide layer 103. The thickness of the silicon nitride layer 113 formed again is 0.9 to 1.1 μm, and 1 μm is used in this embodiment.
The structure shown in fig. 4 is as shown in fig. 5 after being processed in step S107 and step S108.
Step S109: a plurality of second windows are formed on the silicon nitride layer 113 and the buffer oxide layer 103, and a plurality of second trenches 114 are formed in the epitaxial layer 102 according to the plurality of second windows, wherein the plurality of second trenches 114 respectively separate corresponding doped regions in regions where the first diode, the second diode and the main zener diode are formed. Referring to fig. 6, 2 second trenches 114 are formed in the first diode forming region 107 to separate 3 doped regions A, B, C; forming 2 second trenches 114 in the region 108 where the second diode is formed, separating 3 doped regions D, E, F; 2 second trenches 114 are formed in the region 109 where the primary zener diodes are formed, separating 3 doped regions G, H, I.
The step may specifically include: defining a second window region using photoresist as a masking layer on the re-formed silicon nitride layer 113; removing the silicon nitride layer 113 and the buffer oxide layer 103 formed again in the second window area by adopting wet etching; plasma etching is used to form the second trench 114 in the epitaxial layer 102. Wherein, hot phosphoric acid solution is adopted to corrode the silicon nitride layer 113; the buffer oxide layer 103 is etched with a hydrofluoric acid solution. The depth of the second trench 114 is 0.4 to 1.0 micron, and the depth of the second trench is 0.5 micron in this embodiment. It can be seen that the depth of the second trench 114 is shallow compared to the first trench 106.
Step S110: a silicon dioxide material is deposited to fill the second trench 114. As shown in fig. 7.
Step S111: the silicon nitride layer 113 and the silicon oxide layer formed again are sequentially removed. As shown in fig. 8.
Step S112: an N-type well is formed by implanting ions in a region for forming the first diode, and a P-type well is formed by implanting ions in a region for forming the second diode and the main Zener diode. Referring to fig. 9, N-type well 115 is formed by implanting ions in region 107, P-type well 116 is formed by implanting ions in region 108, and P-type well 117 is formed by implanting ions in region 109.
The step of implanting ions in the region 107 for forming the first diode to form the N-type well 115 includes:
using photoresist as a masking layer, positioning and windowing a region 107 for forming a first diode, injecting phosphorus ions and carrying out heat treatment; the dose of implanted phosphorus ions is 1.0 × 1012cm-2～1.0×1013cm-2；
Implanting ions in regions 108, 109 for forming the second diode and the main zener diode to form P- wells 116, 117 comprises:
using photoresist as a masking layer, positioning and windowing the regions 108 and 109 for forming the second diode and the main Zener diode, injecting boron ions and carrying out heat treatment; the dose of implanted boron ions is 1.0 × 1012cm-2～1.0×1013cm-2。
Step S113: and implanting ions into the P-type well 117 corresponding to the main Zener diode to form a deep P-type doped region 118. As shown in fig. 9. The method specifically comprises the following steps: using photoresist as a masking layer, positioning and windowing a preset region of the P-type well 117 corresponding to the main Zener diode, injecting boron ions and carrying out heat treatment; the energy of the implanted boron ions is greater than 120 keV.
Step S114: and implanting ions into the corresponding positions of the N-type well 115 corresponding to the first diode, the P-type well corresponding to the second diode and the P- type wells 116 and 117 corresponding to the main Zener diodes to form N + type doped regions 119, 120, 121, 122 and 123. As shown in fig. 10. The method specifically comprises the following steps: photoresist is used as a masking layer, and the N-type well 115 and the second diode corresponding to the first diode are respectively provided with a first electrode and a second electrodePositioning and windowing the corresponding positions of the P- type wells 116 and 117 corresponding to the tubes and the main Zener diodes, implanting arsenic ions and carrying out heat treatment; the dose of implanted arsenic ions is 2.0 × 1015cm-2～8.0×1015cm-2And the heat treatment time is more than 30 minutes.
Step S115: and implanting ions into the remaining positions of the N-type well 115 corresponding to the first diode, the P-type well corresponding to the second diode and the P- type wells 116 and 117 corresponding to the main Zener diodes to form P + type doped regions 124, 125, 126 and 127. As shown in fig. 11. The method specifically comprises the following steps: using photoresist as a masking layer, positioning windows at the rest positions of the N-type well 115 corresponding to the first diode, the P-type well corresponding to the second diode and the P- type wells 116 and 117 corresponding to the main Zener diode, and implanting indium ions for heat treatment; the dose of the implanted indium ions is 2.0 × 1015cm-2～8.0×1015cm-2And the heat treatment time is more than 30 minutes.
Step S116: a silicon dioxide insulating layer 128 and a fluorine ion doped silicon dioxide layer 129 are deposited. The thickness of the silicon dioxide layer 129 doped with fluorine ions is 5000-7000 angstroms, and the content of the fluorine ions is 4.0% -4.4%.
Step S117: and forming a metal contact hole, depositing a metal layer, and etching the metal layer to form a metal connecting line and a massive metal packaging wiring area. The main Zener diode, the PIN type low-capacitance diode and the NIP type low-capacitance diode are integrated together through metal connecting wires to form a complete protection circuit.
The structure after the processing of step S116 and step S117 is shown in fig. 12. Referring to fig. 11 and 12, N + doped region 119 is electrically connected to terminal 130 through metal deposited in the metal via, P + doped region 124 is electrically connected to terminal 131 through metal deposited in the metal via, N + doped region 120 is electrically connected to terminal 132 through metal deposited in the metal via, P + doped region 125 is electrically connected to terminal 133 through metal deposited in the metal via, N + doped region 121 is electrically connected to terminal 134 through metal deposited in the metal via, P + doped region 126 is electrically connected to terminal 135 through metal deposited in the metal via, P + doped region 127, N + doped region 122 is electrically connected to terminal 136 through metal deposited in the metal via, and N + doped region 123 is electrically connected to terminal 136 through metal deposited in the metal via.
The terminals 130 and 137 are both connected to the high voltage terminal VCC, the terminals 131 and 134 are connected to the same I/O terminal, and the terminals 135 and 136 are connected to the ground terminal GND.
It can be seen that forming a PN junction between the N-well region 115, the P + doped region 124 and the N + doped region 119 forming a first diode results in a first diode having a smaller capacitance, which may be referred to as a PIN diode.
Forming a PN junction between the P-well 116, P + doped 126 and N + doped 121 regions forming a second diode results in a second diode that also has a smaller capacitance and may be referred to as an NIP diode.
The PIN diode and the NIP diode are connected to the same I/O terminal.
In the region 117 where the main zener diode is formed, the N + doped region 123, the deep P doped region 118, the P-well 117, and the N + doped region 122 together form the structure of the main zener diode. The lateral doping concentration gradient is shown in fig. 13.
The resulting circuit structure of the transient high voltage suppressor is shown in fig. 14, which has a plurality of pairs of first and second diodes, each connected in parallel with a main zener diode. It should be noted that each of the diagrams of the method of the above embodiments only shows one pair of the first diode, the second diode and the main zener diode.
Based on the method, the transient high voltage suppressor comprises a main Zener diode and at least one pair of a first diode and a second diode which are connected in series; a first groove filled with a silicon dioxide insulating layer and a P-type polycrystalline silicon layer is adopted among the main Zener diode, the first diode and the second diode for device isolation;
the main Zener diode, the first diode and the second diode are all separated into corresponding doped regions by adopting second grooves filled with silicon dioxide insulating layers;
the depth of the second trench is greater than 1/10 of the depth of the first trench.
The method and the device have the following advantages:
(1) the high integration of the chip is realized by adopting the Shallow Trench Isolation (STI) technology of an advanced process platform, and compared with the conventional TVS diode, the chip area is reduced by more than 30%;
(2) the trench isolation technology is combined with the chemical mechanical polishing process of silicon dioxide, so that complete planarization in device manufacturing is realized, the control of the process is facilitated, the stability of the device is obviously improved, and the yield of chip manufacturing is improved;
(3) the ESD current discharge capacity of the unit chip area of the device is greatly improved, and a system is effectively protected from being impacted by various transient high voltages;
(4) a high-voltage-resistant insulating layer is formed by adopting a Deep Trench Isolation (Deep Trench Isolation) technology, effective Isolation between devices is implemented, and the technical problem of parasitic transistor latch is fundamentally solved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (17)
1. A method of manufacturing a transient voltage suppressor, said transient voltage suppressor comprising a main zener diode and at least one pair of first and second diodes connected in series; the method comprises the following steps:
sequentially forming a stacked N + type monocrystalline silicon substrate, an N type silicon epitaxial layer, a buffer oxidation layer and a silicon nitride layer;
forming a plurality of first windows on the silicon nitride layer and the buffer oxide layer, and forming a plurality of first trenches in the epitaxial layer according to the plurality of first windows, wherein the plurality of first trenches isolate regions for forming the first diode, the second diode and the main Zener diode;
forming a P-type doped region at the bottom of the first trenches;
sequentially depositing isolation material layers to fill the first trench;
sequentially removing the isolation material layer formed on the silicon nitride layer, and removing the silicon nitride layer to expose the buffer oxide layer;
forming a silicon nitride layer on the buffer oxide layer again;
forming a plurality of second windows on the silicon nitride layer and the buffer oxide layer which are formed again, and forming a plurality of second grooves in the epitaxial layer according to the plurality of second windows, wherein the plurality of second grooves respectively separate corresponding doped regions in the regions where the first diode, the second diode and the main Zener diode are formed;
forming the first diode, second diode, and main zener diode structures.
2. The method of claim 1, wherein the epitaxial layer has a thickness of 9 to 11 μm, and the silicon nitride layer formed in the step of sequentially forming the stacked N + -type single crystal silicon substrate, N-type silicon epitaxial layer, buffer oxide layer, and silicon nitride layer has a thickness of 1.8 to 2.2 μm.
3. The method of claim 1, wherein the step of forming a plurality of first windows in the silicon nitride layer and the buffer layer and forming a plurality of first trenches in the epitaxial layer according to the plurality of first windows comprises:
using photoresist as a masking layer on the surface of the silicon nitride layer, and defining a first window region;
removing the silicon nitride layer and the buffer oxide layer in the first window area by adopting wet etching to form a first window;
and forming the first groove in the epitaxial layer by adopting plasma etching.
4. The method of claim 3, wherein the wet etching is performed with a phosphoric acid solution.
5. The method of claim 2, wherein the first trench has a depth greater than 7 μm and less than the thickness of the epitaxial layer, and has an aspect ratio of 10:1 to 30: 1.
6. The method of claim 1, wherein the step of forming the P-type doped region at the bottom of the first trenches comprises:
carrying out vertical boron ion implantation and heat treatment activation; the dose of implanted boron ions is 1.0 × 1013cm-2～1.0×1014cm-2。
7. The method of manufacturing a transient voltage suppressor according to claim 1, wherein said spacer material layer comprises: and sequentially depositing a silicon dioxide insulating layer and a P-type polycrystalline silicon layer.
8. The method of claim 7, wherein the silicon dioxide insulating layer has a thickness greater than 0.1 microns.
9. The method according to claim 7, wherein the steps of sequentially removing the isolation material layer formed on the silicon nitride layer and removing the silicon nitride layer to expose the buffer oxide layer are specifically:
grinding the P-type polycrystalline silicon layer and the silicon dioxide insulating layer by adopting a chemical mechanical polishing process, and stopping at the silicon nitride layer;
and etching the silicon nitride layer by adopting a phosphoric acid solution.
10. The method of claim 1, wherein the thickness of the reformed silicon nitride layer is 0.9 to 1.1 μm.
11. The method of claim 1, wherein the step of opening a plurality of second windows in the silicon nitride layer and the buffer oxide layer and forming a plurality of second trenches in the epitaxial layer according to the plurality of second windows comprises:
defining a second window region on the reformed silicon nitride layer by using photoresist as a masking layer;
removing the silicon nitride layer and the buffer oxide layer in the second window region by adopting wet etching;
and forming the second groove in the epitaxial layer by adopting plasma etching.
12. The method of claim 11, wherein the step of removing the silicon nitride layer and the buffer oxide layer in the second window region by wet etching comprises:
corroding the silicon nitride layer by adopting a phosphoric acid solution;
and etching the buffer oxide layer by using hydrofluoric acid.
13. The method of claim 5, wherein the second trench has a depth of 0.4 to 1.0 μm.
14. The method of manufacturing a transient voltage suppressor of claim 1, wherein the step of forming said first diode, second diode and main zener diode structures comprises:
depositing a silicon dioxide material to fill the second trench;
sequentially removing the silicon nitride layer and the silicon dioxide layer which are formed again;
implanting ions in a region for forming the first diode to form an N-type well, and implanting ions in a region for forming the second diode and the main Zener diode to form a P-type well;
implanting ions into the P-type well corresponding to the main Zener diode to form a deep P-type doped region;
implanting ions into corresponding positions of the N-type well corresponding to the first diode, the P-type well corresponding to the second diode and the P-type well corresponding to the main Zener diode to form an N + type doped region;
injecting ions into the residual positions of the N-type trap corresponding to the first diode, the P-type trap corresponding to the second diode and the P-type trap corresponding to the main Zener diode to form a P + type doped region;
a silicon dioxide insulating layer and a fluorine ion doped silicon dioxide layer are deposited.
15. The method of manufacturing a transient voltage suppressor according to claim 14,
the step of implanting ions in the region for forming the first diode to form an N-type well includes:
using photoresist as a masking layer, positioning and windowing an area for forming a first diode, injecting phosphorus ions and carrying out heat treatment; the dose of implanted phosphorus ions is 1.0 × 1012cm-2～1.0×1013cm-2；
Implanting ions into regions for forming the second diode and the main zener diode to form a P-type well includes:
using photoresist as a masking layer, positioning and windowing a region for forming a second diode and a main Zener diode, injecting boron ions and carrying out heat treatment; the dose of implanted boron ions is 1.0 × 1012cm-2～1.0×1013cm-2；
Implanting ions into the P-type well corresponding to the main Zener diode to form a deep P-type doped region, wherein the deep P-type doped region comprises the following steps:
adopting photoresist as a masking layer, positioning and windowing a preset region of the P-type well corresponding to the main Zener diode, injecting boron ions and carrying out heat treatment; the energy of the injected boron ions is more than 120 kilo-electron volts;
implanting ions into corresponding positions of the N-type well corresponding to the first diode, the P-type well corresponding to the second diode and the P-type well corresponding to the main Zener diode to form an N + type doped region, wherein the N + type doped region comprises the following steps:
using photoresist as a masking layer, positioning and windowing corresponding positions of an N-type well corresponding to the first diode, a P-type well corresponding to the second diode and a P-type well corresponding to the main Zener diode, injecting arsenic ions and carrying out heat treatment; the dose of implanted arsenic ions is 2.0 × 1015cm-2～8.0×1015cm-2The heat treatment time is more than 30 minutes;
implanting ions into the remaining positions of the N-type well corresponding to the first diode, the P-type well corresponding to the second diode and the P-type well corresponding to the main Zener diode to form a P + type doped region, wherein the P + type doped region comprises:
using photoresist as a masking layer, positioning and windowing the rest positions of the N-type well corresponding to the first diode, the P-type well corresponding to the second diode and the P-type well corresponding to the main Zener diode, and injecting indium ions and carrying out heat treatment; the dose of the implanted indium ions is 2.0 × 1015cm-2～8.0×1015cm-2And the heat treatment time is more than 30 minutes.
16. The method of claim 14, wherein the fluorine ion doped silicon dioxide layer has a thickness of 5000 to 7000 angstroms and a fluorine ion content of 4.0 to 4.4%.
17. A transient voltage suppressor comprises a main Zener diode and at least one pair of first and second diodes connected in series; the method is characterized in that:
a first groove filled with a silicon dioxide insulating layer and a P-type polycrystalline silicon layer is adopted among the main Zener diode, the first diode and the second diode for device isolation, the first groove is arranged in an N-type epitaxial layer, and a P-type doped region is formed in the N-type epitaxial layer at the bottom of the first groove;
and the main Zener diode, the first diode and the second diode are all separated into corresponding doped regions by adopting second grooves filled with silicon dioxide insulating layers.
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| CN202473924U (en) * | 2011-12-13 | 2012-10-03 | 杭州士兰集成电路有限公司 | Ultra low capacitance transient voltage suppressor (TVS) |
| CN103390618A (en) * | 2013-07-12 | 2013-11-13 | 江苏艾伦摩尔微电子科技有限公司 | Embedded gate-grounded N-channel metal oxide semiconductor (NMOS)-triggered silicon-controlled transient voltage suppressor |
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| CN202473924U (en) * | 2011-12-13 | 2012-10-03 | 杭州士兰集成电路有限公司 | Ultra low capacitance transient voltage suppressor (TVS) |
| CN103390618A (en) * | 2013-07-12 | 2013-11-13 | 江苏艾伦摩尔微电子科技有限公司 | Embedded gate-grounded N-channel metal oxide semiconductor (NMOS)-triggered silicon-controlled transient voltage suppressor |
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