KR100281106B1 - Esd protection circuit and method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a suitable ESD (Electrostatic Discharge) protection circuit that effectively lowers the trigger voltage without increasing the area, and to a method of manufacturing the same. A device isolation film to be formed, a first conductivity type buried layer formed in the semiconductor substrate, a first conductivity type well and a second conductivity type well isolated from the semiconductor substrate by an element isolation film, and the second conductivity type well A second conductivity type first impurity region and a first conductivity type second impurity region formed in the surface of the formed semiconductor substrate, and a second conductivity type third formed in the surface of the semiconductor substrate on which the first conductivity type well is formed; And an impurity region and a first conductivity type fourth impurity region.

Description

ESDI PROTECTION CIRCUIT AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an ESD protection circuit suitable for low voltage triggering and a method for manufacturing the same.

Hereinafter, the ESD protection circuit of the related art will be described with reference to the accompanying drawings.

1 is a structural cross-sectional view showing a conventional ESD protection circuit.

As illustrated in FIG. 1, a plurality of device isolation layers 12 are formed on the P-type semiconductor substrate 11 at regular intervals, and N-wells 13 are formed on the surface of the semiconductor substrate 11, and the N The first high concentration n-type impurity region 14 and the first high concentration p-type impurity region 15 are formed in the surface of the semiconductor substrate 11 on which the wells 13 are formed.

Subsequently, a second high concentration n-type impurity region 16 and a second high concentration p-type impurity region 17 are formed in the surface of the other semiconductor substrate 11 where the N-well 13 is not formed.

In addition, an input line 18 is commonly connected to the first high concentration n-type impurity region 14 and the first high concentration p-type impurity region 15, and the second high concentration n-type impurity region 16 and the second high concentration The ground line 19 is commonly connected to the p-type impurity region 17.

The first high concentration p-type impurity region 15 is an anode region, and the second high concentration n-type impurity region 16 is a cathode region.

In the conventional ESD protection circuit as described above, the latch-up trigger voltage is determined by the junction breakdown voltage between the N-well 13 and the P-type semiconductor substrate 11. .

Therefore, in general, when a high voltage is applied to the input terminal, a triggering voltage of 40V or more is generated between the N-well 13 and the P-type semiconductor substrate 11, so that the ESD protection circuit may not operate smoothly.

FIG. 2 is a structural cross-sectional view showing another ESD protection circuit of the related art to compensate for the disadvantages of FIG.

As shown in Fig. 2, a plurality of element isolation films 22 of STI (Shallow Trench Isolation) type are formed on the P-type semiconductor substrate 21 at regular intervals, and N is formed in a predetermined region within the surface of the semiconductor substrate 21. A well 23 is formed, and first and second high concentration n-type impurity regions 24 and 25 are formed at regular intervals in the surface of the semiconductor substrate 21 on which the N-well 23 is formed. The first high concentration p-type impurity region 26 is formed in the surface of the semiconductor substrate 21 between the first and second high concentration n-type impurity regions 24 and 25.

Subsequently, a third high concentration n-type impurity region 27 and a second high concentration p-type impurity region 28 are formed in the surface of the semiconductor substrate 21 except that the N-well 23 is not formed.

In addition, an input line 29 is commonly connected to the first high concentration n-type impurity region 24 and the first high concentration p-type impurity region 26, and the third high concentration n-type impurity region 27 and the second high concentration The ground line 30 is commonly connected to the p-type impurity region 28.

The first high concentration p-type impurity region 26 is an anode region, and the third high concentration n-type impurity region 27 is a cathode region.

The second high concentration n-type impurity region 25 is formed at an interface between the N-well 23 and the P-type semiconductor substrate 21.

In the conventional ESD protection circuit having the above structure, as shown in FIG. 2, the trigger voltage is determined by the breakdown voltage between the N-well 13 and the P-type semiconductor substrate 11 as shown in FIG. 2 is determined by the Avalanche Breakdown voltage of the high concentration n-type impurity region 25.

However, in the ESD protection circuit of the prior art as described above has the following problems.

In other words, an additional N-type impurity region must be formed in the boundary region between the N-well and the semiconductor substrate, thereby taking up a larger area, and also forming another conducting path, thereby improving impedance. Is added to increase the ON resistance, making it unsuitable for undervoltage triggers.

An object of the present invention is to provide a method of manufacturing an ESD protection circuit that can artificially adjust a desired trigger voltage without increasing the area to solve the above problems.

1 is a structural cross-sectional view showing a ESD protection circuit of the prior art

Figure 2 is a structural cross-sectional view showing another ESD protection circuit of the prior art

Figure 3 is a structural cross-sectional view showing an ESD protection circuit according to the present invention

Figures 4a to 4b is a process cross-sectional view showing an ESD protection circuit according to the present invention

Explanation of symbols for main parts of the drawings

31 p-type semiconductor substrate 32 device isolation film

33: P type buried layer 34: N-well

35: P-well 36: first high concentration n-type impurity region

37: first high concentration p-type impurity region 38: second high concentration n-type impurity region

39: second high concentration p-type impurity region 40: input line

41: ground line

The ESD protection circuit according to the present invention for achieving the above object is a trench formed at a predetermined interval on the first conductive semiconductor substrate, an element isolation film formed in the trench, and a first formed in the semiconductor substrate A second conductive type agent formed in the surface of the semiconductor substrate on which the conductive buried layer, the first conductive type well and the second conductive type well are formed, and isolated from the semiconductor substrate by an element isolation film; A first impurity region, a first conductivity type second impurity region, and a second conductivity type third impurity region and a first conductivity type fourth impurity region formed in a surface of the semiconductor substrate on which the first conductivity type well is formed; Characterized in that configured.

In addition, the manufacturing method of the ESD protection circuit according to the present invention for achieving the above object comprises the steps of forming a trench with a predetermined interval on the first conductivity type semiconductor substrate, and forming a device isolation film in the trench; Forming a first conductive buried layer in the semiconductor substrate, forming a first conductive well and a second conductive well in the semiconductor substrate, and forming a surface of the semiconductor substrate on which the second conductive well is formed. Forming a second conductivity type first impurity region and a first conductivity type second impurity region therein, and a second conductivity type third impurity region and first conductivity in the surface of the semiconductor substrate on which the first conductivity type well is formed; And forming a type fourth impurity region.

Hereinafter, a method of manufacturing an ESD protection circuit according to the present invention with reference to the accompanying drawings in detail.

3 is a structural cross-sectional view showing an ESD protection circuit according to the present invention.

As shown in FIG. 3, trenches are formed in the P-type semiconductor substrate 31 at regular intervals, and an isolation layer 32 is formed in the trenches, and a p-type buried layer 33 is formed in the semiconductor substrate 31. N-wells 34 and P-wells 35 are formed on the semiconductor substrate 31 and separated from each other by the isolation layer 32.

Subsequently, a first high concentration n-type impurity region 36 and a first high concentration p-type impurity region 37 are formed on a surface of the semiconductor substrate 31 on which the N-well 34 is formed, and the P-well 35 is formed. The second high concentration n-type impurity region 38 and the second p-type impurity region 39 are formed in the surface of the semiconductor substrate 31 on which the () is formed.

In addition, an input line 40 is commonly connected to the first high concentration n-type impurity region 36 and the first high concentration p-type impurity region 37, and the second high concentration n-type impurity region 38 and the second high concentration. The ground line 41 is commonly connected to the p-type impurity region 39.

The first high concentration p-type impurity region 37 is an anode region, and the second high concentration n-type impurity region 38 is a cathode region.

4A through 4D are cross-sectional views illustrating a method of manufacturing an ESD protection circuit according to the present invention.

First, as shown in FIG. 4A, a plurality of trenches are formed in the P-type semiconductor substrate 31 at regular intervals.

Subsequently, an insulating film (not shown) is deposited on the entire surface of the semiconductor substrate 31 including the trench, and a CMP (Chemical Mechanical Polishing) process or an etch back process is performed so that the insulating film remains only inside the trench. In this manner, the device isolation film 32 is formed.

As shown in FIG. 4B, a P-type buried layer is implanted into the semiconductor substrate 31 by injecting boron ions, which are P-type impurity ions, with high energy into the entire surface of the semiconductor substrate 31 including the device isolation layer 32. (Buried Layer) 33 is formed.

As shown in FIG. 4C, P-type impurity ions and N-type impurity ions are selectively implanted into the semiconductor substrate 31, and then subjected to an annealing process, whereby N − is formed in the surface of the semiconductor substrate 31. Wells 34 and P-wells 35 are formed.

As shown in FIG. 4D, the first high concentration n-type impurity region 36 and the first high concentration are formed in the surface of the semiconductor substrate 31 on which the N-well 34 is formed using a conventional impurity ion implantation and diffusion process. The p-type impurity region 37 is formed.

At the same time, the second high concentration n-type impurity region 38 and the second high concentration p-type impurity region 39 are formed in the surface of the semiconductor substrate 31 on which the P-well 35 is formed.

Subsequently, an input line 40 is commonly connected to the first high concentration n-type impurity region 36 and the first high concentration p-type impurity region 37 to form the second high concentration n-type impurity region 38. Ground lines 41 connected to the second high concentration p-type impurity regions 39 are formed, respectively.

As described above, the ESD protection circuit and the method of manufacturing the same according to the present invention have the following effects.

First, it is possible to effectively lower the trigger voltage without increasing the area as in the prior art.

Second, the buried layer doping concentration and the anode-cathode spacing can be adjusted to optimize the ESD protection circuit.

Third, by forming the buried layer, the latch-up trigger characteristic according to the anode-cathode spacing becomes more sensitive, so that the adjustment range can be widened.

Claims (4)

Trenches formed on the first conductive semiconductor substrate at regular intervals; An isolation layer formed in the trench; A first conductivity type buried layer formed in said semiconductor substrate, A first conductivity type well and a second conductivity type well isolated from the semiconductor substrate by an isolation film; A second conductivity type first impurity region and a first conductivity type second impurity region formed in a surface of the semiconductor substrate on which the second conductivity type well is formed; And a second conductivity type third impurity region and a first conductivity type fourth impurity region formed in a surface of the semiconductor substrate on which the first conductivity type well is formed. The method of claim 1, And said first conductivity type is p-type and said second conductivity type is n-type. Forming trenches at regular intervals in the first conductivity type semiconductor substrate; Forming a device isolation layer in the trench; Forming a first conductivity type buried layer in the semiconductor substrate; Forming a first conductivity type well and a second conductivity type well on the semiconductor substrate; Forming a second conductivity type first impurity region and a first conductivity type second impurity region in a surface of the semiconductor substrate on which the second conductivity type well is formed; And forming a second conductivity type third impurity region and a first conductivity type fourth impurity region in a surface of the semiconductor substrate on which the first conductivity type well is formed. The method of claim 1, And the first conductive buried layer is formed by injecting boron ions at high energy into the entire surface of the semiconductor substrate.