CN100448007C - A grid-shaped electrostatic discharge protection device - Google Patents

Abstract

The invention relates to an electrostatic discharge protection device which utilizes polysilicon layout layers to construct an electrostatic current discharge channel. The antistatic effect of the existing thyristor SCR is not ideal, and the voltage value of the trigger point cannot be adjusted flexibly. In the present invention, a plurality of N+ implantation regions arranged in a planar array are arranged in a P well on a P-type substrate, and square-ring shallow moat isolation STIs are arranged along the four side walls of each N+ implantation region. A grid-shaped polysilicon layer is arranged above the P well, and the inner wall of the grid corresponds to the outer wall of the shallow moat isolation STI. The grid node positions of the polysilicon layer are P-type polysilicon regions or N-type polysilicon regions, and each P-type polysilicon region and N-type polysilicon region are arranged at intervals in each direction. A SiO₂ oxide layer is provided between the polysilicon layer and the P-type substrate. The invention effectively increases the effective area of the electrostatic current discharge channel, and at the same time, the voltage value of the trigger point can be adjusted by changing the length of the intrinsic polysilicon.

Description

A grid-shaped electrostatic discharge protection device

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to an electrostatic discharge protection device which utilizes polysilicon layout layers to construct electrostatic current discharge channels.

Background technique

Electrostatic discharge is an instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside to the inside when an integrated circuit is floating, and the whole process takes about 100ns. In addition, hundreds or even thousands of volts of high voltage will be generated when the integrated circuit is discharged, which will break through the gate oxide layer of the input stage in the integrated circuit. As the size of MOS transistors in integrated circuits is getting smaller and smaller, the thickness of the gate oxide layer is also getting thinner. Under this trend, high-performance electrostatic protection circuits are used to discharge electrostatic discharge charges to protect the gate. It is essential that the oxide layer is not damaged.

There are four main modes of ESD phenomena: Human Body Model (HBM), Mechanical Discharge Mode (MM), Charged Device Mode (CDM) and Field Induction Mode (FIM). For general integrated circuit products, it generally has to go through the tests of human body discharge mode, mechanical discharge mode and device charging mode. In order to be able to withstand such a high ESD voltage, integrated circuit products usually must use ESD protection devices with high performance and high endurance.

In order to achieve the purpose of protecting chips against electrostatic attacks, a variety of electrostatic protection devices have been proposed, such as diodes and MOS transistors with grounded gates. Among them, the silicon controlled rectifier (SCR) is recognized as a better protection device. The specific structure of the protection device is shown in FIG. 1 , the P-type substrate 11 is a well region, and the well region includes an N well 12 and a P well 19 . An N+ implantation region 14 and a P+ implantation region 15 are arranged on the N well 12 , wherein the N+ implantation region 14 is disposed at a position away from the P well 19 , and the P+ implantation region 15 is disposed at a position close to the P well 19 . The P well 19 is also provided with an N+ implantation region 17 and a P+ implantation region 18 , wherein the P+ implantation region 18 is disposed at a position away from the N well 12 , and the N+ implantation region 17 is disposed at a position close to the N well 12 . An inter-well N+ implantation region 16 is disposed above the junction of the N well 12 and the P well 19 and bridged between the N well 12 and the P well 19 . All implanted regions are isolated by shallow trench isolation STI 13. The N+ implantation region 14 and the P+ implantation region 15 of the N well 12 are connected to the electrical anode Anode, and the N+ implantation region 17 and the P+ implantation region 18 of the P well 19 are connected to the electrical cathode Cathode. Under normal operation of the integrated circuit, the electrostatic discharge protection device is in a closed state and will not affect the potential on the input and output bonding pads of the integrated circuit. When external static electricity is poured into the integrated circuit to generate an instantaneous high voltage, the device will turn on and discharge the static electricity quickly. However, the anti-static effect of the thyristor SCR in a harsh electrostatic environment is not ideal, and the voltage value of the trigger point cannot be adjusted flexibly.

Contents of the invention

The object of the present invention is to provide an electrostatic discharge protection device that can effectively improve the electrostatic protection capability and flexibly adjust the voltage value of the trigger point to address the shortcomings of the prior art.

The electrostatic discharge protection device of the present invention includes a P-type substrate on which a P well is arranged. A plurality of N+ implantation regions are arranged on the top of the P well, the N+ implantation regions are cubic, and the plurality of N+ implantation regions are arranged in a planar array. In the P well, there are square annular shallow trench isolation STIs along the four side walls of each N+ implantation region, and the inner walls of the square annular shallow trench isolation STIs are connected to the N+ implantation regions. A grid-shaped polysilicon layer is arranged above the P well, and the inner wall of the grid of the polysilicon layer corresponds to the outer wall of the square ring shallow trench isolation STI. The grid node positions of the polysilicon layer are respectively doped with P-type impurities or N-type impurities to become P-type polysilicon regions or N-type polysilicon regions. Each P-type polysilicon region and N-type polysilicon region are arranged alternately in each direction. Adjacent nodes Between the intrinsic polysilicon region. A SiO ₂ oxide layer is provided between the polysilicon layer and the P-type substrate.

The P-type substrate, N well and P well in the present invention adopt the structure and process corresponding to the existing thyristor SCR, and the _SiO2 oxide layer can be realized by using the existing common deposition and other processes. In the application, these arrayed N+ injection regions are staggeredly connected to the circuit, and the 4 N+ injection regions around the N+ injection region connected to the electrical anode are connected to the electrical cathode. Similarly, four N+ implantation regions around one N+ implantation region connected to the electrical cathode are connected to the electrical anode.

Based on the structure of the traditional SCR, the invention utilizes the grid-like polysilicon region to define the N+ injection region to form a parasitic triode structure in the body region, and meanwhile the grid-like polysilicon region itself can build a P-I-N structure to discharge static electricity. In this way, the parasitic triode in the body region and the polysilicon region are connected in parallel to form a parallel polysilicon discharge channel, which effectively increases the effective area of the electrostatic current discharge channel. Interlacing the parasitic triode electrodes in the body region and the P-I-N structure electrodes in the polysilicon region further effectively increases the effective area of the electrostatic current discharge channel. At the same time, the voltage value of the trigger point can be adjusted by changing the length of the intrinsic polysilicon. In this way, the protection device can flexibly adjust the voltage value of the trigger point, and at the same time increase the effective flow area of the electrostatic current.

Description of drawings

FIG. 1 is a schematic structural view of an existing thyristor SCR electrostatic discharge protection device;

Fig. 2 is the elevation structure schematic diagram of the present invention;

Fig. 3 is a schematic plan view of the present invention.

Detailed ways

The present invention will be further described in conjunction with the drawings and embodiments of the specification.

As shown in FIG. 2 and FIG. 3 , a grid-shaped electrostatic discharge protection device includes a P-type substrate 21 on which a P-well 22 is arranged. Above the P well 22 is a fishnet-shaped polysilicon region (24a, 24b, 24c), and just below the polysilicon region (24a, 24b, 24c) is the _SiO2 oxide layer 23 of the same shape, the lower surface of the _SiO2 oxide layer 23 and the P The upper surfaces of the wells 22 are in contact. The nodes (24a, 24c) of the fishnet-shaped polysilicon regions are doped with P-type impurities or N-type impurities to become P-type polysilicon regions 24a or N-type polysilicon regions 24c respectively, while adjacent nodes (P-type polysilicon regions 24a and N-type polysilicon regions 24a and N-type Intrinsic polysilicon regions 24b are provided between the polysilicon regions 24c). The P-type polysilicon region 24a and the N-type polysilicon region 24c are arranged at alternate spatial positions, that is, one P-type polysilicon region 24a is surrounded by four surrounding N-type polysilicon regions 24c. Similarly, one N-type polysilicon region 24c is surrounded by four surrounding P-type polysilicon regions 24a. A ring-shaped shallow trench isolation STI 25 is provided on the top of the P well corresponding to the hollowed-out part of the fishnet-shaped polysilicon region, and the outer wall of the shallow trench isolation STI 25 and the fishnet-shaped polysilicon region (24a, 24b, 24c) Corresponds to the position of the inner wall of the hollowed out part. An N+ implantation region 26 is provided in the ring inner region of the ring-shaped shallow trench isolation STI 25 , and the outer wall of the N+ implantation region 26 coincides with the inner wall of the shallow trench isolation STI 25 . Multiple N+ implantation regions 26 are arranged in a planar array. In the application, these arrayed N+ implantation regions 26 are interleavedly connected to the circuit, and four N+ implantation regions around the N+ implantation region 26 connected to the electrical anode are connected to the electrical cathode. Similarly, one is connected to the electrical cathode. Four N+ implantation regions around the N+ implantation region 26 of the electrical cathode are connected to the electrical anode.

During work, multiple polysilicon with P-I-N structure and internal parasitic triode are connected in parallel. When the electrical anode inputs a normal signal level, the protective device will not be turned on and interfere with the normal operation of the internal circuit of the chip. When a dangerous static signal arrives, the intrinsic polysilicon penetrates forward to discharge the static current, so that the input buffer can resist the external static shock.

Claims (1)

1. A grid-shaped electrostatic discharge protection device, comprising a P-type substrate, characterized in that a P-well is provided on the P-type substrate, and a plurality of N+ implantation regions are arranged on the top of the P-type well; the N+ implantation regions are cube-shaped , a plurality of N+ implant regions are arranged in a planar array; a square-ring shallow trench isolation STI is arranged along the four side walls of each N+ implant region in the P well, and the inner wall of the square-ring shallow trench isolation STI is connected to the N+ implant The grid-shaped polysilicon layer is arranged above the P well, and the grid inner wall of the polysilicon layer corresponds to the outer wall position of the square-ring shallow trench isolation STI; the grid node positions of the polysilicon layer are respectively doped with P-type impurities or N Type impurity becomes P-type polysilicon region or N-type polysilicon region, each P-type polysilicon region and N-type polysilicon region are arranged alternately in each direction, and the adjacent nodes are intrinsic polysilicon regions; the polysilicon layer and the P-type substrate There is a SiO ₂ oxide layer between them.

Images