CN100448007C - Grid-shaped electrostatic discharge protection device - Google Patents
Grid-shaped electrostatic discharge protection device Download PDFInfo
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- CN100448007C CN100448007C CNB2007100681351A CN200710068135A CN100448007C CN 100448007 C CN100448007 C CN 100448007C CN B2007100681351 A CNB2007100681351 A CN B2007100681351A CN 200710068135 A CN200710068135 A CN 200710068135A CN 100448007 C CN100448007 C CN 100448007C
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- 238000002347 injection Methods 0.000 claims abstract description 40
- 239000007924 injection Substances 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 239000013078 crystal Substances 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000003068 static effect Effects 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001012 protector Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to an electrostatic discharge protection device utilizing multicrystal silicon layout to hierarchically construct electrostatic current dumping channel. It is characterized by that in P trap on the P-type substrate N+injection zone several plane array arrangements is set, along peripheral side wall of every N+injection zone a shallow trench isolation STI with square-ring type is set, over P trap a grid-shaped multicrystal silicon layer is set, the inner wall of said grid is correspondent to the outer wall position of said shallow trench isolation STI. The grid node position of said multicrystal silicon layer is P-type multicrystal silicon zone or N-type multicrystal silicon zone, and between the multicrystal silicon layer and P-type substrate a SiO2 oxide layer is set.
Description
Technical field
The invention belongs to technical field of integrated circuits, particularly a kind of electrostatic discharge protection component that utilizes polysilicon domain schichtenaufbau electrostatic induced current leakage path.
Background technology
Static discharge is under the situation of an integrated circuit suspension joint, and a large amount of electric charges pours into the instantaneous process of integrated circuit from outside to inside, the about 100ns consuming time of whole process.In addition, can produce the high pressure of hundreds if not thousands of volts when integrated circuit discharges, this can punch the gate oxide of the input stage in the integrated circuit.Along with the size of the metal-oxide-semiconductor in the integrated circuit is more and more littler, the thickness of gate oxide is also more and more thinner, and under this trend, to be without prejudice be very essential with the protection grid oxic horizon for the electric charge of static discharge to use high performance electrostatic discharge protection circuit to release.
The pattern of static discharge phenomenon mainly contains four kinds: human body discharge mode (HBM), mechanical discharge mode (MM), part charging mode (CDM) and electric field induction pattern (FIM).Concerning general integrated circuit (IC) products, generally to pass through human body discharge mode, the test of mechanical discharge mode and part charging mode.In order to bear so high static discharge voltage, integrated circuit (IC) products must be used the electrostatic discharge protector with high-performance, high tolerance usually.
Resist the purpose that static attacks in order to reach the protection chip; at present existing multiple electrostatic protection device is suggested; such as diode, the metal-oxide-semiconductor of grounded-grid generally acknowledges that wherein the reasonable protective device of effect is controllable silicon SCR (silicon controlled rectifier).The concrete structure of this protective device is a well region on the P type substrate 11 as shown in Figure 1, and well region comprises N trap 12 and P trap 19.N trap 12 is provided with N+ injection region 14 and P+ injection region 15, and wherein N+ injection region 14 is arranged on the position away from P trap 19, and P+ injection region 15 is arranged on the position near P trap 19.Also be provided with N+ injection region 17 and P+ injection region 18 on the P trap 19, wherein P+ injection region 18 is arranged on the position away from N trap 12, and N+ injection region 17 is arranged on the position near N trap 12.N+ injection region 16 is arranged on N trap 12 and P trap 19 junctions top and is connected across between N trap 12 and the P trap 19 between one trap.Be to isolate between all injection regions with shallow trench isolation STI 13.The N+ injection region 14 and the P+ injection region 15 of N trap 12 meet electrical anode Anode, and the N+ injection region 17 and the P+ injection region 18 of P trap 19 meet electrical cathode Cathode.Under the normal running of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the integrated circuit input output joint sheet.And static externally pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, promptly emits electrostatic induced current.But the effect of this controllable silicon SCR antistatic under abominable static environment is not very desirable, and the trigger point voltage value can not be adjusted neatly simultaneously.
Summary of the invention
Purpose of the present invention is exactly at the deficiencies in the prior art, a kind of effective raising protection electrostatic capacity is provided and can adjusts the electrostatic discharge protection component of trigger point voltage value flexibly.
Electrostatic discharge protection component of the present invention comprises P type substrate, and P type substrate is provided with the P trap.Top in the P trap is provided with a plurality of N+ injection region, and the N+ injection region is a cubic type, and a plurality of N+ injection region is that planar array is arranged.Be provided with the shallow trench isolation STI of square ring type in the P trap along the four sides sidewall of each N+ injection region, the inwall of the shallow trench isolation STI of square ring type links to each other with the N+ injection region.P trap top is provided with latticed polysilicon layer, and the grid inwall of polysilicon layer is corresponding with the outer wall position of the shallow trench isolation STI of square ring type.The grid node position of polysilicon layer is mixed p type impurity or N type impurity respectively, becomes P type multi-crystal silicon area or N type multi-crystal silicon area, and each P type multi-crystal silicon area and N type multi-crystal silicon area alternately are provided with on all directions, are the intrinsic polysilicon district between the adjacent node.Be provided with SiO between polysilicon layer and the P type substrate
2Oxide layer.
P type substrate, N trap and P trap among the present invention adopts the structure and the technology of existing controllable silicon SCR correspondence, SiO
2Oxide layer adopts existing general technologies such as deposit to realize.The N+ injection region of these array-likes is linked in the circuit alternately and goes in application, and 4 N+ injection regions on every side of receiving the N+ injection region of electrical anode are linked in the electrical cathode.Same, 4 the N+ injection regions on every side that are linked into the N+ injection region of electrical cathode are linked into electrical anode.
The present invention utilizes latticed polysilicon region definition N+ injection region to form the parasitic triode structure in tagma on the architecture basics of traditional SCR, and latticed polysilicon region itself can make up the P-I-N structure electrostatic induced current of releasing simultaneously.Parasitic triode and polysilicon region parallel connection by the tagma constitutes polysilicon leakage path in parallel like this, effectively increased the effective area of electrostatic induced current leakage path.The staggered effective area that has further increased the electrostatic induced current leakage path effectively that makes up of electrode with the P-I-N structure of the parasitic triode electrode in tagma and polysilicon region.Can adjust the magnitude of voltage of trigger point simultaneously by the length that changes intrinsic polysilicon.This protective device can be adjusted the magnitude of voltage of trigger point neatly like this, has increased the valid circulation area of electrostatic induced current simultaneously.
Description of drawings
Fig. 1 is the structural representation of existing controllable silicon SCR electrostatic discharge protection component;
Fig. 2 is a facade structures schematic diagram of the present invention;
Fig. 3 is a planar structure schematic diagram of the present invention.
Embodiment
The present invention will be further described in conjunction with Figure of description and embodiment.
As shown in Figures 2 and 3, a kind of grid-shaped electrostatic discharge protection device comprises P type substrate 21, and P type substrate is provided with P trap 22.P trap 22 tops are that (24c), (24a, 24b are the SiO of same shape under 24c) to polysilicon region for 24a, 24b for the polysilicon region of fishing net shape
2Oxide layer 23, SiO
2The upper surface of the lower surface of oxide layer 23 and P trap 22 contacts.(the 24a of node place of the polysilicon region of fishing net shape, 24c) p type impurity or N type impurity have been mixed, become P type multi-crystal silicon area 24a or N type multi-crystal silicon area 24c respectively, and be provided with intrinsic polysilicon zone 24b between the adjacent node (P type multi-crystal silicon area 24a and N type multi-crystal silicon area 24c).P type multi-crystal silicon area 24a and N type multi-crystal silicon area 24c are set to locus alternately, and promptly P type multi-crystal silicon area 24a quilt 4 N type multi-crystal silicon area 24c on every side surround.Same, N type multi-crystal silicon area 24c quilt 4 P type multi-crystal silicon area 24a on every side surround.Openwork part in the polysilicon region of the corresponding fishing net shape in the top in the P trap is provided with the shallow trench isolation STI 25 of a ring-type, polysilicon region (the 24a of the outer wall of shallow trench isolation STI 25 and fishing net shape, 24b, 24c) the inner wall position correspondence of the openwork part in.The ring inner region of the shallow trench isolation STI 25 of ring-type is provided with N+ injection region 26, and the inwall of the outer wall of N+ injection region 26 and shallow trench isolation STI 25 overlaps.Arrange for planar array a plurality of N+ injection region 26.The N+ injection region 26 of these array-likes is linked in the circuit alternately and goes in application, 4 N+ injection regions on every side of receiving the N+ injection region 26 of electrical anode are linked in the electrical cathode, same, 4 the N+ injection regions on every side that are linked into the N+ injection region 26 of electrical cathode are linked into electrical anode.
In the work, the polysilicon of a plurality of P-I-N structures and the parallel connection of endobiosis triode.When electrical anode input normal signal level, this protective device can conducting not disturb the normal % of chip internal circuit to do.And when the electrostatic signal of danger arrives, thereby the intrinsic polysilicon forward connects the electrostatic induced current of releasing, thus make input buffer can resist extraneous electrostatic impact.
Claims (1)
1, a kind of grid-shaped electrostatic discharge protection device comprises P type substrate, it is characterized in that P type substrate is provided with the P trap, and the top in the P trap is provided with a plurality of N+ injection region; The N+ injection region is a cubic type, and a plurality of N+ injection region is that planar array is arranged; Be provided with the shallow trench isolation STI of square ring type in the P trap along the four sides sidewall of each N+ injection region, the inwall of the shallow trench isolation STI of square ring type links to each other with the N+ injection region; P trap top is provided with latticed polysilicon layer, and the grid inwall of polysilicon layer is corresponding with the outer wall position of the shallow trench isolation STI of square ring type; The grid node position of polysilicon layer is mixed p type impurity or N type impurity respectively, becomes P type multi-crystal silicon area or N type multi-crystal silicon area, and each P type multi-crystal silicon area and N type multi-crystal silicon area alternately are provided with on all directions, are the intrinsic polysilicon district between the adjacent node; Be provided with SiO between polysilicon layer and the P type substrate
2Oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100681351A CN100448007C (en) | 2007-04-19 | 2007-04-19 | Grid-shaped electrostatic discharge protection device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100681351A CN100448007C (en) | 2007-04-19 | 2007-04-19 | Grid-shaped electrostatic discharge protection device |
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| Publication Number | Publication Date |
|---|---|
| CN101047179A CN101047179A (en) | 2007-10-03 |
| CN100448007C true CN100448007C (en) | 2008-12-31 |
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| CNB2007100681351A Expired - Fee Related CN100448007C (en) | 2007-04-19 | 2007-04-19 | Grid-shaped electrostatic discharge protection device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11561216B2 (en) | 2012-02-13 | 2023-01-24 | Oxford Nanopore Technologies Plc | Apparatus for supporting an array of layers of amphiphilic molecules and method of forming an array of layers of amphiphilic molecules |
| US11596940B2 (en) | 2016-07-06 | 2023-03-07 | Oxford Nanopore Technologies Plc | Microfluidic device |
| US11789006B2 (en) | 2019-03-12 | 2023-10-17 | Oxford Nanopore Technologies Plc | Nanopore sensing device, components and method of operation |
| US12121894B2 (en) | 2017-11-29 | 2024-10-22 | Oxford Nanopore Technologies Plc | Microfluidic device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863803A (en) * | 2019-04-25 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | ESD protection device and electronic device |
| CN113488464B (en) * | 2021-09-08 | 2021-12-07 | 江苏应能微电子有限公司 | Transient voltage suppression protection device with grid-shaped cathode and anode groove structure |
| CN118299408B (en) * | 2024-06-05 | 2024-08-02 | 江苏应能微电子股份有限公司 | Highly doped polysilicon device and process for ESD protection |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020130366A1 (en) * | 2001-03-19 | 2002-09-19 | Yasuyuki Morishita | ESD protection circuit for a semiconductor integrated circuit |
| US20040135141A1 (en) * | 2003-01-09 | 2004-07-15 | International Business Machines Corporation | Electrostatic Discharge Protection Networks For Triple Well Semiconductor Devices |
| US20060049463A1 (en) * | 2004-09-08 | 2006-03-09 | Kil-Ho Kim | High voltage operating electrostatic discharge protection device |
| US20060081935A1 (en) * | 2004-10-18 | 2006-04-20 | Nec Electronics Corporation | ESD protection devices with SCR structures for semiconductor integrated circuits |
| US20060258067A1 (en) * | 2005-05-10 | 2006-11-16 | Samsung Electronics Co., Ltd. | Device for protecting against electrostatic discharge |
-
2007
- 2007-04-19 CN CNB2007100681351A patent/CN100448007C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020130366A1 (en) * | 2001-03-19 | 2002-09-19 | Yasuyuki Morishita | ESD protection circuit for a semiconductor integrated circuit |
| US20040135141A1 (en) * | 2003-01-09 | 2004-07-15 | International Business Machines Corporation | Electrostatic Discharge Protection Networks For Triple Well Semiconductor Devices |
| US20060049463A1 (en) * | 2004-09-08 | 2006-03-09 | Kil-Ho Kim | High voltage operating electrostatic discharge protection device |
| US20060081935A1 (en) * | 2004-10-18 | 2006-04-20 | Nec Electronics Corporation | ESD protection devices with SCR structures for semiconductor integrated circuits |
| US20060258067A1 (en) * | 2005-05-10 | 2006-11-16 | Samsung Electronics Co., Ltd. | Device for protecting against electrostatic discharge |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11561216B2 (en) | 2012-02-13 | 2023-01-24 | Oxford Nanopore Technologies Plc | Apparatus for supporting an array of layers of amphiphilic molecules and method of forming an array of layers of amphiphilic molecules |
| US11913936B2 (en) | 2012-02-13 | 2024-02-27 | Oxford Nanopore Technologies Plc | Apparatus for supporting an array of layers of amphiphilic molecules and method of forming an array of layers of amphiphilic molecules |
| US11596940B2 (en) | 2016-07-06 | 2023-03-07 | Oxford Nanopore Technologies Plc | Microfluidic device |
| US12121894B2 (en) | 2017-11-29 | 2024-10-22 | Oxford Nanopore Technologies Plc | Microfluidic device |
| US11789006B2 (en) | 2019-03-12 | 2023-10-17 | Oxford Nanopore Technologies Plc | Nanopore sensing device, components and method of operation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101047179A (en) | 2007-10-03 |
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Granted publication date: 20081231 Termination date: 20110419 |