CN104124243A - SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance - Google Patents
SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance Download PDFInfo
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- CN104124243A CN104124243A CN201410384998.XA CN201410384998A CN104124243A CN 104124243 A CN104124243 A CN 104124243A CN 201410384998 A CN201410384998 A CN 201410384998A CN 104124243 A CN104124243 A CN 104124243A
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Abstract
The invention discloses an SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance, and belongs to the field of an electronic science and technology. When an IC (Integrated Circuit) chip is in a non-electrifying state in the process of producing, packaging, testing and the like, the SCR structure which has a very strong electric static protection capacity is started; when the chip is in an electrifying state, the PNP structure which has a very strong latch resistance is started; therefore, an electrostatic protection device has a stronger static prevention capacity and a very strong latch resistance, so as to meet the demand of high voltage ESD prevention design. According to the structure, the electrostatic protection device is stronger in static prevention capacity and stronger in latch resistance, is capable of meeting the demand of high voltage ESD prevention design, and saving the area of the chip at the same time.
Description
Technical field
The invention belongs to electronic technology field, relate to SCR device, relate in particular to the SCR_PNP structure with strong anti-breech lock ability of the electrostatic defending (ElectroStatic Discharge, referred to as ESD) for IC chip.
Background technology
In the processes such as IC chip production, encapsulation, test, can touch a large amount of extraneous static electric charges, thereby form the phenomenon of static discharge.Along with dwindling and the use of various advanced technologies of processing procedure, IC chip more and more easily suffers the damage of static discharge.In order to ensure that IC chip avoids damage in static discharge process, improve the yields of chip, Electrostatic Protection Design is more and more subject to IC designer's attention.
Be as shown in Figure 1 traditional SCR device, it because having the strongest current drain ability and the antistatic capacity person of being designed extensive use under unit are; But it has the very low voltage that maintains, more than being not easy to reach supply voltage value, therefore there is larger breech lock hidden danger, easily cause IC chip normally to work, even damage.Conventional method is usually taking the antistatic capacity of sacrificing SCR device as cost, exchange its stronger anti-breech lock ability for, but in high-tension circuit, be still difficult to reach the designing requirement of anti-breech lock, make SCR device be difficult to be applied in the ESD protection Design of high-tension circuit.
As shown in Figure 2, in order to make SCR structure can meet the anti-breech lock requirement of high-tension circuit, we have proposed the structure of a kind of selectively unlocking SCR and PNP.IC chip is in the processes such as production, encapsulation, test, and in power-up state not, SCR structure is opened, and it has very strong antistatic capacity; When chip is during in power-up state, positive-negative-positive structure is opened, and it has very strong anti-breech lock ability; Thereby ensure that this electrostatic protection device has stronger antistatic capacity, there is again very strong anti-breech lock ability, can meet high pressure ESD protection Design demand.
Summary of the invention
The invention provides a kind of SCR_PNP structure for the strong anti-breech lock ability of having of ESD protection Design.This device is in the processes such as production, encapsulation, test, and SCR structure is opened, and carries out static discharge by it, and the ESD protective capacities under unit are is the strongest; Under electrifying condition, SCR structure can not be opened, and static discharge current is released by the positive-negative-positive structure of its parallel branch, the positive-negative-positive structure phenomenon of can not turning back, and voltage when its static discharge more than supply voltage, therefore has very strong anti-breech lock ability all the time.
Technical solution of the present invention is as follows:
A kind of SCR_PNP structure for the strong anti-breech lock ability of having of ESD protection Design, as shown in Figure 2, comprising: the N-type well region on P type well region, N epitaxial loayer on P type substrate, substrate on insulating barrier district, N epi region, N epitaxial loayer, field oxide district, polysilicon grid region, thin oxide layer district, the isolated area for isolated high-voltage device and low-voltage device, N-type heavily doped region, P type heavily doped region.Insulating barrier district is positioned at P type substrate top, N-type epitaxial region is positioned at the top in insulating barrier district, the one P type well region, the 2nd P type well region and the first N-type well region are positioned at the top of N-type epitaxial region, and a P type well region, between the 2nd P type well region and the first N-type well region, has insulating barrier between a P type well region and the 2nd P type well region.The first N-type heavily doped region and a P type heavily doped region are positioned at the top of a P type well region, the one P type heavily doped region is between the first N-type heavily doped region and the first N-type well region, and between a P type heavily doped region and the first N-type well region, there are part the first multi-crystal silicon area and field oxide district in surface.The second N-type heavily doped region and the 3rd N-type heavily doped region are positioned at the top of the 2nd P type well region, between the second N-type heavily doped region and the 3rd N-type heavily doped region, have the second multi-crystal silicon area.The 2nd P type heavily doped region is positioned at the top of N-type well region, and the 2nd P type heavily doped region is as anode; The first N-type heavily doped region and the 3rd N-type heavily doped region and the first multi-crystal silicon area publish in instalments by plain conductor together with as the negative electrode of device, the second N-type heavily doped region is connected by wire with a P type heavily doped region; The second multi-crystal silicon area is wired to low tension source.When application, device anode is connected to the pin port that needs protected chip, and device cathodes is connected to earth potential.
SCR_PNP structure for the strong anti-breech lock ability of having of ESD protection Design provided by the invention, is that the negative electrode N+ of conventional scr device and P trap contact position are exchanged, and is connected in the contact of P trap by switching tube low pressure NMOS with negative electrode N+ simultaneously.Its equivalent electric circuit as shown in Figure 3, when device is in the processes such as production, encapsulation, test, chip is in electrifying condition not, low-tension supply is unsettled, low pressure NMOS is in closed condition, and now SCR structure is easy to open, and current drain path is pathl, carry out static discharge by SCR device, the ESD protective capacities under unit are is the strongest; Under electrifying condition, low-tension supply connects high potential, low pressure NMOS opens, it can suppress the unlatching of SCR structure, static discharge current is released by the positive-negative-positive structure of its parallel branch, and current drain path is path2, the positive-negative-positive structure phenomenon of can not turning back, voltage when its static discharge more than supply voltage, therefore has very strong anti-breech lock ability all the time.
Some deformation programs of such scheme:
(1) as shown in Figure 4,, on the basis of structure shown in Fig. 2, P trap contact P+ bar is become to P+ and N+ distributes alternately.
(2) as shown in Figure 5, on the basis of structure shown in Fig. 2, P trap contact P+ bar is become to P+ and N+ distributes alternately, negative electrode N+ bar becomes N+ and P+ distributes alternately.
The invention has the beneficial effects as follows:
The invention provides a kind of SCR_PNP structure for the strong anti-breech lock ability of having of ESD protection Design.IC chip is in the processes such as production, encapsulation, test, and in power-up state not, SCR structure is opened, and it has very strong antistatic capacity; When chip is during in power-up state, positive-negative-positive structure is opened, and it has very strong anti-breech lock ability; Thereby ensure that this electrostatic protection device has stronger antistatic capacity, there is again very strong anti-breech lock ability, can meet high pressure ESD protection Design demand.This structure ensures that this electrostatic protection device has stronger antistatic capacity, has again very strong anti-breech lock ability, can meet high pressure ESD protection Design demand, has saved chip area simultaneously.
Brief description of the drawings
Fig. 1 is conventional SCR device profile schematic diagram.
Fig. 2 is the improved SCR_PNP generalized section with strong anti-breech lock ability of the first.
Fig. 3 is the improved SCR_PNP equivalent circuit diagram with strong anti-breech lock ability of the first.
Fig. 4 is the improved SCR_PNP generalized section with strong anti-breech lock ability of the second.
Fig. 5 is the third improved SCR_PNP generalized section with strong anti-breech lock ability.
Embodiment
In order to make technical problem to be solved by this invention, technical scheme and good effect clearer, below in conjunction with accompanying drawing, the present invention is further elaborated.
A kind of SCR_PNP structure for the strong anti-breech lock ability of having of ESD protection Design, as shown in Figure 2, comprising: the N-type well region on P type well region, N epitaxial loayer on P type substrate, substrate on insulating barrier district, N epi region, N epitaxial loayer, field oxide district, polysilicon grid region, thin oxide layer district, the isolated area for isolated high-voltage device and low-voltage device, N-type heavily doped region, P type heavily doped region.Insulating barrier district is positioned at P type substrate top, N-type epitaxial region is positioned at the top in insulating barrier district, the one P type well region, the 2nd P type well region and the first N-type well region are positioned at the top of N-type epitaxial region, and a P type well region, between the 2nd P type well region and the first N-type well region, has insulating barrier between a P type well region and the 2nd P type well region.The first N-type heavily doped region and a P type heavily doped region are positioned at the top of a P type well region, the one P type heavily doped region is between the first N-type heavily doped region and the first N-type well region, and between a P type heavily doped region and the first N-type well region, there are part the first multi-crystal silicon area and field oxide district in surface.The second N-type heavily doped region and the 3rd N-type heavily doped region are positioned at the top of the 2nd P type well region, between the second N-type heavily doped region and the 3rd N-type heavily doped region, have the second multi-crystal silicon area.The 2nd P type heavily doped region is positioned at the top of N-type well region, and the 2nd P type heavily doped region is as anode; The first N-type heavily doped region and the 3rd N-type heavily doped region and the first multi-crystal silicon area publish in instalments by plain conductor together with as the negative electrode of device, the second N-type heavily doped region is connected by wire with a P type heavily doped region; The second multi-crystal silicon area is wired to low tension source.When application, device anode is connected to the pin port that needs protected chip, and device cathodes is connected to earth potential.
SCR_PNP structure for the strong anti-breech lock ability of having of ESD protection Design provided by the invention, is that the negative electrode N+ of conventional scr device and P trap contact position are exchanged, and is connected in the contact of P trap by switching tube low pressure NMOS with negative electrode N+ simultaneously.Its equivalent electric circuit as shown in Figure 3, when device is in the processes such as production, encapsulation, test, chip is in electrifying condition not, low-tension supply is unsettled, low pressure NMOS is in closed condition, and now SCR structure is easy to open, and current drain path is pathl, carry out static discharge by SCR device, the ESD protective capacities under unit are is the strongest; Under electrifying condition, low-tension supply connects high potential, low pressure NMOS opens, it can suppress the unlatching of SCR structure, static discharge current is released by the positive-negative-positive structure of its parallel branch, and current drain path is path2, the positive-negative-positive structure phenomenon of can not turning back, voltage when its static discharge more than supply voltage, therefore has very strong anti-breech lock ability all the time.
Some deformation programs of such scheme:
(1) as shown in Figure 4,, on the basis of structure shown in Fig. 2, P trap contact P+ bar is become to P+ and N+ distributes alternately.
(2) as shown in Figure 5, on the basis of structure shown in Fig. 2, P trap contact P+ bar is become to P+ and N+ distributes alternately, negative electrode N+ bar becomes N+ and P+ distributes alternately.
In sum, the invention provides a kind of SCR_PNP structure for the strong anti-breech lock ability of having of ESD protection Design.IC chip is in the processes such as production, encapsulation, test, and in power-up state not, SCR structure is opened, and it has very strong antistatic capacity; When chip is during in power-up state, positive-negative-positive structure is opened, and it has very strong anti-breech lock ability; Thereby ensure that this electrostatic protection device has stronger antistatic capacity, there is again very strong anti-breech lock ability, can meet high pressure ESD protection Design demand.This structure ensures that this electrostatic protection device has stronger antistatic capacity, has again very strong anti-breech lock ability, can meet high pressure ESD protection Design demand, has saved chip area simultaneously.
The foregoing is only part embodiment of the present invention; only unrestricted the present invention for the present invention is described; any amendment of doing within every the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (3)
1. for a SCR_PNP structure for the strong anti-breech lock ability of having of ESD protection Design, comprising: the N-type well region on P type well region, N epitaxial loayer on P type substrate, substrate on insulating barrier district, N epi region, N epitaxial loayer, field oxide district, polysilicon grid region, thin oxide layer district, the isolated area for isolated high-voltage device and low-voltage device, N-type heavily doped region, P type heavily doped region.Insulating barrier district is positioned at P type substrate top, N-type epitaxial region is positioned at the top in insulating barrier district, the one P type well region, the 2nd P type well region and the first N-type well region are positioned at the top of N-type epitaxial region, and a P type well region, between the 2nd P type well region and the first N-type well region, has insulating barrier between a P type well region and the 2nd P type well region.The first N-type heavily doped region and a P type heavily doped region are positioned at the top of a P type well region, the one P type heavily doped region is between the first N-type heavily doped region and the first N-type well region, and between a P type heavily doped region and the first N-type well region, there are part the first multi-crystal silicon area and field oxide district in surface.The second N-type heavily doped region and the 3rd N-type heavily doped region are positioned at the top of the 2nd P type well region, between the second N-type heavily doped region and the 3rd N-type heavily doped region, have the second multi-crystal silicon area.The 2nd P type heavily doped region is positioned at the top of N-type well region, and the 2nd P type heavily doped region is as anode; The first N-type heavily doped region and the 3rd N-type heavily doped region and the first multi-crystal silicon area publish in instalments by plain conductor together with as the negative electrode of device, the second N-type heavily doped region is connected by wire with a P type heavily doped region; The second multi-crystal silicon area is wired to low tension source.When application, device anode is connected to the pin port that needs protected chip, and device cathodes is connected to earth potential.
2. a controlled LIGBT esd protection device with strong anti-breech lock ability, is on the basis of claim 1, P trap contact P+ bar is become to P+ and N+ distributes alternately.Other is identical.
3. a controlled LIGBT esd protection device with strong anti-breech lock ability, is on the basis of claim 1, P trap contact P+ bar is become to P+ and N+ distributes alternately, and negative electrode N+ bar becomes N+ and P+ distributes alternately.Other is identical.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410384998.XA CN104124243A (en) | 2014-08-07 | 2014-08-07 | SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance |
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| CN201410384998.XA CN104124243A (en) | 2014-08-07 | 2014-08-07 | SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108649028A (en) * | 2018-05-22 | 2018-10-12 | 湖南大学 | electrostatic protection device |
| CN111668209A (en) * | 2020-06-10 | 2020-09-15 | 电子科技大学 | Low-leakage silicon controlled rectifier for low-voltage ESD protection |
| WO2023279562A1 (en) * | 2021-07-08 | 2023-01-12 | 长鑫存储技术有限公司 | Identification method for latch-up structure |
-
2014
- 2014-08-07 CN CN201410384998.XA patent/CN104124243A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108649028A (en) * | 2018-05-22 | 2018-10-12 | 湖南大学 | electrostatic protection device |
| CN108649028B (en) * | 2018-05-22 | 2020-06-30 | 湖南大学 | Electrostatic protection device |
| CN111668209A (en) * | 2020-06-10 | 2020-09-15 | 电子科技大学 | Low-leakage silicon controlled rectifier for low-voltage ESD protection |
| CN111668209B (en) * | 2020-06-10 | 2022-03-15 | 电子科技大学 | Low-leakage silicon controlled rectifier for low-voltage ESD protection |
| WO2023279562A1 (en) * | 2021-07-08 | 2023-01-12 | 长鑫存储技术有限公司 | Identification method for latch-up structure |
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