CN102169881B - Power supply clamping structure method applied to high pressure process integrated circuit - Google Patents

Abstract

A power supply clamping structure applied to high-voltage process integrated circuits, including a single MLSCR device, which includes a P well and an N well, and a bridge-shaped P+ injection region between the P well and the N well, and the bridge-shaped P+ injection region The size ranges from 2.5 μm to 10.0 μm. The power supply clamping structure can also be cascaded with at least two of the above-mentioned single MLSCR devices, and the negative pole of each upper-level single MLSCR device is connected to the positive pole of the next-level single MLSCR device. It is connected by metal, and the anode of the first-level single MLSCR device is the positive pole of the cascade structure, and the negative pole of the last-level single MLSCR device is the negative pole of the cascade structure. This power supply clamping structure has a strong electrostatic protection capability per unit area. , the clamping voltage is controlled by adjusting the size of the bridge-shaped P+ injection region. With the multiplication of the cascaded series, the trigger voltage value and the clamping voltage value of the cascaded device will also be multiplied. It does not require many experimental calculations and is easy to popularize and apply. .

Description

A Power Supply Clamping Structure Applied in High-Voltage Process Integrated Circuits

technical field

The invention relates to the technical field of electrostatic discharge protection on semiconductor integrated circuit chips, in particular to a power supply clamping structure used in high-voltage process integrated circuits to avoid latch-up effects.

Background technique

Electrostatic discharge (ESD) phenomena are inevitable in the manufacture, transmission, and final system application of integrated circuit chips, and the energy released by ESD in an instant is very likely to damage the fragile devices in the IC chip. Therefore, it is very necessary to use a high-performance electrostatic protection circuit to clamp the voltage of each pin of the IC chip and discharge the ESD charge to protect the IC chip from damage.

At present, a variety of electrostatic protection devices have been proposed, such as diodes, GGNMOS, SCR and so on. However, in the process of implementing ESD protection for chips manufactured by high-voltage technology, since the operating voltage of such chips is usually relatively high, which can reach 20V-40V or even higher, the trigger voltage of the electrostatic protection module between the power supply and the ground must be high. at normal operating voltage.

If a multi-finger parallel GGNMOS structure is used, the NMOS here must use a high-voltage transistor in a high-voltage process, and for a high-voltage transistor, its primary breakdown voltage is much greater than the secondary breakdown voltage (vt2<<vt1 ), which will violate the basic condition of uniform conduction of multi-finger devices, that is, Vt1<Vt2, so the ESD protection capability of high-voltage NMOS devices connected in parallel with multiple fingers cannot be greatly improved on the basis of single-finger. Generally, resistance can be added to each finger of a multi-finger GGNMOS device to increase the secondary breakdown voltage value of the device, thereby improving the conduction uniformity, but the Vt2 of the high-voltage NMOS is much smaller than the Vt1 value, even in each The resistors connected in series in each finger still cannot satisfy the condition of uniform conduction between each finger, and it is difficult to achieve a high ESD protection capability.

If a multi-finger SCR structure is used, although the non-uniform conduction problem can be avoided and high electrostatic discharge protection capability can be achieved, if external noise appears on the port of the circuit, the SCR module between the power supply and the ground will be triggered by mistake, resulting in Low-resistance path, and the clamping voltage of the general SCR structure is very low, about 2 to 3V. At this time, the clamping voltage at the power supply is smaller than the working voltage of the circuit, and the low-impedance conduction between the power supply and the ground The state can be maintained all the time, thus forming a latch effect, which will eventually cause this part of the circuit to be burned.

Therefore, the electrostatic discharge protection circuit between the power supply and the ground in the high-voltage process integrated circuit must have the ability of uniform conduction and avoiding the latch-up effect caused by external noise.

In view of the above problems, there are three existing solutions disclosed in the literature as follows:

In Mingdou, Ker's paper "Design on latchup-free power-rail ESDclamp circuit in high-voltage CMOS ICs" (EOS/ESD Symposium 2004), different numbers of field oxide devices (FOD) are cascaded to achieve Multiplies the clamping voltage value of a single FOD device to achieve ESD protection without latch-up.

In Olivier Quittard's paper "ESD protection for high-voltage CMOStechnologies" (EOS/ESD Symposium 2006), the clamping power of a single MOSFET is multiplied by cascading different numbers of low-voltage GGNMOS or Gate-up PMOST (GUPMOS) field effect transistor devices. Bit voltage value to achieve ESD protection without latch-up effect.

The above two solutions are based on the fact that FOD devices and GGNMOS/GUPMOS devices have higher clamping voltages, and the expected clamping voltage value is achieved by cascading several identical FOD devices or MOS devices. However, the ESD protection capability per unit area of FOD devices and GGNMOS/GUPMOS is not high, and a large chip area needs to be sacrificed to achieve basic ESD protection indicators.

In the US patent US20090212323 "Silicon-Controlled Rectifier (SCR) devices for high-voltage Electrostatic Discharge (ESD) applications", a new SCR structure is proposed to increase the clamping voltage of a single SCR device structure. The new SCR structure replaces the emitter of the parasitic BJT of the traditional SCR device (the P+ emitter of the parasitic PNP and the N+ emitter of the parasitic NPN) in the vertical direction of the device by alternating P+ and N+ doping. The clamping voltage of the new SCR device will be greatly improved. By selecting the appropriate P+ and N+ doping area ratio, the clamping voltage can be adjusted so that the clamping voltage value is higher than the normal operating voltage range of the circuit, thereby effectively avoiding latch-up. shrinkage effect occurs. However, in the practical application of this invention, suitable parameters need to be selected: the distance between the positive pole and the negative pole, the area ratio of N+ and P+ doping, the selection of these parameters is to be based on more experiments, and it is difficult to obtain a wide range of parameters. application.

Contents of the invention

Aiming at the defects existing in the prior art, the object of the present invention is to provide a power supply clamping structure applied in high-voltage process integrated circuits, which has a very high electrostatic protection capacity per unit area, and can optimize the entire circuit design area. The size of the P+ injection region controls the clamping structure of the power supply, and as the number of cascaded series doubles, the trigger voltage value and clamping voltage value of the cascaded device also doubles. It does not require many experimental calculations and is easy to popularize and apply.

In order to achieve the above purpose, the technical solution adopted by the present invention is: a power supply clamping structure applied to high-voltage process integrated circuits, including a cascaded structure formed by at least two single MLSCR devices, and the single MLSCR device includes a P-well and N well, there is a bridge-shaped P+ implant region between the P well and the N well, and the size adjustment range of the bridge-shaped P+ implant region is between 2.5um and 10.0um; each upper-level single MLSCR device The negative electrode and the positive electrode of the next-level single MLSCR device are connected through a metal, and the positive electrode of the first-level single MLSCR device is the positive electrode of the cascade structure, and the negative electrode of the last-level single MLSCR device is the negative electrode of the cascade structure. The single MLSCR device adopts N-ring isolation, the single MLSCR devices adopt P-ring isolation, N-ring isolation is suspended, and P-ring isolation is grounded.

Wherein, the single MLSCR device includes a P-type substrate, an N epitaxial or N-Tub layer on the P-type substrate, and a well region on the N epitaxial or N-Tub layer, and the well region includes an N well and a P well. Both the well and the P well are provided with two implantation regions, which are N+ implantation regions and P+ implantation regions respectively.

Wherein, the N+ implantation region of the N well is arranged at an end far away from the P well, and the P+ implantation region is arranged at an end close to the P well; the P+ implantation region of the P well is arranged at an end far away from the N well, and the N+ implantation region is arranged at an end close to the N well. One end of the well; the N+ injection region and the P+ injection region are isolated by FOX.

Wherein, the single MLSCR device includes a P-type substrate, a buried layer on the P-type substrate, and a well region on the buried layer, and the well region includes a deep N well and a deep P well.

The beneficial effects of the present invention are:

1. The single MLSCR device has a bridge-shaped P+ injection region, which changes the forward breakdown voltage of the traditional SCR structure, and reduces the breakdown voltage from N-Well/P-Well (N Well/P Well) to N-Well/ P+ (N well/P+ injection region) junction breakdown voltage reduces the trigger voltage of SCR single device;

2. This type of single MLSCR device can be adjusted by adjusting the size of the P+ implanted region in the N well and the N+ implanted region in the P well, the distance between the P+ implanted region in the N well and the bridge-shaped P+ implanted region, and the distance between the N+ implanted region and the bridge in the P well. The distance between the bridge-shaped P+ injection region and the width of the bridge-shaped P+ injection region in the N-well and P-well to achieve a high clamping voltage. Selecting an appropriate size can make the clamping voltage of the single MLSCR device gradually approach the trigger voltage;

3. With the multiplication of the cascaded series of single MLSCR devices, through the effective isolation of N-ring and P-ring, the trigger voltage value and clamping voltage value of the cascaded devices will also be multiplied, and the appropriate number of cascaded devices should be selected. , can realize the power supply clamp electrostatic discharge protection circuit design without latching effect.

Description of drawings

Fig. 1 is the cross-sectional view of the single MLSCR device structure of the first embodiment of the present invention;

Figure 2 is a cross-sectional view of the cascaded structure of two single MLSCR devices in Figure 1;

Fig. 3 is a top view of the metal cascade in Fig. 2;

4 is a cross-sectional view of the structure of a single MLSCR device according to the second embodiment of the present invention;

FIG. 5 is a cross-sectional view of the cascaded structure of two single MLSCR devices in FIG. 4 .

Fig. 6 is a TLP test characteristic diagram of the cascaded structure of single MLSCR devices with different numbers of the present invention.

Reference signs:

The first embodiment: P-type substrate 1a, N epitaxial or N-Tub layer 2a, N well 3a, P well 4a, N+ implantation regions (21a, 31a, 41a), P+ implantation regions (22a, 41a, 42a), FOX 5a, bridge-shaped P+ injection region 6a, a layer of metal 54, a second layer of metal 56, and a hole 55.

Second embodiment: P-type substrate 1b, buried layer 2b, deep N well 3b, deep P well 4b, N+ implantation regions (21b, 31b, 41b), P+ implantation regions (22b, 41b, 42b), FOX 5b, Bridge-shaped P+ injection region 6b.

Detailed ways

Embodiments of the present invention will be described in further detail below in conjunction with the accompanying drawings.

As shown in Figure 1, it is the basic unit of the cascaded structure of the first embodiment of the present invention, the structural cross-sectional view of the single MLSCR device, which includes a P-type substrate 1a, and the P-type substrate 1a is N epitaxy or On the N-Tub layer 2a, the N epitaxy or the N-Tub layer 2a is a well region, and the well region includes an N well 3a and a P well 4a. Both the N well 3a and the P well 4a are provided with two implanted regions, namely the N+ implanted region 31a and the P+ implanted region 32a on the N well 3a; and the N+ implanted region 41a and the P+ implanted region 42a on the P well 4a. Wherein the N+ implantation region 31a of the N well 3a is arranged at an end away from the P well 4a, and the P+ implantation region 32a is arranged at an end close to the P well 4a; the P+ implantation region 42a of the P well 4a is arranged at an end far away from the N well 3a, and the N+ implantation The region 41a is set at one end close to the N well 3a; the N+ implantation region and the P+ implantation region on the N well 3a and the P well 4a are isolated by FOX 5a. At the junction of the N well 3a and the P well 4a, there is a bridge-shaped P+ injection region 6a connecting the N well 3a and the P well 4a. The N+ implantation region 31a and the P+ implantation region 32a in the N well 3a constitute the anode of the monolithic MLSCR device, and the N+ implantation region 41a and the P+ implantation region 42a in the P well 4a constitute the negative pole of the monolithic MLSCR device. The width dimension of the N+ implantation region 31a in the N well 3a, the P+ implantation region 32a and the N+ implantation region 41a in the P well 4a, the P+ implantation region 42a is D1, and the widths of the isolation FOX5a on the N well 3a and the P well 4a are respectively are D2 and D5, the width of the bridge-shaped P+ implantation region 6a in the N well 3a is D3, and the width in the P well 4a is D4. By adjusting the sizes of D1, D5, D3 and D4, a high clamping voltage can be realized. Selecting appropriate values of D3 and D4 can make the clamping voltage gradually approach the trigger voltage. In this embodiment, the bridge-shaped P+ injection region 6a The width, that is, the size adjustment range is between 2.5um and 10.0um.

As shown in Figure 2, it is the first embodiment of the present invention, two single MLSCR device cascaded structure, the negative electrode of the first level single MLSCR device is composed of N+ implantation region 41a and P+ implantation region 42a in P well 4a; The anode of the second-level single MLSCR device is composed of the N+ implantation region 31a and the P+ implantation region 32a in the N well 3a; the negative pole of the first-level single MLSCR device and the positive pole of the second-level single MLSCR device pass through connected together. The anode of the first-level SCR single device is reserved, and the N+ injection region 31a and the P+ injection region 32a in the N well 3a are used as the anode of the cascaded structure, which is not connected to metal. The negative electrode of the second-level single MLSCR device is reserved, and the N+ implantation region 41a and the P+ implantation region 42a in the P well 4a are used as the negative electrode of the cascade structure, which is not connected to the metal. The N epitaxial or N-Tub layer 2a of the two-stage monolithic MLSCR device is biased, that is, the N-ring (consisting of two N+ injection regions 21a) is suspended, and the P-ring (consisting of two P+ The injection region 22a constitutes) isolation, and the P-ring is grounded (GND).

As shown in Figure 3, it is the metal cascade top view of the first embodiment, the positive and negative electrodes of each single MLSCR device are covered with a layer of metal 54, and the cascade between each two single MLSCR devices uses two layers The metal 56 is connected, and the first layer of metal 54 and the second layer of metal 56 are interconnected by holes 55 .

As shown in Figure 4, it is a cross-sectional view of the structure of a single MLSCR device in the second embodiment of the present invention. The structure is basically the same as that of the single MLSCR device in the first embodiment, and can be regarded as the single MLSCR device in the first embodiment. The difference is that the N epitaxial or N-Tub region 2a is replaced with a buried layer 2b, the N well 3a is replaced with a deep N well 3b, and the P well 4a is replaced with a deep P well 4b, that is, the single MLSCR device includes a P-type lining The bottom 1b is a buried layer 2b on the P-type substrate 1b, and a well region is formed on the buried layer 2b, and the well region includes a deep N well 3b and a deep P well 4b. The N+ implant region 31b and the P+ implant region 32b in the deep N well 3b described in this embodiment and the N+ implant region 41b and the P+ implant region 42b in the deep P well 4b have a width of D1, and the deep N well 3b and the deep N well 4b have a width of D1. The widths of the isolation FOX 5b on the P well 4b are D2 and D5 respectively, the width of the bridge-shaped P+ implantation region 6b in the deep N well 3b is D3, and the width in the deep P well 4b is D4. Adjusting the sizes of D1, D5, D3, and D4 can realize a high clamping voltage, and selecting appropriate values of D3 and D4 can make the clamping voltage gradually approach the trigger voltage.

Of course, in other embodiments, the single MLSCR device can also be replaced with a related extended structure. Referring to FIG. 3, the N epitaxial or N-Tub layer 2a on the P-type substrate 1b can be replaced by other N-type lightly doped layers , the N well 3a can be replaced by an N-type doped layer whose doping concentration is deeper than that of the N epitaxy or N-Tub layer 2a (or other N-type shallow doped layers) and shallower than the N+ implantation region 31a, and the P well 4a can be doped The P-type doped layer whose concentration is deeper than the N epitaxial or N-Tub layer 2a (or other shallow N-type doped layer) and shallower than the P+ implantation region 42a is replaced.

As shown in Figure 5, it is a cross-sectional view of the cascaded structure of the second embodiment. The negative electrode of the first-level monomer MLSCR device is composed of an N+ implantation region 41b and a P+ implantation region 42b in a deep P well 4b; the second-level monomer The anode of the MLSCR device is composed of the N+ injection region 31b and the P+ injection region 32b in the deep N well 3b; the cathode of the first-level single MLSCR device and the anode of the second-level single MLSCR device are connected together through metal. The N+ implantation region 31b and the P+ implantation region 32b in the deep N well of the first-level SCR single device are reserved as the positive electrode of the cascade structure. The N+ implantation region 41b and the P+ implantation region 42b in the deep P well 4b of the second-level single MLSCR device are reserved as the negative electrode of the cascade structure. A certain interval width is controlled between the two-stage MLSCR monomers. The interval width value needs to meet the minimum value specified in the corresponding process rules to achieve no latch-up effect. The interval connects the P-type substrate and the Ground (GND).

As shown in Figure 6, it is the current-voltage (I-V) characteristic diagram after the TLP test of the cascaded structure TLP of different numbers of single MLSCR devices (the hollow icons indicate the corresponding leakage current values), in which there are single MLSCR Devices, two MLSCR devices cascaded, three MLSCR devices cascaded, four MLSCR devices cascaded graphical representation, as the number of cascaded stages multiplies, the trigger voltage value and clamping voltage value of cascaded single MLSCR devices Also followed by doubling. By selecting the appropriate number of SCR cascades, the design of the power supply clamp electrostatic discharge protection circuit without latch effect can be realized.

The present invention is not limited to the above-mentioned embodiments. For those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications are also considered protection of the present invention. within range.

Claims (4)

1. A power supply clamping structure applied to high-voltage process integrated circuits, comprising a cascaded structure formed by at least two single MLSCR devices, said single MLSCR device comprising a P well and an N well, characterized in that: said P There is a bridge-shaped P+ implantation region between the well and the N-well, and the size adjustment range of the bridge-shaped P+ implantation region is between 2.5um and 10.0um; the negative electrode of each upper-level monomer MLSCR device and the lower-level monomer The anode of the MLSCR device is connected by a metal, and the anode of the first-stage monomer MLSCR device is the cathode of the cascade structure, and the cathode of the last-stage monomer MLSCR device is the cathode of the cascade structure, and the monomer MLSCR device adopts N- Ring isolation, P-ring isolation is used between single MLSCR devices, N-ring isolation is suspended, and P-ring isolation is grounded. 2. The power supply clamping structure applied to high-voltage process integrated circuits as claimed in claim 1, wherein the single MLSCR device includes a P-type substrate, and the P-type substrate is an N epitaxy or N-Tub layer , the N epitaxial or N-Tub layer is a well region, and the well region includes an N well and a P well, and both the N well and the P well are provided with two implantation regions, which are respectively an N+ implantation region and a P+ implantation region. 3. The power supply clamping structure applied in high-voltage process integrated circuits as claimed in claim 2, characterized in that: the N+ injection region of the N well is arranged at an end far away from the P well, and the P+ injection region is arranged at an end close to the P well. One end; the P+ injection region of the P well is set at the end far away from the N well, and the N+ injection region is set at the end close to the N well; the N+ injection region and the P+ injection region are isolated by FOX. 4. The power supply clamping structure applied to high-voltage process integrated circuits as claimed in claim 1, wherein the single MLSCR device comprises a P-type substrate, the P-type substrate is a buried layer, and the buried layer is The well region includes a deep N well and a deep P well.

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