CN110556416A - Low-residual-voltage large-surge unidirectional snapback TVS device and manufacturing method thereof - Google Patents
Low-residual-voltage large-surge unidirectional snapback TVS device and manufacturing method thereof Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 17
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- 238000002513 implantation Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000002457 bidirectional effect Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- NUHSROFQTUXZQQ-UHFFFAOYSA-N isopentenyl diphosphate Chemical compound CC(=C)CCO[P@](O)(=O)OP(O)(O)=O NUHSROFQTUXZQQ-UHFFFAOYSA-N 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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Abstract
The invention discloses a low residual voltage large surge unidirectional snapback TVS device and a manufacturing method thereof, wherein the TVS device comprises an N-type substrate, a P-type epitaxial layer is arranged above the N-type substrate, an SN layer and an SP layer are arranged on the P-type epitaxial layer, and the SN layer and the SP layer are used for isolating a trench through a deep groove.
Description
Technical Field
the invention relates to the technical field of semiconductor electronic devices, in particular to a TVS device with low residual voltage and large surge and a manufacturing method thereof.
Background
The Transient Voltage Suppressor (TVS) is widely applied to various electronic products, and in contrast to a low-frequency electrostatic event of a data port, a battery port is continuously impacted by surge current in a power plugging and unplugging process, and power voltages of VBAT and VBUS ends of a battery module have different requirements, for example, the power voltage of the VBAT end is generally 4.5V, and the power voltage of the VBUS end is different from 7V to 26V. Different battery module schemes and different test stress conditions thereof require TVS to provide a series of products that can accommodate various supply voltages and cooperate with OVP protection schemes. The TVS not only can quickly bypass the large surge in the breakdown direction and the forward conduction direction to the ground, but also can provide low clamping voltage for the rear stage in both directions, so that the master control IC is not damaged. On the other hand, in the trend of miniaturization of electronic products, the TVS of VBAT & VBUS terminal needs to be continuously technically improved, and new technology is adopted to realize the performance of higher power density and lower clamping voltage under a smaller package body so as to meet the requirements of products with high integration level, small size and portability.
As shown in fig. 1, a conventional unidirectional TVS device cannot obtain a larger IPP and a lower residual voltage in the VBR direction of the conventional unidirectional TVS, and increasing the surge current capability of the TVS usually increases the area of the PN junction, but simply increasing the area may cause a series of problems: the area of the TVS device is increased, so that a larger packaging body is used, and the requirement of an application terminal on miniaturization cannot be met. And secondly, the cost is increased and the product competitiveness is reduced by simply increasing the TVS junction area. Lowering VBR can lower the residual voltage of the device to some extent, but brings about a problem of an increase in leakage current.
As shown in fig. 2, the bidirectional TVS device with a bidirectional NPN structure has an NPN negative resistance structure, which has the advantages of reducing VBR to reduce residual voltage and reducing leakage current, because the limiting power of the diodes with the same area during surge is close, and the IPP value is greatly increased by the formula PPP (IPP × VC), when the clamping voltage VC is reduced more, but has the disadvantage that when a negative surge occurs, the current must be released to break down the VBR direction, and the residual voltage must be much higher.
Therefore, in summary, the unidirectional PN junction and the bidirectional NPN have advantages and disadvantages, and it is difficult for one structure to satisfy the product design with high power density and low clamping voltage.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a low residual voltage large surge unidirectional snapback TVS device and a manufacturing method thereof.
The technical scheme of the invention is as follows:
A TVS device with low residual voltage and large surge in one-way snapback comprises an N-type substrate (Nsub), wherein a P-type epitaxial layer is arranged above the N-type substrate, an SN layer and an SP layer are arranged on the P-type epitaxial layer, and the SN layer and the SP layer are isolated through a deep groove.
The manufacturing method of the low residual voltage large surge unidirectional snapback TVS device comprises the following steps:
step A: selecting an N + substrate/P type epitaxial wafer;
And B: forming an SN layer by ion implantation after photoetching definition is carried out on the P type epitaxial layer;
And C: after photoetching definition is carried out on the P type epitaxial layer, an SP layer is formed through ion implantation;
Step D: carrying out RTP annealing on the SN layer and the SP layer at the same time, and activating the injection elements;
step E: dry etching the deep isolation groove on the P type epitaxial layer till reaching the substrate and filling the deep groove isolation with LPTEOS;
Step F, depositing a layer of SiO 2 as a medium of the contact hole;
Step G: dry etching the contact hole and depositing metal.
besides, a PWell (P well) layer or an NWell (N well) layer can be arranged between the P type epitaxial layer (Pepi) and the SN layer and the SP layer, and a step of general injection for the PWell or the NWell of the P type epitaxial layer is added after the step A and before the step B without a photoetching plate. The PWell general implantation element is B, the dosage is between 1E12 and 1E13, the annealing temperature is between 1050 and 1150, the NWell general implantation element is P, the dosage is between 1E13 and 1E14, and the annealing temperature is between 1050 and 1150.
preferably, in step A, the resistivity of the N + substrate is 0.001-0.006ohm, the resistivity of the P-type epitaxial is 0.015-0.15ohm, and the thickness of the P-type epitaxial is 5-10 um.
Preferably, in the step B, after photoetching definition is carried out on the P-type epitaxial layer, an SN layer is formed through ion implantation, the implantation elements are P and As, the implantation dose is between 1E15 and 8E15, the energy is between 50kev and 80kev, and the area of the SN layer accounts for 70-90% of the whole chip area.
preferably, in the step C, after the photolithographic definition is carried out on the P-type epitaxial layer, an SP layer is formed by ion implantation, the implantation element is B, the implantation dosage is between 1E15 and 8E15, the energy is between 50kev and 80kev, and the area of the SP layer accounts for 10 to 30 percent of the whole chip area.
Preferably, in step D, the SP and SN layers are subjected to RTP rapid annealing at 1000-.
Preferably, step E: the deep isolation groove is etched on the P type epitaxial layer by a dry method and extends to the substrate, the depth of the deep isolation groove is 15-20 um, the CD of the deep groove is 1.2um, and the deep groove is filled with LPTEOS after being etched to achieve the isolation effect.
Preferably, step F, a layer of SiO 2 is deposited as the contact hole dielectric to a thickness of 0.6um to 0.8 um.
Preferably, step G: etching a contact hole by photoetching definition and a dry method and depositing metal, wherein the metal is AlSiCu of 3-4.5 um; the metal interconnects the SN/SP on the front side.
The invention has the beneficial effects that: the invention provides a novel TVS device, which not only reduces breakdown voltage while providing low leakage current, but also greatly improves peak current IPP in a breakdown direction, and simultaneously reduces clamping voltage in a positive conduction direction and a negative breakdown direction, so that the device is completely in a safety area, and the device has the advantages of high power, low cost and the like.
Drawings
FIG. 1 is a TVS diagram of the unidirectional structure of SP/Pepi/Nsub.
FIG. 2 is a TVS diagram of the bidirectional structure of SN/Pepi/Nsub.
Fig. 3 is a schematic structural diagram of a unidirectional snapback TVS device in embodiment 1 of the present invention.
Fig. 4 is a schematic circuit diagram of a unidirectional snapback TVS device in embodiment 1 of the present invention.
Fig. 5 is a schematic structural diagram of a unidirectional snapback TVS device in embodiment 2 of the present invention.
fig. 6 is a schematic structural diagram of a unidirectional snapback TVS device in embodiment 3 of the present invention.
Detailed Description
example 1:
in the step A, an N + substrate/a P type epitaxial wafer is adopted, wherein the resistivity of the N + substrate is 0.001-0.006ohm, the resistivity of the P type epitaxy is 0.015-0.15ohm, and the thickness of the P type epitaxy is 5-10 um;
In the step B, after photoetching definition is carried out on the P-type epitaxial layer, an SN layer is formed through ion implantation, the implantation elements are P or As, the implantation dosage is between 1E15 and 8E15, the energy is between 50kev and 80kev, and the area of the SN layer accounts for 70 to 90 percent of the area of the whole chip;
Step C, after photoetching definition is carried out on the P-type epitaxial layer, an SP layer is formed through ion implantation, the implantation element is B, the implantation dosage is between 1E15 and 8E15, the energy is between 50kev and 80kev, and the area of the SP layer accounts for 10 to 30 percent of the area of the whole chip;
In the step D, performing RTP rapid annealing on the SP layer and the SN layer, controlling the temperature to be 1000-1100 ℃ and the time to be 20-30S, and activating the injected elements;
step E: dry etching the deep isolation groove on the P-type epitaxy until the deep isolation groove extends to the substrate, wherein the depth of the deep isolation groove is 15-20 um, the CD of the deep groove is 1.2um, and the deep groove is filled with LPTEOS after being etched to achieve an isolation effect;
Step F, depositing a layer of SiO 2 as a medium of the contact hole, wherein the thickness is 0.6um-0.8 um;
Step G: etching a contact hole by photoetching definition and a dry method and depositing metal, wherein the metal is AlSiCu of 3-4.5 um;
Step H: the metal interconnects the SP and SN on the front side.
Example 2:
The method is similar to example 1 except that a layer of PWell implant is added after step A, the implant element is B, the dose is 1E12-1E13, the annealing temperature is 1050-.
Example 3:
a layer of NWell is added after step A, the implantation element is P, the dosage is between 1E13-1E14, the annealing temperature is between 1050-.
As shown in fig. 3, the PN junction unidirectional structure of fig. 1 and the NPN structure of fig. 2 are innovatively combined, and an NPN structure is formed from the product back IO2 to the product front IO1, and the structure has a unidirectional snapback characteristic, so that when a surge impacts, the clamping voltage in the direction can be effectively reduced without increasing the area, and the structure can obtain a larger surge capacity than a unidirectional TVS. The positive PN junction VF positive direction is arranged from the front side to the back side of the product, and compared with an NPN structure, the positive PN junction has stronger discharge capacity when negative surge impacts, so that the TVS can play a role of bidirectional protection. In addition, the 2 structures are isolated through the deep groove isolation trench, the VBR can be made lower, and the requirements of customer application can be met; because the shunt of the parallel structure is related to the resistance, the distribution current can be adjusted by adjusting the layout area of the two channels through the layout design during the design, so that the NPN negative resistance channel obtains larger current and low residual voltage is realized;
in embodiment 1, without the general remark of PWell, it is easier to put through compared to embodiment 2, VBR can achieve lower voltage;
compared with the embodiment 1, the embodiment 2 has the advantages that the common note of one layer of PWell is added, the Pepi concentration is increased, namely the NPN triode base region concentration is increased, the NPN punch-through is more difficult, and the punch-through voltage in the VBR direction is increased;
in example 3, adding a layer of NWell to example 1, NWell will be much deeper than the junction depth of N + compared to example 1, which makes the effective Pepi thickness reduced, thereby making NPN punch-through easier and reducing punch-through voltage in VBR direction to some extent.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner. Although the invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make many possible variations and modifications to the disclosed embodiments, or equivalent modifications, without departing from the spirit and scope of the invention, using the methods and techniques disclosed above. Therefore, any modification, equivalent replacement, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.
Claims (13)
1. The TVS device is characterized by comprising an N-type substrate, wherein a P-type epitaxial layer is arranged above the N-type substrate, an SN layer and an SP layer are arranged on the P-type epitaxial layer, and the SN layer and the SP layer are isolated through a deep groove.
2. The TVS device of claim 1, wherein a PWell layer is disposed between said P-epi layer and said SN and SP layers.
3. the TVS device of claim 1, wherein an NWell layer is disposed between said P-epi layer and said SN and SP layers.
4. The TVS device of claim 1, wherein the SN layer has an area of 70% to 90% of the total chip area, and the SP layer has an area of 10% to 30% of the total chip area.
5. The method of manufacturing a low residual voltage and large surge unidirectional snapback TVS device of claim 1, comprising:
Step A: selecting an N + substrate/P type epitaxial wafer;
and B: forming an SN layer by ion implantation after photoetching definition is carried out on the P type epitaxial layer;
And C: after photoetching definition is carried out on the P type epitaxial layer, an SP layer is formed through ion implantation;
Step D: carrying out RTP annealing on the SN layer and the SP layer at the same time, and activating the injection elements;
step E: dry etching the deep isolation groove on the P type epitaxial layer till reaching the substrate and filling the deep groove isolation with LPTEOS;
Step F, depositing a layer of SiO 2 as a medium of the contact hole;
Step G: dry etching the contact hole and depositing metal.
6. The method for preparing a low residual voltage large surge unidirectional snapback TVS device as claimed in claim 5, wherein: after the step A, a step of adding PWELL or NWELL common notes to the P type epitaxial layer before the step B without a photoetching plate.
7. The method for preparing a low residual voltage large surge unidirectional snapback TVS device as claimed in claim 5 or 6, wherein: in the step A, an N + substrate/a P type epitaxial wafer is adopted, wherein the resistivity of the N + substrate is 0.001-0.006ohm, the resistivity of the P type epitaxial wafer is 0.015-0.15ohm, and the thickness of the P type epitaxial wafer is 5-10 um.
8. the method for preparing a low residual voltage large surge unidirectional snapback TVS device as claimed in claim 5 or 6, wherein: in the step B, after photoetching definition is carried out on the P-type epitaxial layer, an SN layer is formed through ion implantation, implantation elements are P and As, the implantation dosage is between 1E15 and 8E15, the energy is between 50kev and 80kev, and the area of the SN layer accounts for 70 to 90 percent of the area of the whole chip.
9. the method for preparing a low residual voltage large surge unidirectional snapback TVS device as claimed in claim 5 or 6, wherein: in the step C, after photoetching definition is carried out on the P-type epitaxial layer, an SP layer is formed through ion implantation, the implantation element is B, the implantation dosage is between 1E15 and 8E15, the energy is between 50kev and 80kev, and the area of the SP layer accounts for 10% -30% of the area of the whole chip.
10. The method for preparing a low residual voltage large surge unidirectional snapback TVS device as claimed in claim 5 or 6, wherein: and D, performing RTP rapid annealing on the SP layer and the SN layer at the temperature of 1000-1100 ℃ for 20-30S to activate the injected elements.
11. the method for preparing a low residual voltage large surge unidirectional snapback TVS device as claimed in claim 5 or 6, wherein: step E: the deep isolation groove is etched on the P type epitaxial layer by a dry method and extends to the substrate, the depth of the deep isolation groove is 15-20 um, the CD of the deep groove is 1.2um, and the deep groove is filled with LPTEOS after being etched to achieve the isolation effect.
12. The method for preparing a low residual voltage large surge unidirectional snapback TVS device as claimed in claim 5 or 6, wherein step F, a layer of SiO 2 is deposited as a medium of a contact hole with a thickness of 0.6um to 0.8 um.
13. The method for preparing a low residual voltage large surge unidirectional snapback TVS device as claimed in claim 5 or 6, wherein: step G: etching a contact hole by photoetching definition and a dry method and depositing metal, wherein the metal is AlSiCu of 3-4.5 um; the metal interconnects the SN/SP on the front side.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111180336A (en) * | 2019-12-30 | 2020-05-19 | 上海芯导电子科技有限公司 | Low residual voltage surge protection device and manufacturing method thereof |
| CN111180337A (en) * | 2019-12-30 | 2020-05-19 | 上海芯导电子科技有限公司 | One-way surge protection device and manufacturing method |
| CN111668210A (en) * | 2020-06-18 | 2020-09-15 | 上海韦尔半导体股份有限公司 | Unidirectional high-voltage transient voltage suppression protection device and preparation method thereof |
| CN114093952A (en) * | 2021-11-19 | 2022-02-25 | 无锡中微晶园电子有限公司 | High-symmetry bidirectional TVS diode and preparation method thereof |
| CN115799076A (en) * | 2023-02-03 | 2023-03-14 | 之江实验室 | Manufacturing method of wafer system micro-channel capable of measuring flow speed, pressure and temperature |
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