CN113437063A - MOS triggers SCR device - Google Patents
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- CN113437063A CN113437063A CN202110722637.1A CN202110722637A CN113437063A CN 113437063 A CN113437063 A CN 113437063A CN 202110722637 A CN202110722637 A CN 202110722637A CN 113437063 A CN113437063 A CN 113437063A
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- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
Abstract
The invention discloses an MOS-triggered SCR device. The MOS triggering SCR device comprises a P-type substrate, a low-voltage N well and a low-voltage P well which are positioned at the upper end of the P-type substrate and sequentially arranged along the length direction of the substrate, a first SN region, a first SP region, a second SN region, a second SP region, a third region positioned at the junction of the low-voltage N well and the low-voltage P well, and an adjustable component positioned between the second SN region and the third region or positioned between the first SP region and the third region. By arranging the adjustable component between the second SN region and the third region or between the first SP region and the third region and adjusting the adjustable component, the threshold voltage of a parasitic MOS tube in the SCR device can be controlled, when the threshold voltage changes, the trigger voltage of the SCR device also changes, and therefore stepless adjustment of the trigger voltage of the SCR device is achieved by adjusting the threshold voltage of the parasitic MOS tube.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an MOS (metal oxide semiconductor) triggering SCR (silicon controlled rectifier) device.
Background
At present, electrostatic discharge (ESD) is ubiquitous in the processes of manufacturing, packaging, testing and using chips, accumulated static charges are released in a nanosecond-microsecond time by a current of several amperes or dozens of amperes, instantaneous power is up to dozens or hundreds of watts, and the destruction strength of chips in a circuit system is very high. Statistically, more than 35% of chip failures are due to ESD damage. Therefore, in the design of chips or systems, the design of the esd protection module is directly related to the functional stability of the circuit system and the system reliability, and is very important for electronic products.
As the density of integrated circuits increases, the voltage endurance and operating voltage thereof decrease. Although the ultra-low operating voltages of 0.9V and 1.2V, etc. do not cause latch-up (latch-up) common in ESD devices, the too low voltage thereof poses design challenges for triggering the ESD devices, and the original low trigger voltage silicon controlled rectifier (scr) (lvtscr) has not been able to achieve a sufficiently low voltage. Diode-triggered Silicon Controlled Rectifier (SCR) (dtscr) is an effective technology for solving the ultra-low voltage triggering, however, since the forward conduction Voltage (VF) of the diode is only about 0.7V, the voltage port of 2V requires at least 4 diodes to be stacked, and since 3 diodes are stacked to about 2.1V, which is risky, at least 4 diodes are required, which not only wastes a large area, but also makes it difficult to make the SCR triggering voltage an appropriate value due to the minimum interval of 0.7V.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
The invention mainly aims to provide an MOS (metal oxide semiconductor) triggering SCR (silicon controlled rectifier) device, and aims to solve the technical problem that the triggering voltage of the SCR device cannot be adjusted in a stepless manner in the prior art.
To achieve the above object, the present invention provides a MOS-triggered SCR device, which includes: the low-voltage N-well and the low-voltage P-well are positioned at the upper end of the P-type substrate and sequentially arranged along the length direction of the substrate, and the first SN region, the first SP region, the second SN region and the second SP region are positioned at the upper ends of the low-voltage N-well and the low-voltage P-well and sequentially arranged along the length direction of the substrate, wherein the first SN region and the first SP region are positioned at the upper end of the low-voltage N-well, the second SN region and the second SP region are positioned at the upper end of the low-voltage P-well, the third region at the junction of the low-voltage N-well and the low-voltage P-well, and the adjustable component is positioned between the second SN region and the third region or between the first SP region and the third region.
Optionally, when the third region is an SN region, the MOS-triggered SCR device is a PMOS-triggered SCR device, and when the third region is an SP region, the MOS-triggered SCR device is an NMOS-triggered SCR device.
Optionally, the tunable element comprises a tunable trench implant region with a tunable concentration.
Optionally, the adjustable component further comprises: the gate structure comprises a first gate oxide layer positioned at the upper end of the channel adjusting injection region and a polysilicon gate positioned at the upper end of the first gate oxide layer.
Optionally, when the MOS-triggered SCR device is a PMOS-triggered SCR device, the first SN region, the first SP region, and the polysilicon gate are connected to serve as an anode of the MOS-triggered SCR device, and the second SN region and the second SP region are connected to serve as a cathode of the MOS-triggered SCR device.
Optionally, when the MOS-triggered SCR device is an NMOS-triggered SCR device, the first SN region is connected to the first SP region to serve as an anode of the MOS-triggered SCR device, and the second SN region, the second SP region, and the polysilicon gate are connected to serve as a cathode of the MOS-triggered SCR device.
Optionally, the adjustable component comprises a second gate oxide layer with an adjustable thickness.
Optionally, the adjustable component further comprises: and the polysilicon gate is positioned at the upper end of the second gate oxide layer.
Optionally, when the MOS-triggered SCR device is a PMOS-triggered SCR device, the first SN region, the first SP region, and the polysilicon gate are connected to serve as an anode of the MOS-triggered SCR device, and the second SN region and the second SP region are connected to serve as a cathode of the MOS-triggered SCR device.
Optionally, when the MOS-triggered SCR device is an NMOS-triggered SCR device, the first SN region is connected to the first SP region to serve as an anode of the MOS-triggered SCR device, and the second SN region, the second SP region, and the polysilicon gate are connected to serve as a cathode of the MOS-triggered SCR device.
In the present invention, a MOS-triggered SCR device includes: the low-voltage N-well and the low-voltage P-well are positioned at the upper end of the P-type substrate and sequentially arranged along the length direction of the substrate, and the first SN region, the first SP region, the second SN region and the second SP region are positioned at the upper ends of the low-voltage N-well and the low-voltage P-well and sequentially arranged along the length direction of the substrate, wherein the first SN region and the first SP region are positioned at the upper end of the low-voltage N-well, the second SN region and the second SP region are positioned at the upper end of the low-voltage P-well, the third region at the junction of the low-voltage N-well and the low-voltage P-well, and the adjustable component is positioned between the second SN region and the third region or between the first SP region and the third region. According to the invention, the adjustable component is arranged between the second SN region and the third region or between the first SP region and the third region, and the threshold voltage of the parasitic MOS tube in the SCR device can be controlled by adjusting the adjustable component, when the threshold voltage changes, the trigger voltage of the SCR device also changes, so that the trigger voltage of the SCR device can be steplessly adjusted by adjusting the threshold voltage of the parasitic MOS tube.
Drawings
Reference will now be made in detail to the embodiments or drawings that are required for use in the description of the prior art, the drawings being illustrative of some embodiments of the invention and other drawings may be derived from the structures shown in these drawings by those skilled in the art without the benefit of any inventive faculty.
Fig. 1 is a schematic structural diagram of a first embodiment of a MOS-triggered SCR device according to the present invention;
fig. 2 is another schematic structural diagram of a first embodiment of a MOS-triggered SCR device according to the present invention;
fig. 3 is a schematic structural diagram of a second embodiment of a MOS-triggered SCR device according to the present invention;
fig. 4 is another schematic structural diagram of a second embodiment of a MOS-triggered SCR device according to the present invention;
fig. 5 is a schematic structural diagram of a third embodiment of a MOS-triggered SCR device according to the present invention;
fig. 6 is another schematic structural diagram of a third embodiment of a MOS-triggered SCR device according to the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 22 | P- |
052 | |
| 11 | Low voltage N- |
06 | |
| 12 | Low- |
30 | First gate oxide layer |
| 01 | A first SN region | 31 | P-type channel-adjusting |
| 02 | |
32 | Polysilicon |
| 03 | Second SN region | 33 | N-type channel adjusting |
| 04 | Second |
40 | Second |
| 05 | |
41 | Anode |
| 051 | |
42 | Cathode electrode |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a MOS-triggered SCR device according to a first embodiment of the present invention.
As shown in fig. 1, in the present embodiment, the MOS-triggered SCR device includes: the low-voltage N-well structure comprises a P-type substrate 22, a low-voltage N-well 11 and a low-voltage P-well 12 which are positioned at the upper end of the P-type substrate 22 and sequentially arranged along the length direction of the substrate, and a first SN region 01, a first SP region 02, a second SN region 03 and a second SP region 04 which are positioned at the upper ends of the low-voltage N-well 11 and the low-voltage P-well 12 and sequentially arranged along the length direction of the substrate, wherein the first SN region 01 and the first SP region 02 are positioned at the upper end of the low-voltage N-well 11, the second SN region 03 and the second SP region 04 are positioned at the upper end of the low-voltage P-well 12, a third region 05 positioned at the junction of the low-voltage N-well 11 and the low-voltage P-well 12.
It will be appreciated that the MOS-triggered SCR device in fig. 1 is a PMOS-triggered SCR device, the first SN 01, the first SP 02 and the tunable element 06 are connected as an anode 41 of the MOS-triggered SCR device, and the second SN 03 is connected to the second SP 04 as a cathode 42 of the MOS-triggered SCR device.
In a specific implementation, the adjustable component 06 is located on the surface of the low-voltage P-well 12, the voltage of the anode 41 can be transmitted to the cathode 42 through the first SN region 01, the first SP region 02, the third region 05, the adjustable component 06, and the second SN region 03, so that the SCR device is turned on, and the threshold voltage of the parasitic MPS tube can be changed through the adjustable component 06.
It should be understood that the device in fig. 1 is a PMOS triggered SCR device, and when the ESD voltage of the anode 41 is higher than the preset threshold voltage of the PMOS transistor, the P channel of the PMOS transistor is turned on, so as to provide a base current for a parasitic NPN structure in the SCR device, thereby triggering the positive feedback action of NPN and PNP to turn on the SCR device. If the circuit voltage is very low or slightly high, the threshold voltage of the parasitic PMOS transistor can be reduced or increased by adjusting the adjustable component 06, so that the parasitic NPN in the SCR device can obtain the base current earlier or later, thereby turning on the SCR device earlier or later.
Referring to fig. 2, fig. 2 is another schematic structural diagram of a first embodiment of a MOS-triggered SCR device according to the present invention.
As shown in fig. 2, in the present embodiment, the MOS-triggered SCR device includes: the low-voltage N-well structure comprises a P-type substrate 22, a low-voltage N-well 11 and a low-voltage P-well 12 which are located at the upper end of the P-type substrate 22 and sequentially arranged along the length direction of the substrate, and a first SN region 01, a first SP region 02, a second SN region 03 and a second SP region 04 which are located at the upper ends of the low-voltage N-well 11 and the low-voltage P-well 12 and sequentially arranged along the length direction of the substrate, wherein the first SN region 01 and the first SP region 02 are located at the upper end of the low-voltage N-well 11, the second SN region 03 and the second SP region 04 are located at the upper end of the low-voltage P-well 12, a third region 05 located at the junction of the low-voltage N-well 11 and the low-voltage P-well 12, and an adjustable component 06 located between the first SP region 02 and the third region 05.
It is understood that the MOS-triggered SCR device in fig. 2 is an NMOS-triggered SCR device, the first SN region 01 is connected to the first SP region 02 as the anode 41 of the MOS-triggered SCR device, and the second SN region 03, the second SP region 04, and the tunable element 06 are connected as the cathode 42 of the MOS-triggered SCR device.
It should be noted that Silicon Controlled Rectifiers (SCRs) are of the unidirectional, bidirectional, turn-off and light-Controlled type. The device has the advantages of small volume, light weight, high efficiency, long service life, convenient control and the like, and is widely applied to various automatic control and high-power electric energy conversion occasions such as controllable rectification, voltage regulation, inversion, contactless switches and the like.
It is understood that the third region 05 can be an SN region or an SP region, where the MOS-triggered SCR device is a PMOS-triggered SCR device when the third region 05 is the SN region, and the MOS-triggered SCR device is an NMOS-triggered SCR device when the third region 05 is the SP region. The setting can be self-set according to the actual situation, and this embodiment is not particularly limited to this.
It will be appreciated that the position of the adjustable component 06 is determined by the type of the third zone 05, and that in the case of the third zone 05 being the SN zone, the adjustable component 06 is located between the second SN zone 03 and the third zone 05, i.e. as shown in fig. 1; where the third zone 05 is an SP zone, the tunable member 06 is located between the first SP zone 02 and the third zone 05, as shown in fig. 2.
It should be understood that the device in fig. 2 is an NMOS triggered SCR device, and when the ESD voltage of the anode 41 is higher than the threshold voltage of the preset NMOS, the N channel of the NMOS is turned on, so as to provide a base current for the parasitic PNP structure in the SCR device, thereby triggering the positive feedback of the PNP and NPN to turn on the SCR device. If the circuit voltage is very low or slightly high, the threshold voltage of the parasitic NMOS transistor can be reduced or increased by adjusting the adjustable component 06, so that the parasitic PNP in the SCR device can obtain the base current earlier or later, and thus the SCR device can be turned on earlier or later.
In this embodiment, the MOS-triggered SCR device includes: the low-voltage N-well and the low-voltage P-well are positioned at the upper end of the P-type substrate and sequentially arranged along the length direction of the substrate, and the first SN region, the first SP region, the second SN region and the second SP region are positioned at the upper ends of the low-voltage N-well and the low-voltage P-well and sequentially arranged along the length direction of the substrate, wherein the first SN region and the first SP region are positioned at the upper end of the low-voltage N-well, the second SN region and the second SP region are positioned at the upper end of the low-voltage P-well, the third region at the junction of the low-voltage N-well and the low-voltage P-well, and the adjustable component is positioned between the second SN region and the third region or between the first SP region and the third region. In this embodiment, the adjustable component is disposed between the second SN region and the third region or between the first SP region and the third region, and the adjustable component is adjusted to control the threshold voltage of the parasitic MOS transistor in the SCR device, and when the threshold voltage changes, the trigger voltage of the SCR device also changes, so that the trigger voltage of the SCR device is steplessly adjusted by adjusting the threshold voltage of the parasitic MOS transistor.
Further, referring to fig. 3, fig. 3 is a schematic structural diagram of a second embodiment of the MOS-triggered SCR device according to the present invention.
As shown in fig. 3, in the present embodiment, the tunable component 06 includes a tunable trench implantation region with tunable concentration.
In a specific implementation, the concentration of the trench adjustment implantation region can be adjusted by means of ion implantation.
It should be understood that the type of the channel-adjusting implantation region is also determined according to the type of the third region 05, and when the third region 05 is an SN region, the channel-adjusting implantation region is a P-type channel-adjusting implantation region 31; when the third region 05 is an SP region, the channel-modulated implantation region is an N-type channel-modulated implantation region 33.
Further, the adjustable component 06 further includes: a first gate oxide layer 30 on the upper end of the channel adjusting injection region and a polysilicon gate 32 on the upper end of the first gate oxide layer 30.
The MOS-triggered SCR device in fig. 3 is a PMOS-triggered SCR device, wherein the third region 05 is a third SN region 051, the first SN region 01, the first SP region 02 and the polysilicon gate 32 are connected to serve as an anode 41 of the MOS-triggered SCR device, and the second SN region 03 and the second SP region 04 are connected to serve as a cathode 42 of the MOS-triggered SCR device.
It can be understood that the MOS-triggered SCR device in fig. 3 is a PMOS-triggered SCR device, and by adjusting the concentration of the P-type channel-adjusting injection region 31, when the concentration of the P-type channel-adjusting injection region 31 is higher than that of the low-voltage P-well 12, the threshold voltage of the parasitic MOS transistor increases; when the concentration of the P-type channel-adjusting implantation region 31 is lower than that of the low-voltage P-well 12, the threshold voltage of the parasitic MOS transistor is reduced.
In specific implementation, when the ESD voltage of the anode 41 is higher than the threshold voltage of the predetermined PMOS transistor, the P channel of the PMOS transistor is turned on, so as to provide a base current for a parasitic NPN structure in the SCR device, thereby triggering a positive feedback effect of the NPN and the PNP to turn on the SCR device. If the circuit voltage is extremely low, the concentration of the P-type channel-adjusting injection region 31 can be reduced to reduce the threshold voltage of the parasitic PMOS tube, so that the parasitic NPN in the SCR device can obtain the base current earlier, and the SCR device can be started earlier. If the circuit voltage is slightly higher, the concentration of the P-type channel-adjusting implantation region 31 can be increased to increase the threshold voltage of the parasitic PMOS transistor, so that the parasitic NPN in the SCR device can obtain the base current later, and the SCR device can be turned on later.
Further, referring to fig. 4, fig. 4 is another schematic structural diagram of a second embodiment of the MOS-triggered SCR device according to the present invention.
As shown in fig. 4, the MOS-triggered SCR device in fig. 4 is an NMOS-triggered SCR device, wherein the third region 05 is a third SP region 052, the first SN region 01 is connected to the first SP region 02 to serve as an anode 41 of the MOS-triggered SCR device, and the second SN region 03, the second SP region 04, and the polysilicon gate 32 are connected to serve as a cathode 42 of the MOS-triggered SCR device.
It can be understood that the MOS-triggered SCR device in fig. 4 is an NMOS-triggered SCR device, and by adjusting the concentration of the N-type channel-adjusting injection region 33, when the concentration of the N-type channel-adjusting injection region 33 is higher than that of the low-voltage N-well 11, the threshold voltage of the parasitic MOS transistor increases; when the concentration of the N-type channel-adjusting implantation region 33 is lower than that of the low-voltage N-well 11, the threshold voltage of the parasitic MOS transistor is reduced.
In specific implementation, when the ESD voltage of the anode 41 is higher than the threshold voltage of the predetermined NMOS, the N channel of the NMOS is turned on, so as to provide a base current for a parasitic PNP structure in the SCR device, thereby triggering a positive feedback action of the PNP and NPN to turn on the SCR device. If the circuit voltage is very low, the concentration of the N-type channel-adjusting injection region 33 can be reduced to reduce the threshold voltage of the parasitic NMOS tube, so that the parasitic PNP in the SCR device can obtain the base current earlier, and the SCR device can be started earlier. If the circuit voltage is slightly higher, the parasitic PNP in the SCR device can get the base current later by increasing the concentration of the N-type channel-adjusting implantation region 33 to increase the threshold voltage of the parasitic NMOS transistor, thereby turning on the SCR device later.
The adjustable component in the embodiment comprises a channel adjusting injection region with adjustable concentration, the threshold voltage of a parasitic MOS tube in the SCR device can be changed and controlled by adjusting the concentration of the channel adjusting injection region, when the threshold voltage is changed, the lowest voltage of base current obtained by parasitic NPN or PNP in the SCR device is also changed, so that the trigger voltage of the SCR device is also changed, and the stepless adjustment of the trigger voltage of the SCR device is realized by adjusting the threshold voltage of the parasitic MOS tube.
Further, referring to fig. 5, fig. 5 is a schematic structural diagram of a third embodiment of a MOS-triggered SCR device according to the present invention.
As shown in fig. 5, in the present embodiment the adjustable component 06 comprises a second gate oxide layer 40 with an adjustable thickness.
Understandably, when the thickness of the gate oxide layer changes, the threshold voltage of the parasitic MOS transistor also changes.
Further, the adjustable component 06 further includes: and a polysilicon gate 32 on the upper end of the second gate oxide layer 40.
The MOS-triggered SCR device in fig. 5 is a PMOS-triggered SCR device, wherein the third region 05 is a third SN region 051, the first SN region 01, the first SP region 02 and the polysilicon gate 32 are connected to serve as an anode 41 of the MOS-triggered SCR device, and the second SN region 03 and the second SP region 04 are connected to serve as a cathode 42 of the MOS-triggered SCR device.
In specific implementation, when the ESD voltage of the anode 41 is higher than the threshold voltage of the predetermined PMOS transistor, the P channel of the PMOS transistor is turned on, so as to provide a base current for a parasitic NPN structure in the SCR device, thereby triggering a positive feedback effect of the NPN and the PNP to turn on the SCR device. If the circuit voltage is extremely low, the thickness of the second gate oxide layer 40 can be reduced to reduce the threshold voltage of the parasitic PMOS tube, so that the parasitic NPN in the SCR device can obtain the base current earlier, and the SCR device can be started earlier. If the circuit voltage is slightly higher, the parasitic NPN in the SCR device can get the base current later by increasing the thickness of the second gate oxide layer 40 to increase the threshold voltage of the parasitic PMOS transistor, thereby turning on the SCR device later.
Further, referring to fig. 6, fig. 6 is another schematic structural diagram of a third embodiment of a MOS-triggered SCR device according to the present invention.
As shown in fig. 6, the MOS-triggered SCR device in fig. 6 is an NMOS-triggered SCR device, wherein the third region 05 is a third SP region 052, the first SN region 01 is connected to the first SP region 02 to serve as an anode 41 of the MOS-triggered SCR device, and the second SN region 03, the second SP region 04 and the polysilicon gate 32 are connected to serve as a cathode 42 of the MOS-triggered SCR device.
In specific implementation, when the ESD voltage of the anode 41 is higher than the threshold voltage of the predetermined NMOS, the N channel of the NMOS is turned on, so as to provide a base current for a parasitic PNP structure in the SCR device, thereby triggering a positive feedback action of the PNP and NPN to turn on the SCR device. If the circuit voltage is extremely low, the thickness of the second gate oxide layer 40 can be reduced to reduce the threshold voltage of the parasitic NMOS tube, so that the parasitic PNP in the SCR device can obtain the base current earlier, and the SCR device can be started earlier. If the circuit voltage is slightly higher, the parasitic PNP in the SCR device can get the base current later by increasing the thickness of the second gate oxide layer 40 to increase the threshold voltage of the parasitic NMOS transistor, thereby turning on the SCR device later.
The adjustable component in the embodiment comprises a second gate oxide layer with adjustable thickness, the threshold voltage of a parasitic MOS tube in the SCR device can be changed and controlled by adjusting the thickness of the second gate oxide layer, when the threshold voltage is changed, the lowest voltage of base current obtained by parasitic NPN or PNP in the SCR device is also changed, so that the trigger voltage of the SCR device is also changed, and the trigger voltage of the SCR device is steplessly adjusted by adjusting the threshold voltage of the parasitic MOS tube.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A MOS-triggered SCR device, the MOS-triggered SCR device comprising: the low-voltage N-well and the low-voltage P-well are positioned at the upper end of the P-type substrate and sequentially arranged along the length direction of the substrate, and the first SN region, the first SP region, the second SN region and the second SP region are positioned at the upper ends of the low-voltage N-well and the low-voltage P-well and sequentially arranged along the length direction of the substrate, wherein the first SN region and the first SP region are positioned at the upper end of the low-voltage N-well, the second SN region and the second SP region are positioned at the upper end of the low-voltage P-well, the third region at the junction of the low-voltage N-well and the low-voltage P-well, and the adjustable component is positioned between the second SN region and the third region or between the first SP region and the third region.
2. The MOS-triggered SCR device of claim 1, wherein the MOS-triggered SCR device is a PMOS triggered SCR device when the third region is a SN region and an NMOS triggered SCR device when the third region is an SP region.
3. The MOS-triggered SCR device of claim 2, wherein the tunable component comprises a tunable channel implant region of tunable concentration.
4. The MOS-triggered SCR device of claim 3, wherein the tunable component further comprises: the gate structure comprises a first gate oxide layer positioned at the upper end of the channel adjusting injection region and a polysilicon gate positioned at the upper end of the first gate oxide layer.
5. The MOS-triggered SCR device of claim 4, wherein the first SN region, the first SP region, and the polysilicon gate are connected as an anode of the MOS-triggered SCR device and the second SN region and the second SP region are connected as a cathode of the MOS-triggered SCR device when the MOS-triggered SCR device is a PMOS-triggered SCR device.
6. The MOS-triggered SCR device of claim 4, wherein the first SN region is connected to the first SP region as an anode of the MOS-triggered SCR device, and the second SN region, the second SP region, and the polysilicon gate are connected as a cathode of the MOS-triggered SCR device, when the MOS-triggered SCR device is an NMOS-triggered SCR device.
7. The MOS-triggered SCR device of claim 2, wherein the adjustable component comprises a second gate oxide layer that is adjustable in thickness.
8. The MOS-triggered SCR device of claim 7, wherein the tunable component further comprises: and the polysilicon gate is positioned at the upper end of the second gate oxide layer.
9. The MOS-triggered SCR device of claim 8, wherein the first SN region, the first SP region, and the polysilicon gate are connected as an anode of the MOS-triggered SCR device and the second SN region and the second SP region are connected as a cathode of the MOS-triggered SCR device when the MOS-triggered SCR device is a PMOS-triggered SCR device.
10. The MOS-triggered SCR device of claim 8, wherein the first SN region is connected to the first SP region as an anode of the MOS-triggered SCR device, and the second SN region, the second SP region, and the polysilicon gate are connected as a cathode of the MOS-triggered SCR device, when the MOS-triggered SCR device is an NMOS-triggered SCR device.
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