CN103094271B - A kind of ESD protection circuit - Google Patents

A kind of ESD protection circuit Download PDF

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Publication number
CN103094271B
CN103094271B CN201110337536.9A CN201110337536A CN103094271B CN 103094271 B CN103094271 B CN 103094271B CN 201110337536 A CN201110337536 A CN 201110337536A CN 103094271 B CN103094271 B CN 103094271B
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China
Prior art keywords
source
trap
diffusion region
pick
area
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CN201110337536.9A
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Chinese (zh)
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CN103094271A (en
Inventor
甘正浩
张莉菲
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中芯国际集成电路制造(上海)有限公司
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Publication of CN103094271A publication Critical patent/CN103094271A/en
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Abstract

The invention provides a kind of ESD protection circuit, it is characterized in that, comprising: multiple nmos pass transistor, adjacent described nmos pass transistor common-source diffusion region or drain diffusion regions; P trap is formed below described drain diffusion regions; The middle body of described shared source diffusion region is formed with pick-up area; The grid of described nmos pass transistor and source ground; Described pick-up area ground connection.According to the present invention, when there is static discharge, each finger in GGNMOS can be made simultaneously to open electrostatic discharge (ESD) protection, improve the electrostatic discharge (ESD) protection level weighed with human-body model (HBM).

Description

A kind of ESD protection circuit

Technical field

The present invention relates to ESD protection circuit, the unified ESD protection circuit opened can be realized in particular to a kind of.

Background technology

When integrated circuit (IC) is started working, the high-energy from outside is applied to described IC, there will be static discharge (ESD) phenomenon occurred instantaneously in described IC.Described ESD can produce instantaneous high pressure in described IC inside, and it will cause puncturing of gate oxide, and described IC is broken down.

Esd protection circuit conventional in prior art is the NMOS (GateGroundedNMOS) of grounded-grid; as shown in Figure 1; in the nmos area of GGNMOS; source S and grid G ground connection; pick-up area (Pickup) also ground connection; the resistance formed between the NPN knot formed between often pair of source S and drain D and described pick-up area is respectively R1, R2, R3 and R4, and the NPN knot wherein formed between often pair of source S and drain D is called finger (finger).Because described NPN knot is different from the distance between described pick-up area, therefore described pass between resistance R1, R2, R3 and R4 is R1<R2<R3<R4, namely described distance is longer, and the resistance value of the described resistance of formation is larger.When there is static discharge, can be observed by low-light microscope, opening electrostatic discharge (ESD) protection at the middle body of described nmos area, and not open electrostatic discharge (ESD) protection in the part near described pick-up area, there is a small amount of electrostatic discharge leakage stream.The resistance formed just because of the part of described nmos area near described pick-up area is less than the resistance formed between the middle body of described nmos area and described pick-up area, just causes different described fingers can not open electrostatic discharge (ESD) protection simultaneously.

Therefore, needing the GGNMOS proposing a kind of improvement, when there is static discharge, each finger in GGNMOS can be made to open electrostatic discharge (ESD) protection simultaneously.

Summary of the invention

For the deficiencies in the prior art, the invention provides a kind of ESD protection circuit, it is characterized in that, comprising: multiple nmos pass transistor, adjacent described nmos pass transistor common-source diffusion region or drain diffusion regions; P trap is formed below described drain diffusion regions; The middle body of described source diffusion region is formed with pick-up area; The grid of described nmos pass transistor and source ground; Described pick-up area ground connection.

Further, described ESD protection circuit is GGNMOS.

The present invention also provides a kind of manufacture method of ESD protection circuit, comprises, and provides P type semiconductor substrate, in described P type semiconductor substrate, be formed with P trap; Described P type semiconductor substrate forms a thin oxide layer, covers described P trap; Described thin oxide layer is formed the grid structure being positioned at described P trap both sides; Etch described thin oxide layer, expose described P trap, and implement source/drain region injection, to form source diffusion region and drain diffusion regions; Described P type semiconductor substrate forms a sacrifice layer, covers described grid structure; Etch described sacrifice layer, to expose the middle body of described source diffusion region; Implement ion implantation, the middle body in described source diffusion region forms pick-up area; Remove described sacrifice layer.

Further, described source/drain region is infused in described P type semiconductor substrate and forms source diffusion region, and forms drain diffusion regions in described P trap.

Further, the material of described sacrifice layer is silica.

Further, described pick-up area is P +diffusion region.

Further, described ESD protection circuit is GGNMOS.

According to the present invention, when there is static discharge, each finger in GGNMOS can be made simultaneously to open electrostatic discharge (ESD) protection, improve the electrostatic discharge (ESD) protection level weighed with human-body model (HBM).

Accompanying drawing explanation

Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.

In accompanying drawing:

Fig. 1 is the schematic cross sectional view of the NMOS (GGNMOS) of grounded-grid conventional in existing esd protection technology;

Fig. 2 is the schematic cross sectional view that can realize the unified ESD protection circuit opened that the present invention proposes.

Fig. 3 is the schematic cross sectional view that can realize each step of the manufacture method of the unified ESD protection circuit opened that the present invention proposes

Embodiment

In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.

In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the ESD protection circuit that can realize unified unlatching of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.

Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.

Below, the ESD protection circuit that can realize unified unlatching of the present invention's proposition is described with reference to Fig. 2.

As shown in Figure 2, be the GGNMOS of an improvement.In P type substrate (P-substrate), be formed with nmos area, the grid G ground connection of described nmos area, source S ground connection, at the N of each source S +the middle part of diffusion region forms P +diffusion region, to form pick-up area (Pickup), described pick-up area also ground connection.The P trap (P-Well) with low-resistivity is only formed at the N of drain D +the below of diffusion region.Described GGNMOS has multiple finger, and each finger all forms parasitic bipolar junction transistor.Because the distance between each finger with described pick-up area is identical, the resistance therefore formed between each finger with described pick-up area is identical, i.e. R5=R6.When there is static discharge, each finger in GGNMOS can be made to open electrostatic discharge (ESD) protection simultaneously.

Compare with R4 with resistance R1, R2, the R3 shown in Fig. 1, the resistance value of resistance R5 and R6 shown in Fig. 2 is suitable with the resistance value of described resistance R3 and R4, is greater than the resistance value of described resistance R1 and R2.This is because each finger shown in Fig. 1 is all arranged in P trap, and each finger shown in Fig. 2 is all arranged in P type substrate, and the resistance value of P type substrate is greater than the resistance value of P trap.Therefore, the magnitude of current flowing through each finger is very little, and GGNMOS can be made to work under low power consumpting state.

Below, the schematic cross sectional view that can realize each step of the manufacture method of the unified ESD protection circuit opened of the present invention's proposition is described with reference to Fig. 3.

First, as shown in Figure 3A, provide P type semiconductor substrate 300, in described P type semiconductor substrate 300, be formed with P trap 301.

Then, as shown in Figure 3 B, described P type semiconductor substrate 300 forms a thin oxide layer 302, cover described P trap 301.

Next, described thin oxide layer 302 is formed the grid structure being positioned at described P trap 301 both sides.Described grid structure comprises gate material layers and is positioned at the clearance wall structure of gate material layers both sides near gate material layers.Described clearance wall structure can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.

Then, as shown in Figure 3 C, with described grid structure for mask, etch described thin oxide layer 302, expose described P trap 301.

Then, as shown in Figure 3 D, with described grid structure for mask, implement source/drain region and inject 305, in described P type semiconductor substrate 300, form source diffusion region 303, in described P trap 301, form drain diffusion regions 304.

Then, as shown in FIGURE 3 E, described P type semiconductor substrate 300 is formed a sacrifice layer 306, covers described grid structure.The material of described sacrifice layer 306 is silica.

Then, as illustrated in Figure 3 F, described sacrifice layer 306 is etched, to expose the middle body of described source diffusion region 303.

Then, as shown in Figure 3 G, with described sacrifice layer 306 for mask, implement ion implantation 307, the middle body in described source diffusion region 303 forms P +diffusion region 308 is as pick-up area.

Then, as shown in figure 3h, described sacrifice layer 306 is removed.

So far, whole processing steps that the method according to an exemplary embodiment of the present invention that completes is implemented, to form the GGNMOS for electrostatic discharge (ESD) protection.Next, can be completed the making of whole semiconductor device by subsequent technique, described subsequent technique is identical with traditional process for fabricating semiconductor device.When there is static discharge, each finger in GGNMOS can be made simultaneously to open electrostatic discharge (ESD) protection, improve the electrostatic discharge (ESD) protection level weighed with human-body model (HBM).

The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.

Claims (7)

1. an ESD protection circuit, is characterized in that, comprising:
Multiple nmos pass transistor, adjacent described nmos pass transistor common-source diffusion region or drain diffusion regions;
Only below described drain diffusion regions, be formed with P trap;
The middle body of described source diffusion region is formed with pick-up area;
The grid of described nmos pass transistor and source ground;
Described pick-up area ground connection.
2. circuit according to claim 1, is characterized in that, described ESD protection circuit is GGNMOS.
3. a manufacture method for ESD protection circuit, comprises,
P type semiconductor substrate is provided, in described P type semiconductor substrate, is formed with P trap;
Described P type semiconductor substrate forms a thin oxide layer, covers described P trap;
Described thin oxide layer is formed the grid structure being positioned at described P trap both sides;
Etch described thin oxide layer, expose described P trap, and implement source/drain region injection, to form source diffusion region and drain diffusion regions;
Described P type semiconductor substrate forms a sacrifice layer, covers described grid structure;
Etch described sacrifice layer, to expose the middle body of described source diffusion region;
Implement ion implantation, the middle body in described source diffusion region forms pick-up area;
Remove described sacrifice layer.
4. method according to claim 3, is characterized in that, described source/drain region is infused in described P type semiconductor substrate and forms source diffusion region, and forms drain diffusion regions in described P trap.
5. method according to claim 3, is characterized in that, the material of described sacrifice layer is silica.
6. method according to claim 3, is characterized in that, described pick-up area is P +diffusion region.
7. method according to claim 3, is characterized in that, described ESD protection circuit is GGNMOS.
CN201110337536.9A 2011-11-01 2011-11-01 A kind of ESD protection circuit CN103094271B (en)

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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN104505399B (en) * 2014-12-18 2018-01-02 杭州捷茂微电子有限公司 One kind is used for grounded-grid NMOS structure ESD protective devices
CN107346786B (en) * 2016-05-05 2020-05-01 中芯国际集成电路制造(上海)有限公司 GGNMOS transistor, multi-finger GGNMOS device and circuit

Citations (3)

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Publication number Priority date Publication date Assignee Title
CN101740616A (en) * 2008-11-27 2010-06-16 上海华虹Nec电子有限公司 GGNMOS (grounded-gate negative-channel metal oxide semiconductor) device and making method thereof
CN101866922A (en) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 GGNMOS device used in ESD protective circuit
CN102034814A (en) * 2010-10-28 2011-04-27 浙江大学 Electrostatic discharge protective device

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Publication number Priority date Publication date Assignee Title
US6355508B1 (en) * 1998-09-02 2002-03-12 Micron Technology, Inc. Method for forming electrostatic discharge protection device having a graded junction
US20020076876A1 (en) * 2000-12-15 2002-06-20 Ming-Dou Ker Method for manufacturing semiconductor devices having ESD protection

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740616A (en) * 2008-11-27 2010-06-16 上海华虹Nec电子有限公司 GGNMOS (grounded-gate negative-channel metal oxide semiconductor) device and making method thereof
CN101866922A (en) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 GGNMOS device used in ESD protective circuit
CN102034814A (en) * 2010-10-28 2011-04-27 浙江大学 Electrostatic discharge protective device

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