CN108899314B - Electrostatic protection device - Google Patents
Electrostatic protection device Download PDFInfo
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- CN108899314B CN108899314B CN201810502138.XA CN201810502138A CN108899314B CN 108899314 B CN108899314 B CN 108899314B CN 201810502138 A CN201810502138 A CN 201810502138A CN 108899314 B CN108899314 B CN 108899314B
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- electrostatic protection
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- 238000002347 injection Methods 0.000 claims abstract description 73
- 239000007924 injection Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000007943 implant Substances 0.000 claims description 19
- 230000001012 protector Effects 0.000 claims 2
- 235000012773 waffles Nutrition 0.000 claims 1
- 238000012423 maintenance Methods 0.000 abstract description 9
- 238000002513 implantation Methods 0.000 description 11
- 230000002457 bidirectional effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000003321 amplification Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000010531 catalytic reduction reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an electrostatic protection device, which comprises a substrate, wherein a deep N well is arranged in the substrate, a first N well, a first P well and a second N well are sequentially arranged in the deep N well from left to right, a first N+ injection region, a first P+ injection region and a second N+ injection region are arranged in the first N well, the second N+ injection region is bridged between the first N well and the first P well, a third N+ injection region, a second P+ injection region and a fourth N+ injection region are arranged in the first P well, a fifth N+ injection region, a third P+ injection region and a sixth N+ injection region are arranged in the second N well, the fifth N+ injection region is bridged between the first P well and the second N well, the first P well and the second N well form a first NPN structure, and the second N+ injection region, the first P well and the third N+ injection region form a second NPN structure. The electrostatic protection device provided by the invention can improve the maintenance voltage, reduce the trigger voltage and enhance the electrostatic discharge capability.
Description
Technical Field
The invention relates to the technical field of electrostatic protection of integrated circuits, in particular to an electrostatic protection device.
Background
In each link of the integrated circuit, charge accumulation is possible. Under certain conditions, charge can be transferred, and the instantaneous high current can exceed the critical value of the device, so that the chip is burnt. Statistical data indicate that: electrostatic discharge (Electro Static Discharge, ESD) is the leading cause of integrated circuit failure, particularly in power integrated circuits. The problem of electrostatic discharge is therefore the most of the concerns of the designer.
In order to reduce the economic loss caused by electrostatic discharge in the integrated circuit, the most effective method is to design ESD protection devices with corresponding high efficiency ratios for each input and output port of the integrated circuit. At present, the conventional low-voltage process-oriented ESD protection measures are relatively mature, and common ESD protection device structures comprise a diode, a bipolar transistor, a grid grounding NMOS (N-channel metal oxide semiconductor) tube and an SCR (selective catalytic reduction) device. SCR devices are considered to be the most efficient devices for ESD protection due to their higher quality. In applications of ESD protection devices, it is necessary to ensure that the sustain voltage is higher than the operating voltage of the circuit to be protected while meeting robustness criteria.
However, in practical application, the existing SCR device is difficult to realize high maintenance voltage characteristic in a limited layout area, and the practical protection effect is affected.
Disclosure of Invention
In view of the above situation, the present invention aims to solve the problem that in the prior art, in practical application, the existing SCR device is difficult to realize high maintenance voltage characteristics in a limited layout area, and thus the practical protection effect is affected.
The invention provides an electrostatic protection device, which comprises a substrate, wherein a deep N well is arranged in the substrate, a first N well, a first P well and a second N well are sequentially arranged in the deep N well from left to right, a first N+ injection region, a first P+ injection region and a second N+ injection region are sequentially arranged in the first N well from left to right, the second N+ injection region is bridged between the first N well and the first P well, a third N+ injection region, a second P+ injection region and a fourth N+ injection region are sequentially arranged in the first P well, a fifth N+ injection region, a third P+ injection region and a sixth N+ injection region are sequentially arranged in the second N well, the fifth N+ injection region is bridged between the first P well and the second N well, the first P well and the second N well form a first NPN type transistor, and the second N+ injection region, the first P well and the third NPN type transistor form the second NPN type transistor.
According to the electrostatic protection device, the base electrode and the collector electrode of the second NPN type transistor are short-circuited with the base electrode of the first NPN type transistor, and the emitter electrodes of the first NPN type transistor and the second NPN type transistor are short-circuited, so that the clamping effect is generated on the SCR device of the main channel, and the maintenance voltage can be improved; meanwhile, the second N+ injection region and the fifth N+ injection region are bridged between the N well and the P well, so that a trigger point is transferred from the P well-N well junction to the P+ injection region-N well junction, and the trigger voltage can be reduced; in addition, as the P well regions are arranged below the first P+ injection region and the third P+ injection region, the base concentration of the first PNP and the second PNP can be reduced, the amplification factor can be improved, and the electrostatic discharge capacity can be enhanced.
In addition, the electrostatic protection device provided by the invention can also have the following additional technical characteristics:
the electrostatic protection device is characterized in that a second P well is arranged below the first P+ injection region, and a third P well is arranged below the third P+ injection region.
The electrostatic protection device comprises a first N+ injection region, a second P+ injection region, a third P+ injection region, a sixth N+ injection region, a third P+ injection region, a fourth P+ injection region, a fifth P+ injection region, a sixth N+ injection region and a third P+ injection region.
The electrostatic protection device comprises a first p+ injection region, a first N well and a first P well, wherein the first p+ injection region, the first N well and the first P well form a first PNP structure, and the third p+ injection region, the second N well and the first P well form a second PNP structure.
The electrostatic protection device, wherein the second N-well, the first P-well and the first N-well form a third NPN structure.
The electrostatic protection device, wherein the fifth n+ injection region, the first P-well and the fourth n+ injection region form a fourth NPN structure.
The substrate is a P-type substrate.
Drawings
FIG. 1 is a cross-sectional view of a prior art SCR device;
fig. 2 is a cross-sectional view of an electrostatic protection device according to a first embodiment of the present invention;
fig. 3 is an equivalent circuit diagram of an electrostatic protection device according to a first embodiment of the present invention;
fig. 4 is a layout of an electrostatic protection device according to a first embodiment of the present invention;
fig. 5 is a layout of an electrostatic protection device according to a second embodiment of the present invention.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," "upper," "lower," and the like are used herein for descriptive purposes only and not to indicate or imply that the apparatus or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, fig. 1 is a cross-sectional view of a conventional bi-directional SCR device, in which the conventional bi-directional SCR device is difficult to realize high maintenance voltage characteristics in a limited layout area, thereby affecting the actual protection effect. In order to solve the technical problem, the present invention provides an electrostatic protection device, specifically a compact high-maintenance voltage bidirectional SCR device, referring to fig. 2 to 4, for the compact high-maintenance voltage bidirectional SCR device according to the first embodiment of the present invention, the electrostatic protection device includes a substrate and a deep N-well 200 disposed in the substrate, wherein the substrate is a P-type substrate 100.
A first N-well 300, a first P-well 301, and a second N-well 302 are sequentially disposed in the deep N-well 200 from left to right. A first n+ implant region 400, a first p+ implant region 401, and a second n+ implant region 402 are sequentially disposed within the first N well 300 from left to right. It should be noted that the second n+ implantation region 402 is connected across the first N well 300 and the first P well 301.
A second P well 303 is disposed below the first p+ implantation region 401, and a third n+ implantation region 403, a second p+ implantation region 404, and a fourth n+ implantation region 405 are sequentially disposed in the first P well 301. Wherein the third n+ implant region 403, the second p+ implant region 404, and the fourth n+ implant region 405 are connected to each other.
A fifth n+ implant region 406, a third p+ implant region 407, and a sixth n+ implant region 408 are sequentially disposed within the second N well 302. The fifth n+ implant region 406 is connected across the first P-well 301 and the second N-well 302.
A third P well 304 is disposed below the third p+ implant region 407, the first n+ implant region 400 is connected to the first p+ implant region 401 and the anode, and the third p+ implant region 407 and the sixth n+ implant region 408 are connected to the cathode. As can be seen from fig. 4, the compact high-maintenance-voltage bidirectional SCR device provided in this embodiment adopts a Waffle-like compact layout structure, the layout center is a shared first P-well, and the periphery is divided into two regions, namely an anode region and a cathode region.
It should be noted that, referring to fig. 3, the first p+ implantation region 401, the first N well 300 and the first P well 301 form a first PNP transistor Qp1; the first N-well 300, the first P-well 301, and the second N-well 302 form a first NPN transistor Qn1; the second n+ implantation region 402, the first P well 301, and the third n+ implantation region 403 form a second NPN transistor Qn2; the third p+ implantation region 407, the second N well 302 and the first P well 301 form a second PNP transistor Qp2; the second N-well 302, the first P-well 301, and the first N-well 300 form a third NPN transistor Qn3; the fifth n+ implantation region 406, the first P well 301, and the fourth n+ implantation region 405 form a fourth NPN transistor Qn4.
According to the electrostatic protection device provided by the invention, as the base electrode and the collector electrode of the second NPN type transistor Qn2 are short-circuited with the base electrode of the first NPN type transistor Qn1, the emitter electrodes of the first NPN type transistor Qn1 and the second NPN type transistor Qn2 are short-circuited, the clamping effect is generated on the SCR device of the main channel, and the maintenance voltage can be improved; meanwhile, the second n+ injection region 402 and the fifth n+ injection region 406 are connected across the N well and the P well, so that the trigger point is transferred from the P well-N well junction to the p+ injection region-N well junction, and the trigger voltage can be reduced; in addition, since the P well regions are disposed below the first p+ injection region 401 and the third p+ injection region 407, the base concentration of the first PNP transistor Qp1 and the second PNP transistor Qp2 can be reduced, the amplification factor can be increased, and the electrostatic discharge capability can be enhanced.
Referring to fig. 5, for the compact high-maintenance voltage bidirectional SCR device according to the second embodiment of the present invention, the bidirectional SCR device in the present embodiment is a four-finger type.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (5)
1. The electrostatic protection device is characterized by comprising a substrate, wherein a deep N well is arranged in the substrate, a first N well, a first P well and a second N well are sequentially arranged in the deep N well from left to right, a first N+ injection region, a first P+ injection region and a second N+ injection region are sequentially arranged in the first N well from left to right, the second N+ injection region is bridged between the first N well and the first P well, a third N+ injection region, a second P+ injection region and a fourth N+ injection region are sequentially arranged in the first P well, a fifth N+ injection region, a third P+ injection region and a sixth N+ injection region are sequentially arranged in the second N well, the fifth N+ injection region is bridged between the first P well and the second N well, the first P well and the second N well form a first NPN type transistor, and the second N+ injection region, the first P well and the third NPN+ injection region form a second NPN type transistor;
the second N+ injection region and the fifth N+ injection region are bridged among the first N well, the first P well and the second N well, so that a trigger point is transferred from a P well-N well junction to a P+ injection region-N well junction and used for reducing trigger voltage;
the electrostatic protector is characterized in that a second P well is arranged below the first P+ injection region, a third P well is arranged below the third P+ injection region, the first N+ injection region and the first P+ injection region are connected with an anode, and the third P+ injection region and the sixth N+ injection region are connected with a cathode, so that the electrostatic protector is of a Waffle structure.
2. The electrostatic protection device of claim 1, wherein the first p+ implant region, the first N-well, and the first P-well comprise a first PNP transistor, and the third p+ implant region, the second N-well, and the first P-well comprise a second PNP transistor.
3. The electrostatic protection device of claim 2, wherein the second N-well, the first P-well, and the first N-well comprise a third NPN transistor.
4. The electrostatic protection device of claim 2, wherein the fifth n+ implant region, the first P-well, and the fourth n+ implant region comprise a fourth NPN transistor.
5. The electrostatic protection device of claim 1, wherein the substrate is a P-type substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810502138.XA CN108899314B (en) | 2018-05-23 | 2018-05-23 | Electrostatic protection device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810502138.XA CN108899314B (en) | 2018-05-23 | 2018-05-23 | Electrostatic protection device |
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| Publication Number | Publication Date |
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| CN108899314A CN108899314A (en) | 2018-11-27 |
| CN108899314B true CN108899314B (en) | 2023-05-12 |
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| CN201810502138.XA Active CN108899314B (en) | 2018-05-23 | 2018-05-23 | Electrostatic protection device |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10468513B1 (en) * | 2018-08-30 | 2019-11-05 | Amazing Microelectronic Corp. | Bidirectional silicon-controlled rectifier |
| CN109962098A (en) * | 2019-02-25 | 2019-07-02 | 中国科学院微电子研究所 | Bidirectional triode thyristor ESD-protection structure and soi structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034858A (en) * | 2010-10-28 | 2011-04-27 | 浙江大学 | Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit |
| CN102544001A (en) * | 2012-03-15 | 2012-07-04 | 电子科技大学 | SCR (Silicon Controlled Rectifier) structure for providing ESD ( Electro-Static discharge) protection for I/O (Input/Output) port of integrated circuit under all modes |
| CN102956632A (en) * | 2011-08-31 | 2013-03-06 | 北京中电华大电子设计有限责任公司 | Two-way SCR (Silicon Controlled Rectifier)-based ESD (electrostatic discharge) protection structure with low parasitic capacitance |
| CN103606548A (en) * | 2013-12-09 | 2014-02-26 | 江南大学 | Zener breakdown high-voltage ESD (Electronic Static Discharge) protective device with small-hysteresis SCR (Selective Catalytic Reduction) structure |
| CN105428354A (en) * | 2015-12-17 | 2016-03-23 | 江南大学 | Electronic static discharge (ESD) protection device with bidirectional silicon controlled rectifier (SCR) structure embedded with interdigital N-channel metal oxide semiconductor (NMOS) |
| CN205177841U (en) * | 2015-12-17 | 2016-04-20 | 江南大学 | ESD protective device with two -way SCR structure of embedded interdigital NMOS |
-
2018
- 2018-05-23 CN CN201810502138.XA patent/CN108899314B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034858A (en) * | 2010-10-28 | 2011-04-27 | 浙江大学 | Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit |
| CN102956632A (en) * | 2011-08-31 | 2013-03-06 | 北京中电华大电子设计有限责任公司 | Two-way SCR (Silicon Controlled Rectifier)-based ESD (electrostatic discharge) protection structure with low parasitic capacitance |
| CN102544001A (en) * | 2012-03-15 | 2012-07-04 | 电子科技大学 | SCR (Silicon Controlled Rectifier) structure for providing ESD ( Electro-Static discharge) protection for I/O (Input/Output) port of integrated circuit under all modes |
| CN103606548A (en) * | 2013-12-09 | 2014-02-26 | 江南大学 | Zener breakdown high-voltage ESD (Electronic Static Discharge) protective device with small-hysteresis SCR (Selective Catalytic Reduction) structure |
| CN105428354A (en) * | 2015-12-17 | 2016-03-23 | 江南大学 | Electronic static discharge (ESD) protection device with bidirectional silicon controlled rectifier (SCR) structure embedded with interdigital N-channel metal oxide semiconductor (NMOS) |
| CN205177841U (en) * | 2015-12-17 | 2016-04-20 | 江南大学 | ESD protective device with two -way SCR structure of embedded interdigital NMOS |
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