CN114975419A - Electrostatic discharge protection circuit structure - Google Patents

Electrostatic discharge protection circuit structure Download PDF

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Publication number
CN114975419A
CN114975419A CN202110187198.9A CN202110187198A CN114975419A CN 114975419 A CN114975419 A CN 114975419A CN 202110187198 A CN202110187198 A CN 202110187198A CN 114975419 A CN114975419 A CN 114975419A
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region
esd
conductivity
doped regions
well region
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陈哲宏
陈永初
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Macronix International Co Ltd
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses an electrostatic discharge protection circuit structure, which comprises: a substrate; a first well region of a first conductivity type disposed in the substrate; a second well region of a second conductivity type disposed in the first well region; a first ring region of the first conductivity type disposed in the first well region and coupled to a ground terminal; a plurality of first conductive type doped regions disposed in the second well region and including at least a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to a high level terminal; and a plurality of second conductive type doped regions disposed in the first well region and at least including a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to a ground terminal. At least a second region of the plurality of first conductivity-type doped regions and the second region of the plurality of second conductivity-type doped regions are electrically connected to each other.

Description

Electrostatic discharge protection circuit structure
Technical Field
The present invention relates to an electrostatic discharge protection circuit, and more particularly, to an electrostatic discharge protection circuit with a high holding voltage.
Background
In a semiconductor Integrated Circuit (IC), an electrostatic discharge protection circuit is often provided between an internal circuit and an input pad in order to prevent damage to the internal circuit due to static electricity. Among them, the SCR circuit has excellent high current behavior and can provide good area gain, and thus is often used as an electrostatic discharge protection circuit.
SCR circuits are generally very robust as is well known, but have a deep snapback (deep snapback) effect due to their circuit characteristics, so that SCRs can only have a low holding voltage. This problem will create a latch-up (LU) effect problem. Therefore, if the SCR circuit is triggered by noise during the operation of the IC circuit, the SCR circuit will burn out (burn out), which affects the protection of the esd.
To solve this problem, the prior art provides two solutions, one is the method shown in fig. 1A, i.e. increasing the trigger current; that is, the SCR circuit is not easily triggered to cause malfunction. The other is the method shown in fig. 1B, i.e., increasing the holding voltage.
However, there is still a need in the art to provide an esd protection circuit that can increase the holding voltage and also reduce the trigger voltage without causing malfunction.
Disclosure of Invention
According to an embodiment of the present invention, an esd protection circuit is provided, which includes: a substrate; a first well region of a first conductivity type disposed in the substrate; a second well region of a second conductivity type disposed in the first well region; a first ring region of the first conductivity type disposed in the first well region and coupled to a ground terminal; a plurality of first conductive type doped regions disposed in the second well region and including at least a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to a high-level terminal; and a plurality of second conductive type doped regions disposed in the first well region and at least including a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to the ground terminal. At least the second regions of the plurality of first conductivity-type doped regions and the second regions of the plurality of second conductivity-type doped regions are electrically connected to each other. The first region, the second region and the second well region of the plurality of first-conductivity-type doped regions constitute a first parasitic transistor, and the second region, the third region and the first well region of the plurality of second-conductivity-type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path. The second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path. The second region, the third region and the second well region of the plurality of first-conductivity-type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the plurality of second-conductivity-type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path.
According to an embodiment of the present invention, the esd protection circuit may further include: a second ring region of the second conductivity type disposed in the second well region, surrounding the plurality of first conductivity type doped regions, and coupled to the high-voltage terminal; and a third ring region of the first conductivity type, disposed in the first well region, surrounding the plurality of second conductivity type doped regions, and connected to the ground terminal.
According to an embodiment of the present invention, in the esd protection circuit, the first conductive type is P-type, the second conductive type is N-type, and the substrate is P-type.
According to an embodiment of the present invention, in the esd protection circuit, each of the first conductive type doping regions is disposed adjacent to each other at a certain interval in a first direction of the substrate and extends in a second direction perpendicular to the first direction.
According to an embodiment of the present invention, in the esd protection circuit, the trigger voltage of the first esd path is greater than the trigger voltage of the second esd path, and the trigger voltage of the second esd path is greater than the trigger voltage of the third esd path.
According to an embodiment of the present invention, in the esd protection circuit, the corresponding holding voltages of the first esd path, the second esd path and the third esd path are substantially equal.
According to an embodiment of the present invention, in the esd protection circuit, the fourth parasitic transistor and the fifth parasitic transistor of the third esd path form a scr.
According to another embodiment of the present invention, an esd protection circuit structure is provided, which includes: a substrate; a first well region of a first conductivity type disposed in the substrate; a second well region of a second conductivity type disposed in the first well region; a first ring region of the first conductivity type disposed in the first well region and coupled to a ground terminal; a plurality of first conductive type doped regions disposed in the second well region and including at least first, second and third regions in sequence, wherein the first and third regions are coupled to a high level terminal, and a gate is disposed on the substrate and between each of the first, second and third regions; and a plurality of second conductive type doped regions disposed in the first well region and including at least first, second and third regions in sequence, wherein the first and third regions are coupled to the ground, and a gate is disposed on the substrate and between each of the first, second and third regions. At least the second regions of the plurality of first conductivity-type doped regions and the second regions of the plurality of second conductivity-type doped regions are electrically connected to each other. The first region, the second region and the second well region of the plurality of first-conductivity-type doped regions constitute a first parasitic transistor, and the second region, the third region and the first well region of the plurality of second-conductivity-type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path. The second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path. The second region, the third region, and the second well region of the plurality of first conductivity-type doped regions constitute a fourth parasitic transistor, and the first region, the second region, and the first well region of the plurality of second conductivity-type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path.
According to an embodiment of the present invention, the esd protection circuit may further include: a second ring region of the second conductivity type disposed in the second well region, surrounding the plurality of first conductivity type doped regions, and connected to the high level connection terminal; and a third ring region of the first conductivity type, disposed in the first well region, surrounding the plurality of second conductivity type doped regions, and connected to the ground terminal.
According to an embodiment of the present invention, in the esd protection circuit, the first conductive type is P-type, the second conductive type is N-type, and the substrate is P-type.
According to an embodiment of the present invention, in the esd protection circuit, the gates disposed between every two of the first, second and third regions of the first conductive type doped regions are used as PMOS trigger nodes, and the gates disposed between every two of the first, second and third regions of the second conductive type doped regions are used as NMOS trigger nodes.
According to an embodiment of the present invention, in the esd protection circuit, each of the plurality of first conductive type doping regions is disposed at a certain interval in a first direction of the substrate and extends in a second direction perpendicular to the first direction.
According to an embodiment of the present invention, in the esd protection circuit, the trigger voltage of the first esd path is greater than the trigger voltage of the second esd path, and the trigger voltage of the second esd path is greater than the trigger voltage of the third esd path.
According to an embodiment of the present invention, in the esd protection circuit, the corresponding holding voltages of the first esd path, the second esd path and the third esd path are substantially equal.
According to an embodiment of the present invention, in the esd protection circuit, the fourth parasitic transistor and the fifth parasitic transistor of the third esd path form a scr.
In view of the above, the esd protection circuit structure according to the embodiment of the invention provides three esd paths with different trigger voltages, so that esd can be further effectively performed. In addition, the parasitic silicon controlled rectifier part in the electrostatic discharge protection circuit structure is triggered by the secondary current, so that the transistor interval in the parasitic silicon controlled rectifier can be increased, and the holding voltage can be further increased. In addition, the area of the esd protection circuit structure can be further reduced by improving the esd performance.
Drawings
Fig. 1A and 1B illustrate two known approaches to solving the problem of SCR circuit latch-up.
Fig. 2 is a top view of an esd protection circuit according to an embodiment of the invention.
FIG. 3A is a cross-sectional doping diagram of the ESD protection circuit cut from section line A-A' of FIG. 2.
FIG. 3B is a schematic diagram of the doping and parasitic transistors of the cross-sectional view of FIG. 3A.
Fig. 4A is a schematic diagram of an equivalent circuit and a discharge path of fig. 3B according to an embodiment of the invention.
Fig. 4B is a schematic diagram of a discharge path according to an embodiment of the invention.
Fig. 5 is a Transmission Line Pulse (TLP) current-voltage graph of an esd protection circuit according to an embodiment of the invention.
FIG. 6A is a schematic cross-sectional doping diagram of an ESD protection circuit according to another embodiment of the present invention.
FIG. 6B is a schematic diagram of the doping and parasitic transistors of the cross-sectional view of FIG. 6A.
FIG. 6C is a schematic diagram of the equivalent circuit and the discharge path of FIG. 6B.
[ description of symbols ]
100. 200: substrate
102. 202: a first well region
104. 204: second well region
110. 210: first ring zone
112. 212: second annular region
114. 214: multiple first conductive type doped regions
114a, 114b, 114 c: first, second, and third regions
214a, 214b, 214 c: first, second, and third regions
122. 224: multiple second conductive type doped regions
122a, 122b, 122 c: first, second, and third regions
224a, 224b, 224 c: first, second, and third regions
120. 210: third ring zone
216a, 216b, 226a, 226 b: grid electrode
P11, P12, P31, P32: parasitic transistor
N11, N12, N31, N32: parasitic transistor
P2, P4: parasitic transistor
ESD 1-ESD 3: first to third electrostatic discharge currents
GND: grounding terminal
Detailed Description
Fig. 2 is a top view of an esd protection circuit according to an embodiment of the invention. FIG. 3A is a cross-sectional doping diagram of the ESD protection circuit cut from section line A-A' of FIG. 2. The semiconductor structure of the esd protection circuit of the present invention will be described with reference to fig. 2 and fig. 3A.
As shown in fig. 2 and 3A, the esd protection circuit includes a substrate 100, a first well 102, a second well 104, a first ring 110, a plurality of first conductive type doped regions 114 and a plurality of second conductive type doped regions 122. The substrate 100 may have a first conductivity type, such as P-type doping. The first well region 102 has the same first conductivity type as the substrate 100 and is disposed in the substrate 100. The second well region 104, having a second conductivity type, is disposed in the first well region 102. Here, the second conductivity type is, for example, N-type doping.
In addition, the first ring region 110 has the first conductivity type, is disposed in the first well region 102, and is coupled to the ground GND. Here, the ground GND may be at the lowest level of the entire circuit system. In addition, although the first ring region 110 shown in fig. 2 has a substantially square or rectangular structure, it is not limited to this shape, and it can be designed according to the actual requirement.
In addition, the first conductive type doping regions 114 may include a plurality of regions spaced apart from each other, and are disposed in the first well region 102, taking the first region 114a, the second region 114b, and the second region 114c as an illustrative example. Similarly, the plurality of second conductive type doping regions 122 may also include a plurality of regions and are spaced apart from each other, and are disposed in the first well region 102. In the present embodiment, the first region 122a, the second region 122b and the third region 122 are taken as an illustrative example. Regarding the plurality of first-conductivity-type doped regions 114 and the plurality of second-conductivity-type doped regions 122, those skilled in the art can change or modify the number and the electrical connection manner thereof based on the description of the embodiment without departing from the scope of the invention.
In addition, as shown in fig. 2, each of the plurality of first conductive type doping regions 114 (e.g., 114a, 114b, 114c) is sequentially disposed in a first direction X of the substrate 100 at a certain interval, and extends in a second direction Y perpendicular to the first direction X. Similarly, each of the plurality of second conductive type doping regions 122 (e.g., 122a, 122b, 122c) is sequentially disposed at a certain interval in the first direction X of the substrate 100 and extends in a second direction Y perpendicular to the first direction X.
In addition, as shown in fig. 3A, at least the second regions 114b of the first conductive-type-doped regions 114 and the second regions 122b of the second conductive-type-doped regions 122 are electrically connected to each other. In addition, the first region 114a and the third region 114c of the plurality of first conductive type doping regions 114 are coupled to the high level end. The high voltage terminal may be an input pad, a power rail (power rail), or the like, and is simply a terminal of the circuit having a relatively high level. The first region 122a and the third region 122c of the plurality of second conductive type doped regions 122 are coupled to the ground GND.
In addition, according to an embodiment of the present invention, the esd protection circuit structure may further include a second ring region 112 and a third ring region 120. The second ring region 112, of the second conductivity type, is disposed in the second well 104, surrounds the plurality of first-conductivity-type doped regions 114, and is coupled to a high-voltage terminal. The third ring region 120, having the first conductivity type, is disposed in the first well 102, surrounds the plurality of second-conductivity-type doped regions 122, and is coupled to the ground GND. In addition, although the second ring region 112 and the third ring region 120 are shown in fig. 2 as having a substantially square or rectangular structure, the shape is not limited thereto, and may be designed according to the actual requirement.
The circuit structure and operation of the esd protection circuit according to the embodiment of the present invention are described next. FIG. 3B is a schematic diagram of the doping and parasitic transistors of the cross-sectional view of FIG. 3A. In the following description, the first conductivity type and the second conductivity type will be described as P-type doping and N-type doping, respectively.
As shown in fig. 3B, although the N-doped ring of the second ring region 112 and the P-doped ring of the third ring region 120 are illustrated, the second ring region 112 and the third ring region 120 may be selectively disposed as described above. In addition, although P + doped regions and N + doped regions are illustrated, the P + or N + doping is not required in the embodiment, and only this type of doping is required, for example, a relatively light doping, such as P-or N-can be adopted.
As shown in fig. 3B, a first region (P + doped in this example) 114a, a second region (P + doped in this example) 114B and a second well region (N well in this example) 104 in the plurality of first conductive type doped regions 114 constitute a first parasitic transistor P11 (i.e., a parasitic PNP transistor), and a second region (N + doped in this example) 122B, a third region (N + doped in this example) 112c and a first well region (P well in this example) 102 in the plurality of second conductive type doped regions 122 constitute a second parasitic transistor N11 (i.e., an NPN parasitic transistor), thereby constituting a first electrostatic discharge path ESD 1. The second well region 102, the substrate 100 and the first well region 102 constitute a third parasitic transistor P2 (i.e., a parasitic PNP transistor), thereby constituting a second electrostatic discharge path ESD 2. The second and third regions of the plurality of first conductive type doped regions 114 and the second well region 104 form a fourth parasitic transistor P12 (i.e., a parasitic PNP transistor), and the first and second regions 122a and 122b of the plurality of second conductive type doped regions 122 and the first well region 102 form a fifth parasitic transistor N12, thereby forming a third electrostatic discharge path ESD 3. The fourth parasitic transistor P12 and the fifth parasitic transistor N12 form a SCR.
Fig. 4A is a schematic diagram of an equivalent circuit and a discharge path of fig. 3B according to an embodiment of the invention. Fig. 4B is a schematic diagram of a discharge path according to an embodiment of the invention. The equivalent circuit diagram of the esd protection circuit structure depicted in fig. 3B is shown in fig. 4A. According to the embodiment of the invention, three first to third electrostatic discharge paths ESD1 to ESD3 with different trigger voltages are provided between the high-level terminal and the ground terminal GND. The first ESD path ESD1 is formed by the first parasitic transistor P11 and the second parasitic transistor N11 coupled between the high-level terminal and the ground terminal GND, and is the discharge path triggered at the earliest time. The second ESD path ESD 2 is formed by a third parasitic transistor P2 (PNP type) coupled between the high-level terminal and the ground terminal GND, and is a discharge path that is triggered continuously. The third electrostatic discharge path ESD 3(SCR type) is formed by the fourth parasitic transistor P12 and the fifth parasitic transistor N12 coupled between the high level terminal and the ground terminal GND, and is a discharge path that is finally triggered.
As shown in fig. 4A and 4B, when an ESD event occurs at a high-level terminal (e.g., an input pad), the first ESD path ESD1 is triggered to turn on first, and the turn-on voltage is the breakdown voltage of the first parasitic transistor P11 and the second parasitic transistor N12. Thereby, the ESD current can be conducted to the ground GND through the first ESD path ESD 1. As shown in fig. 3A, the ESD current enters from the first region 114a of the first conductive type doped regions 114, passes through the second region 114b, enters the second region 122b of the second conductive type doped regions 122 through electrical connection, and then discharges to the ground GND through the third region 122 c.
Then, after the first ESD path ESD1 is turned on, the secondary current will continuously turn on the second ESD path ESD 2 and the second ESD path ESD 3. After the second ESD path ESD 2 is triggered and turned on, the discharge current is discharged from the first ring region (P + doping) 110 to the ground GND through the first well region 102 from the second well region 104 (or from the N + doping 112 of the second ring region into the second well region 104). Then, after the third ESD path ESD3 is turned on, the discharge current enters from the second region 114b of the first conductive type doped regions 114, passes through the third region 114c, enters the second region 122b of the second conductive type doped regions 122 through electrical connection, and then is discharged to the ground GND through the first region 122 a.
As described above, according to the ESD protection circuit of the embodiment of the invention, since the third ESD path ESD3 is triggered by the secondary current, the interval d (see fig. 3A and 3B) between the parasitic SCR constituting the third ESD path ESD3 can be further increased, and thus a higher holding voltage characteristic can be obtained.
Fig. 5 is a Transmission Line Pulse (TLP) current-voltage graph of an esd protection circuit according to an embodiment of the invention. As shown in fig. 5, the ESD protection circuit of the present embodiment may have three triggering stages, which correspond to the first to third ESD paths ESD1 to ESD3, respectively. As can be seen from fig. 5, the trigger voltage Vt of the first ESD path ESD1 is about 23.3V and the holding voltage Vh is about 18.3V, the trigger voltage Vt of the second ESD path ESD 2 is about 18.88V and the holding voltage Vh is about 18V, and the trigger voltage Vt of the third ESD path ESD3 is about 19.66V and the holding voltage Vh is about 18.37V. It can be seen that the trigger voltage of the first electrostatic discharge path is greater than the trigger voltage of the second electrostatic discharge path, and the trigger voltage of the second electrostatic discharge path is less than the trigger voltage of the third electrostatic discharge path. In addition, the holding voltages of the first to third electrostatic discharge paths are substantially equal. From this result, it can be seen that the esd protection circuit according to the embodiment of the present invention can be applied to the operation with higher holding voltage.
In summary, in an experimental example of the esd protection circuit according to the embodiment of the present invention, the breakdown voltage is about 23V, and can reach 1.953V/μm under the Human Body Model (HBM) test 2 . Compared with the current ESD protection circuit, the Human Body Model (HBM) test is only 0.549V/μm 2 . In terms of performance, the performance of the ESD protection circuit of this embodiment can be increased by at least three times.
In addition, according to the experimental result of the electrostatic discharge protection circuit of the embodiment of the present invention, the area is only 4095 μm 2 About, at least 9000 μm compared to the current general area size 2 Area of the present embodimentThe area of the disclosed ESD protection circuit can be reduced by nearly half.
Next, another embodiment of the present invention will be described. FIG. 6A is a schematic cross-sectional doping diagram of an ESD protection circuit according to another embodiment of the present invention. FIG. 6B is a schematic diagram of the doping and parasitic transistors of the cross-sectional view of FIG. 6A. FIG. 6C is a schematic diagram of the equivalent circuit and the discharge path of FIG. 6B.
In addition, the embodiment shown in fig. 6A to 6C is different from the above-mentioned embodiments in that the two doped regions in the well region form a gate structure, and the structure of the rest portion is substantially the same or similar. This will be described below with reference to fig. 6A to 6C.
As shown in fig. 6A, the esd protection circuit includes a substrate 200, a first well 202, a second well 204, a first ring region 210, a plurality of first conductive type doped regions 214, and a plurality of second conductive type doped regions 224. The substrate 200 may have a first conductivity type, such as P-type doping. The first well region 202 has the same first conductivity type as the substrate 200 and is disposed in the substrate 200. The second well region 204, having a second conductivity type, is disposed in the first well region 202. Here, the second conductivity type is, for example, N-type doping.
In addition, the first ring region 210 has the first conductivity type, is disposed in the first well 202, and is coupled to the ground GND. Here, the ground GND may be at the lowest level of the entire circuit system. As in the previous embodiments, the first ring region 210 may have a substantially square or rectangular structure, but is not limited to this shape, and may be designed according to the actual requirement.
In addition, the plurality of first conductive type doping regions 214 may include a plurality of regions spaced apart from each other, and are disposed in the first well region 202, taking the first region 214a, the second region 214b, and the second region 214c as an illustrative example in this embodiment. Similarly, the plurality of second conductive type doping regions 224 may also include a plurality of second conductive type doping regions spaced apart from each other and disposed in the first well region 202. In the present embodiment, the first region 224a, the second region 224b and the second region 224c are taken as an illustrative example. Regarding the first conductive-type doped regions 214 and the second conductive-type doped regions 224, those skilled in the art can appropriately change or modify the number and the electrical connection manner thereof based on the description of the embodiment without departing from the scope of the invention.
In addition, as shown in fig. 6A, the gate electrodes 216A and 216b are disposed between each of the first, second and third regions 214a, 214b and 214c of the plurality of first conductive type doped regions 214. The gate electrodes 226a and 226b are disposed between each of the first, second and third regions 224a, 224b and 224c of the plurality of second-conductivity-type-doped regions 224.
In addition, as shown in fig. 6A, at least the second regions 214b of the first conductive-type-doped regions 214 and the second regions 224b of the second conductive-type-doped regions 224 are electrically connected to each other. In addition, the first region 214a and the third region 214c of the plurality of first conductive type doping regions 214 are coupled to the high level end. The first region 224a and the third region 224c of the plurality of second conductive type doped regions 224 are coupled to the ground GND.
In addition, according to an embodiment of the present invention, the esd protection circuit structure may further include a second ring region 212 and a third ring region 222. The second ring region 212, which is of the second conductivity type, is disposed in the second well region 204, surrounds the plurality of first-conductivity-type doped regions 214, and is coupled to the high-voltage terminal. The third ring region 222 of the first conductivity type is disposed in the first well 202, surrounds the plurality of second-conductivity-type doped regions 224, and is coupled to the ground GND. Similarly, the second ring area 112 and the third ring area 120 may be a substantially square or rectangular structure, but are not limited to this shape, and they may be designed according to the actual requirement. In addition, as mentioned above, the second ring region 212 and the third ring region 222 can be selectively disposed.
As an example, fig. 6B illustrates that the first conductivity type and the second conductivity type will be P-type doped and N-type doped, respectively. In this example, gates 216a, 216b may serve as trigger nodes for PMOS transistors, while gates 226a, 226b may serve as trigger nodes for NMOS transistors. As shown in fig. 6B, a first region (P + doped in this example) 214a, a second region (P + doped in this example) 214B, a second well region (N well in this example) 204 and a gate 216a in the plurality of first conductive type doped regions 214 constitute a first parasitic transistor P31 (i.e., a parasitic PMOS transistor), and a second region (N + doped in this example) 224B, a third region (N + doped in this example) 224c, a gate 226B and a first well region (P well in this example) 202 in the plurality of second conductive type doped regions 224 constitute a second parasitic transistor N31 (i.e., a parasitic NMOS transistor), thereby constituting a first electrostatic discharge path ESD 1. The second well region 202, the substrate 200 and the first well region 202 form a third parasitic transistor P4 (i.e., a parasitic PNP transistor), thereby forming a second electrostatic discharge path ESD 2. The second region 214b, the third region 214c, the gate electrode 216b and the second well region 204 of the plurality of first conductive-type doped regions 214 constitute a fourth parasitic transistor P32 (i.e., a parasitic PNP transistor), and the first region 224a, the second region 224b, the gate electrode 226a and the first well region 202 of the plurality of second conductive-type doped regions 224 constitute a fifth parasitic transistor N32, thereby constituting a third electrostatic discharge path ESD 3. The fourth parasitic transistor P32 and the fifth parasitic transistor N32 form a SCR.
In addition, the equivalent circuit diagram of the ESD protection circuit structure shown in fig. 6B is shown in fig. 6C, except that the gates 216a, 216B, 226a, and 226C are added so that the parasitic transistor constituting the first ESD path ESD1 is composed of the parasitic NMOS transistor N31 and the parasitic PMOS transistor P31, and the other parasitic transistor components are the same. In addition, in this embodiment, the triggering manner and the operation manner of the first to third electrostatic discharge paths ESD1 to ESD3 are the same as those of the previous embodiment, and therefore, the description thereof is omitted.
In summary, according to the esd protection circuit structure of the embodiments of the invention, three esd paths with different trigger voltages are provided, so that esd can be further effectively performed. In addition, the parasitic silicon controlled rectifier part in the electrostatic discharge protection circuit structure is triggered by the secondary current, so that the transistor interval in the parasitic silicon controlled rectifier can be increased, and the holding voltage can be further increased. In addition, the area of the ESD protection circuit structure can be further reduced by improving the ESD performance.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (15)

1. An ESD protection circuit structure, comprising:
a substrate;
a first well region of a first conductivity type disposed in the substrate;
a second well region of a second conductivity type disposed in the first well region;
a first ring region of the first conductivity type disposed in the first well region and coupled to a ground terminal;
a plurality of doped regions of the first conductivity type disposed in the second well region and including at least a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to a high-level terminal; and
a plurality of second conductive type doped regions disposed in the first well region and including at least a first region, a second region and a third region in sequence, wherein the first region and the third region are coupled to the ground terminal,
wherein at least the second regions of the plurality of first conductivity-type doped regions and the second regions of the plurality of second conductivity-type doped regions are electrically connected to each other,
wherein the first region, the second region and the second well region of the plurality of first-conductivity-type doped regions constitute a first parasitic transistor, the second region, the third region and the first well region of the plurality of second-conductivity-type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path,
the second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path, an
The second region, the third region and the second well region of the plurality of first-conductivity-type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the plurality of second-conductivity-type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path.
2. The esd-protection circuit structure of claim 1, further comprising:
a second ring region of the second conductivity type disposed in the second well region, surrounding the plurality of first conductivity type doped regions, and connected to the high level connection terminal; and
and a third ring region of the first conductivity type, disposed in the first well region, surrounding the plurality of second conductivity type doped regions, and connected to the ground terminal.
3. The esd-protection circuit structure of claim 2, wherein the first conductivity type is P-type, the second conductivity type is N-type, and the substrate is P-type.
4. The ESD protection circuit structure of claim 1,
each of the plurality of first conductive type doped regions is disposed at a certain interval in a first direction of the substrate and extends in a second direction perpendicular to the first direction.
5. The esd-protection circuit structure of claim 1, wherein the trigger voltage of the first esd path is greater than the trigger voltage of the second esd path, and the trigger voltage of the second esd path is less than the trigger voltage of the third esd path.
6. The ESD protection circuit structure of claim 5, wherein the holding voltages of the first ESD path, the second ESD path and the third ESD path are substantially equal.
7. The esd protection circuit structure of claim 1, wherein the fourth and fifth parasitic transistors of the third esd path form a silicon controlled rectifier.
8. An electrostatic discharge protection circuit structure, comprising:
a substrate;
a first well region of a first conductivity type disposed in the substrate;
a second well region of a second conductivity type disposed in the first well region;
a first ring region of the first conductivity type disposed in the first well region and coupled to a ground terminal;
a plurality of first conductive type doped regions disposed in the second well region and including at least first, second and third regions in sequence, wherein the first and third regions are coupled to a high level terminal, and a gate is disposed on the substrate and between each of the first, second and third regions; and
a plurality of second conductive type doped regions disposed in the first well region and including at least first, second and third regions in sequence, wherein the first and third regions are coupled to the ground, and a gate is disposed on the substrate and between every two of the first, second and third regions,
wherein at least the second regions of the plurality of first conductivity-type doped regions and the second regions of the plurality of second conductivity-type doped regions are electrically connected to each other,
wherein the first region, the second region and the second well region of the plurality of first-conductivity-type doped regions constitute a first parasitic transistor, the second region, the third region and the first well region of the plurality of second-conductivity-type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path,
the second well region, the substrate and the first well region form a third parasitic transistor, thereby forming a second electrostatic discharge path, an
The second region, the third region and the second well region of the plurality of first-conductivity-type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the plurality of second-conductivity-type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path.
9. The esd-protection circuit structure of claim 8, further comprising:
a second ring region of the second conductivity type disposed in the second well region, surrounding the plurality of first-conductivity-type doped regions, and connected to the high-voltage-connection terminal; and
and a third ring region of the first conductivity type, disposed in the first well region, surrounding the plurality of second-conductivity-type doped regions, and connected to the ground terminal.
10. The esd-protection circuit structure of claim 9, wherein the first conductivity type is P-type, the second conductivity type is N-type, and the substrate is P-type.
11. The esd protection circuit structure of claim 10, wherein the gates of the first, second and third regions of the plurality of first conductivity-type doped regions disposed in between are configured as PMOS trigger nodes, and the gates of the first, second and third regions of the plurality of second conductivity-type doped regions disposed in between are configured as NMOS trigger nodes.
12. The ESD protection circuit structure of claim 8,
each of the plurality of first conductive type doped regions is disposed at intervals in a first direction of the substrate and extends in a second direction perpendicular to the first direction.
13. The esd-protection circuit structure of claim 8, wherein the trigger voltage of the first esd path is greater than the trigger voltage of the second esd path, and the trigger voltage of the second esd path is less than the trigger voltage of the third esd path.
14. The esd protection circuit structure of claim 13, wherein the respective holding voltages of the first esd path, the second esd path and the third esd path are substantially equal.
15. The esd-protection circuit structure of claim 8, wherein the fourth and fifth parasitic transistors of the third esd path form a silicon controlled rectifier.
CN202110187198.9A 2021-02-18 2021-02-18 Electrostatic discharge protection circuit structure Pending CN114975419A (en)

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CN202110187198.9A CN114975419A (en) 2021-02-18 2021-02-18 Electrostatic discharge protection circuit structure

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Application Number Priority Date Filing Date Title
CN202110187198.9A CN114975419A (en) 2021-02-18 2021-02-18 Electrostatic discharge protection circuit structure

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